The Wio Terminal includes a RealTek RTL8720D as a companion to the main chip to provide WiFi and Bluetooth capabilities via eRPC over a UART connection. The WIO Terminal schematic labels some pins as the RXD/TXD for the UART, and that was captured in the board definition for CircuitPython. However, these pins may be used for logging in another mode, but they are not the main pins used to communicate with the RTL chip. The correct configuration is RX on PC24/pad 2 and TX on PB24/pad 0 of SERCOM 0. The comments on the pin definitions now reflect this situation, for anyone trying to get the WiFi/BLE to work on the Wio Terminal.
PicoDVI in CP support 640x480 and 800x480 on Feather DVI, Pico and
Pico W. 1 and 2 bit grayscale are full resolution. 8 and 16 bit
color are half resolution.
Memory layout is modified to give the top most 4k of ram to the
second core. Its MPU is used to prevent flash access after startup.
The port saved word is moved to a watchdog scratch register so that
it doesn't get overwritten by other things in RAM.
Right align status bar and scroll area. This normally gives a few
pixels of padding on the left hand side and improves the odds it is
readable in a case. Fixes#7562
Fixes c stack checking. The length was correct but the top was being
set to the current stack pointer instead of the correct top.
Fixes#7643
This makes Bitmap subscr raise IndexError instead of ValueError
when the index arguments are wrong.
Doing a squash merge to avoid having the `slc_cli_linux` .zip files in the history. They were added in one commit and removed and replaced with a submodule in another.
* Initial commit for xg24
* Fix SLC issue
* Fix SLC extract fail
* Change board's name
* Correct spelling of code
Build immediately after slc generate
* Remove VID and PID
* Change creator and creation id
* Apply new creator_id and creation_id
* Update makefile, error message, mcu_processor function
* Update mpconfigboard.mk
* Update Board extensions, PORT_DEPS
* Update makefile
* Add exclude_patterns
* Show java, jinja2 version
* Show path for debugging CI
* Add requirements-dev for slc
* Add PATH slc_cli
* Update background function
* Add jinja2 PATH
* Show PATH
* Update jinja2 path
* Update jinja2 path
* Update jinja2 path
* Update jinja2 path
* Change slc folder
* Change markupsafe folder
* Add symbolic link for slc
* Update makefile
* Update makefile
* Update MX25R3235F.toml from submodule nvm.toml
* alphabetize the list
* Remove slc_cli_linux folder
* Update slc_cli submodule
---------
Co-authored-by: Chat Nguyen <cvnguyen@silabs.com>
Co-authored-by: silabs-ChatNguyen <chat.nguyen@silabs.com>
Co-authored-by: silabs-ChatNguyen <126220343+silabs-ChatNguyen@users.noreply.github.com>
Previous pins definition stated that the UART1 RTS and CTS were not connected. They are connected and can currently be used via A1 and PWM0 respectively. To make things a little clearer, enabling the RTS1/CTS1.
In #7497 port_background_task was renamed to port_background_tick
but the actual call site wasn't changed. This meant that it was
no longer called!
Rename more functions from task to tick to make it clearer which is
which.
Fixes polling thread looping forever hangs preventing new connections.
Don't lose listening sockets on mp resets and re-init.
Keep better separation of "system" and "user" sockets.
Track socket states to prevent re-use of sockets before closed.
Close REST socket when transaction completes. No post-init.
Remove unnecessary state flags.
In contrast to MidiTrack, this can be controlled from Python code,
turning notes on/off as desired.
Not tested on real HW yet, just the acceptance test based on checking
which notes it thinks are held internally.
This makes all the samples from Dan's collection register as 440Hz
when playing on pwmio or i2sout, using https://webaudiodemos.appspot.com/pitchdetect/index.html
to detect the frequency played (all should show as A 440Hz; an error
of up to 20 "cents" should be treated as OK)
There's an audible carrier with PWM output and the 8kHz samples. This is
probably a limitation of the peripheral which is documented as being for
input signals of 44 kHz or 48 kHz; the carrier frequency is a fixed
multiple of the sample frequency.
Closes#7800
.. via a peripheral known as the "MQS" (medium quality sound). It uses an
~192kHz PWM signal to generate audio. It sounds OK on a small speaker with
no amplifier. There's a small pop when starting/stopping audio, as is
typical.
.. and write a general 'pin change interrupt' facility to power it
This uses the same quadrature state machine as atmel-samd, nrf, and
rp2040. The 1011 doesn't have a dedicated encoder peripheral, so we
go the pin-change + software route.
This reverts commit 7e6e824d56.
Fixes#7770
The change in #7623 needs to be revered; the raise-site added in #7632
is the correct one and the one in socketpool needs to be reverted.
This is not affecting 8.0.x because #7623 was not back-ported to there
before we realized it was not a full fix.
Both #7770 and #7606 should be re-tested. I didn't test.
tested on metro m7 (green prototype version) with max98357a i2s amplifier and the following test code:
```py
import board
import time
import digitalio
from audiobusio import I2SOut
from audiocore import RawSample
from microcontroller import pin
from ulab import numpy as np
n = np.array(np.sin(np.linspace(0, np.pi*2, 218, endpoint=False)) * 200, dtype=np.int16)
print(n)
r = RawSample(n, sample_rate=8000, channel_count=2)
def main():
with digitalio.DigitalInOut(board.LED) as l:
l.switch_to_output(True)
value = False
while True:
with I2SOut(pin.GPIO_06, pin.GPIO_07, pin.GPIO_04) as i:
time.sleep(.01)
l.value = value = not value
i.play(r, loop=True)
print(i.playing)
time.sleep(.5)
i.stop()
print("STOPPED")
print(i.playing)
time.sleep(.5)
i.play(r, loop=True)
print(i.playing)
print("PLAY AGAIN")
time.sleep(.5)
time.sleep(1)
```
Only stereo, 16-bit, raw samples were tested; the sample rate is actually fixed
at 48kHz in the core right now. There is more to do, but the basics work.
# Conflicts:
# ports/mimxrt10xx/Makefile
# ports/mimxrt10xx/mpconfigport.mk
* Enable dcache for OCRAM where the VM heap lives.
* Add CIRCUITPY_SWO_TRACE for pushing program counters out over the
SWO pin via the ITM module in the CPU. Exempt some functions from
instrumentation to reduce traffic and allow inlining.
* Place more functions in ITCM to handle errors using code in RAM-only
and speed up CP.
* Use SET and CLEAR registers for digitalio. The SDK does read, mask
and write.
* Switch to 2MiB reserved for CircuitPython code. Up from 1MiB.
* Run USB interrupts during flash erase and write.
* Allow storage writes from CP if the USB drive is disabled.
* Get perf bench tests running on CircuitPython and increase timeouts
so it works when instrumentation is active.
