In particular, this makes the L4 .isr_vector section 16K in size so it's
the same as the F4/F7 MCUs. The patch also moves the L4 filesystem to
the end of flash, which allows for 512K filesystem on the 1Mb devices
like the STM32L476DISC.
This patch adds support to fsusermount for multiple block devices
(instead of just one). The maximum allowed is fixed at compile time by
the size of the fs_user_mount array accessed via MP_STATE_PORT, which
in turn is set by MICROPY_FATFS_VOLUMES.
With this patch, stmhal (which is still tightly coupled to fsusermount)
is also modified to support mounting multiple devices And the flash and
SD card are now just two block devices that are mounted at start up if
they exist (and they have special native code to make them more
efficient).
You can now create (singleton) objects representing the flash and SD
card, using:
flash = pyb.Flash()
sdcard = pyb.SDCard()
These objects provide the block protocol.
USB serial is now working for F7.
Internal file storage is now working for F7. The flash is laid out a bit
differently to the F4 - 4 x 32K, 1 x 128K with the rest 256K, so the
internal storage is 96K.
Added more pind definitions for STM32F7DISC board. Made USART1 be the
default HWUART repl. The STLINK usb connector also looks like a USB
serial port which is attached to USART1 on the STM32F7DISC.
When enabled this allows the internal storage to be split over 2
contiguous regions of flash (two segments), and so the storage can be
increased.
This option is disabled by default, giving original behaviour.
Blanket wide to all .c and .h files. Some files originating from ST are
difficult to deal with (license wise) so it was left out of those.
Also merged modpyb.h, modos.h, modstm.h and modtime.h in stmhal/.
Internal flash used for the filesystem is now written (from the cache)
only after a 5s delay, or when a file is closed, or when the drive is
unmounted from the host. This delay means that multiple writes can
accumulate in the cache, and leads to less writes to the flash, making
it last longer.
It's implemented by a high-priority interrupt that takes care of flash
erase and write, and flushing the cache.
This is still only an interim solution for the flash filesystem. It
eventually needs to be replaced with something that uses less RAM for
the cache, something that can use more of the flash, and something that
does proper wear levelling.
