Commit Graph

3 Commits

Author SHA1 Message Date
Scott Shawcroft
5bb8a7a7c6
Improve iMX RT performance
* Enable dcache for OCRAM where the VM heap lives.
* Add CIRCUITPY_SWO_TRACE for pushing program counters out over the
  SWO pin via the ITM module in the CPU. Exempt some functions from
  instrumentation to reduce traffic and allow inlining.
* Place more functions in ITCM to handle errors using code in RAM-only
  and speed up CP.
* Use SET and CLEAR registers for digitalio. The SDK does read, mask
  and write.
* Switch to 2MiB reserved for CircuitPython code. Up from 1MiB.
* Run USB interrupts during flash erase and write.
* Allow storage writes from CP if the USB drive is disabled.
* Get perf bench tests running on CircuitPython and increase timeouts
  so it works when instrumentation is active.
2023-03-14 12:30:58 -07:00
Scott Shawcroft
7d8dac9211
Refine iMX RT memory layout and add three boards
Introduces a way to place CircuitPython code and data into
tightly coupled memory (TCM) which is accessible by the CPU in a
single cycle. It also frees up room in the corresponding cache for
intermittent data. Loading from external flash is slow!

The data cache is also now enabled.

Adds support for the iMX RT 1021 chip. Adds three new boards:
* iMX RT 1020 EVK
* iMX RT 1060 EVK
* Teensy 4.0

Related to #2492, #2472 and #2477. Fixes #2475.
2020-01-17 17:36:08 -08:00
arturo182
13e0cba6f1 Add initial MIMXRT10XX port 2020-01-06 21:08:49 +01:00