djsundog/circuitpython
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

cc3200: Fix SPI clock divider calculation.

Browse Source
This commit is contained in:
danicampora 2015-11-01 23:17:01 +01:00
parent d0601b0a1f
commit f67d06194f
1 changed files with 3 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
cc3200/hal/spi.c
View File

@ -782,15 +782,9 @@ SPIConfigSetExpClk(unsigned long ulBase,unsigned long ulSPIClk,
}
//
// Mask the configurations and set clock divider granularity
// to 1 cycle
// set clock divider granularity to 1 cycle
//
ulRegData = (ulRegData & (~(MCSPI_CH0CONF_WL_M |
MCSPI_CH0CONF_EPOL |
MCSPI_CH0CONF_POL |
MCSPI_CH0CONF_PHA |
MCSPI_CH0CONF_TURBO ) |
MCSPI_CH0CONF_CLKG));
ulRegData |= MCSPI_CH0CONF_CLKG;
//
// Get the divider value
@ -798,7 +792,7 @@ SPIConfigSetExpClk(unsigned long ulBase,unsigned long ulSPIClk,
ulDivider = ((ulSPIClk/ulBitRate) - 1);
//
// The least significant four bits of the divider is used fo configure
// The least significant four bits of the divider is used to configure
// CLKD in MCSPI_CHCONF next eight least significant bits are used to
// configure the EXTCLK in MCSPI_CHCTRL
//