From f67d06194fd56d480809e87dbf761c7973ff2ab7 Mon Sep 17 00:00:00 2001 From: danicampora Date: Sun, 1 Nov 2015 23:17:01 +0100 Subject: [PATCH] cc3200: Fix SPI clock divider calculation. --- cc3200/hal/spi.c | 12 +++--------- 1 file changed, 3 insertions(+), 9 deletions(-) diff --git a/cc3200/hal/spi.c b/cc3200/hal/spi.c index 397ac971a6..8c8c678289 100644 --- a/cc3200/hal/spi.c +++ b/cc3200/hal/spi.c @@ -782,15 +782,9 @@ SPIConfigSetExpClk(unsigned long ulBase,unsigned long ulSPIClk, } // - // Mask the configurations and set clock divider granularity - // to 1 cycle + // set clock divider granularity to 1 cycle // - ulRegData = (ulRegData & (~(MCSPI_CH0CONF_WL_M | - MCSPI_CH0CONF_EPOL | - MCSPI_CH0CONF_POL | - MCSPI_CH0CONF_PHA | - MCSPI_CH0CONF_TURBO ) | - MCSPI_CH0CONF_CLKG)); + ulRegData |= MCSPI_CH0CONF_CLKG; // // Get the divider value @@ -798,7 +792,7 @@ SPIConfigSetExpClk(unsigned long ulBase,unsigned long ulSPIClk, ulDivider = ((ulSPIClk/ulBitRate) - 1); // - // The least significant four bits of the divider is used fo configure + // The least significant four bits of the divider is used to configure // CLKD in MCSPI_CHCONF next eight least significant bits are used to // configure the EXTCLK in MCSPI_CHCTRL //