stmhal: Add stm32fxxx_hal_i2s_ex.c to hal/f2 (dummy) and hal/f4.
This commit is contained in:
Damien George
parent
abc24c1876
commit
99a21dc05d
1
stmhal/hal/f2/src/stm32f2xx_hal_i2s_ex.c
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stmhal/hal/f2/src/stm32f2xx_hal_i2s_ex.c
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// dummy file to keep build system homogeneous across MCU series
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752
stmhal/hal/f4/src/stm32f4xx_hal_i2s_ex.c
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stmhal/hal/f4/src/stm32f4xx_hal_i2s_ex.c
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/**
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******************************************************************************
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* @file stm32f4xx_hal_i2s_ex.c
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* @author MCD Application Team
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* @version V1.1.0
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* @date 19-June-2014
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* @brief I2S HAL module driver.
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* This file provides firmware functions to manage the following
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* functionalities of I2S extension peripheral:
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* + Extension features Functions
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*
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@verbatim
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==============================================================================
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##### I2S Extension features #####
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==============================================================================
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[..]
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(#) In I2S full duplex mode, each SPI peripheral is able to manage sending and receiving
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data simultaneously using two data lines. Each SPI peripheral has an extended block
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called I2Sxext (i.e I2S2ext for SPI2 and I2S3ext for SPI3).
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(#) The extension block is not a full SPI IP, it is used only as I2S slave to
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implement full duplex mode. The extension block uses the same clock sources
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as its master.
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(#) Both I2Sx and I2Sx_ext can be configured as transmitters or receivers.
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[..]
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(@) Only I2Sx can deliver SCK and WS to I2Sx_ext in full duplex mode, where
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I2Sx can be I2S2 or I2S3.
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##### How to use this driver #####
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===============================================================================
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[..]
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Three operation modes are available within this driver :
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*** Polling mode IO operation ***
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=================================
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[..]
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(+) Send and receive in the same time an amount of data in blocking mode using HAL_I2S_TransmitReceive()
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*** Interrupt mode IO operation ***
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===================================
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[..]
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(+) Send and receive in the same time an amount of data in non blocking mode using HAL_I2S_TransmitReceive_IT()
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(+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
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add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
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(+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
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add his own code by customization of function pointer HAL_I2S_TxCpltCallback
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(+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
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add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
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(+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
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add his own code by customization of function pointer HAL_I2S_RxCpltCallback
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(+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
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add his own code by customization of function pointer HAL_I2S_ErrorCallback
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*** DMA mode IO operation ***
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==============================
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[..]
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(+) Send and receive an amount of data in non blocking mode (DMA) using HAL_I2S_TransmitReceive_DMA()
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(+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
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add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
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(+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
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add his own code by customization of function pointer HAL_I2S_TxCpltCallback
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(+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
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add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
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(+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
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add his own code by customization of function pointer HAL_I2S_RxCpltCallback
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(+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
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add his own code by customization of function pointer HAL_I2S_ErrorCallback
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(+) Pause the DMA Transfer using HAL_I2S_DMAPause()
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(+) Resume the DMA Transfer using HAL_I2S_DMAResume()
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(+) Stop the DMA Transfer using HAL_I2S_DMAStop()
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@endverbatim
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of STMicroelectronics nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************
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*/
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f4xx_hal.h"
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/** @addtogroup STM32F4xx_HAL_Driver
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* @{
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*/
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/** @defgroup I2SEx
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* @brief I2S HAL module driver
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* @{
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*/
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#ifdef HAL_I2S_MODULE_ENABLED
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/* Private typedef -----------------------------------------------------------*/
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/* Private define ------------------------------------------------------------*/
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/* Private macro -------------------------------------------------------------*/
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/* Private variables ---------------------------------------------------------*/
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/* Private function prototypes -----------------------------------------------*/
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/* Private functions ---------------------------------------------------------*/
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/** @defgroup I2SEx_Private_Functions
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* @{
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*/
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/** @defgroup I2SEx_Group1 Extension features functions
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* @brief Extension features functions
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*
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@verbatim
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===============================================================================
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##### Extension features Functions #####
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===============================================================================
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[..]
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This subsection provides a set of functions allowing to manage the I2S data
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transfers.
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(#) There are two modes of transfer:
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(++) Blocking mode : The communication is performed in the polling mode.
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The status of all data processing is returned by the same function
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after finishing transfer.
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(++) No-Blocking mode : The communication is performed using Interrupts
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or DMA. These functions return the status of the transfer startup.
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The end of the data processing will be indicated through the
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dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when
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using DMA mode.
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(#) Blocking mode functions are :
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(++) HAL_I2S_TransmitReceive()
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(#) No-Blocking mode functions with Interrupt are :
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(++) HAL_I2S_TransmitReceive_IT()
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(#) No-Blocking mode functions with DMA are :
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(++) HAL_I2S_TransmitReceive_DMA()
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(#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
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(++) HAL_I2S_TxCpltCallback()
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(++) HAL_I2S_RxCpltCallback()
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(++) HAL_I2S_ErrorCallback()
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@endverbatim
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* @{
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*/
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/**
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* @brief Full-Duplex Transmit/Receive data in blocking mode.
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* @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
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* the configuration information for I2S module
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* @param pTxData: a 16-bit pointer to the Transmit data buffer.
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* @param pRxData: a 16-bit pointer to the Receive data buffer.
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* @param Size: number of data sample to be sent:
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* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
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* configuration phase, the Size parameter means the number of 16-bit data length
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* in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
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* the Size parameter means the number of 16-bit data length.
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* @param Timeout: Timeout duration
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* @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
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* between Master and Slave(example: audio streaming).
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* @retval HAL status
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*/
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HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size, uint32_t Timeout)
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{
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uint32_t tickstart = 0;
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uint32_t tmp1 = 0, tmp2 = 0;
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if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))
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{
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return HAL_ERROR;
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}
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/* Check the I2S State */
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if(hi2s->State == HAL_I2S_STATE_READY)
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{
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tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
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tmp2 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
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/* Check the Data format: When a 16-bit data frame or a 16-bit data frame extended
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is selected during the I2S configuration phase, the Size parameter means the number
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of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data
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frame is selected the Size parameter means the number of 16-bit data length. */
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if((tmp1 == I2S_DATAFORMAT_24B)|| \
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(tmp2 == I2S_DATAFORMAT_32B))
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{
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hi2s->TxXferSize = Size*2;
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hi2s->TxXferCount = Size*2;
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hi2s->RxXferSize = Size*2;
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hi2s->RxXferCount = Size*2;
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}
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else
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{
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hi2s->TxXferSize = Size;
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hi2s->TxXferCount = Size;
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hi2s->RxXferSize = Size;
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hi2s->RxXferCount = Size;
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}
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/* Process Locked */
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__HAL_LOCK(hi2s);
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/* Set the I2S State busy TX/RX */
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hi2s->State = HAL_I2S_STATE_BUSY_TX_RX;
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tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
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tmp2 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
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/* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */
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if((tmp1 == I2S_MODE_MASTER_TX) || (tmp2 == I2S_MODE_SLAVE_TX))
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{
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/* Check if the I2S is already enabled: The I2S is kept enabled at the end of transaction
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to avoid the clock de-synchronization between Master and Slave. */
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if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
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{
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/* Enable I2Sext(receiver) before enabling I2Sx peripheral */
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I2SxEXT(hi2s->Instance)->I2SCFGR |= SPI_I2SCFGR_I2SE;
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/* Enable I2Sx peripheral */
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__HAL_I2S_ENABLE(hi2s);
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}
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while(hi2s->TxXferCount > 0)
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{
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/* Wait until TXE flag is set */
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if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, RESET, Timeout) != HAL_OK)
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{
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return HAL_TIMEOUT;
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}
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hi2s->Instance->DR = (*pTxData++);
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/* Get tick */
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tickstart = HAL_GetTick();
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/* Wait until RXNE flag is set */
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while((I2SxEXT(hi2s->Instance)->SR & SPI_SR_RXNE) != SPI_SR_RXNE)
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{
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if(Timeout != HAL_MAX_DELAY)
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{
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if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
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{
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/* Process Unlocked */
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__HAL_UNLOCK(hi2s);
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return HAL_TIMEOUT;
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}
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}
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}
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(*pRxData++) = I2SxEXT(hi2s->Instance)->DR;
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hi2s->TxXferCount--;
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hi2s->RxXferCount--;
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}
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}
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/* The I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX Mode is selected */
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else
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{
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/* Check if the I2S is already enabled */
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if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
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{
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/* Enable I2S peripheral before the I2Sext*/
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__HAL_I2S_ENABLE(hi2s);
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/* Enable I2Sext(transmitter) after enabling I2Sx peripheral */
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I2SxEXT(hi2s->Instance)->I2SCFGR |= SPI_I2SCFGR_I2SE;
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}
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else
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{
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/* Check if Master Receiver mode is selected */
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if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
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{
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/* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
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access to the SPI_SR register. */
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__HAL_I2S_CLEAR_OVRFLAG(hi2s);
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}
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}
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while(hi2s->TxXferCount > 0)
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{
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/* Get tick */
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tickstart = HAL_GetTick();
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/* Wait until TXE flag is set */
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while((I2SxEXT(hi2s->Instance)->SR & SPI_SR_TXE) != SPI_SR_TXE)
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{
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if(Timeout != HAL_MAX_DELAY)
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{
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if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
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{
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/* Process Unlocked */
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__HAL_UNLOCK(hi2s);
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return HAL_TIMEOUT;
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}
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}
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}
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I2SxEXT(hi2s->Instance)->DR = (*pTxData++);
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/* Wait until RXNE flag is set */
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if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, RESET, Timeout) != HAL_OK)
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{
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return HAL_TIMEOUT;
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}
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(*pRxData++) = hi2s->Instance->DR;
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hi2s->TxXferCount--;
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hi2s->RxXferCount--;
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}
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}
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/* Set the I2S State ready */
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hi2s->State = HAL_I2S_STATE_READY;
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/* Process Unlocked */
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__HAL_UNLOCK(hi2s);
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return HAL_OK;
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}
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else
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{
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return HAL_BUSY;
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}
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}
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/**
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* @brief Full-Duplex Transmit/Receive data in non-blocking mode using Interrupt
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* @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
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* the configuration information for I2S module
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* @param pTxData: a 16-bit pointer to the Transmit data buffer.
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* @param pRxData: a 16-bit pointer to the Receive data buffer.
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* @param Size: number of data sample to be sent:
|
||||||
|
* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
|
||||||
|
* configuration phase, the Size parameter means the number of 16-bit data length
|
||||||
|
* in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
|
||||||
|
* the Size parameter means the number of 16-bit data length.
|
||||||
|
* @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
|
||||||
|
* between Master and Slave(example: audio streaming).
|
||||||
|
* @retval HAL status
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size)
|
||||||
|
{
|
||||||
|
uint32_t tmp1 = 0, tmp2 = 0;
|
||||||
|
|
||||||
|
if(hi2s->State == HAL_I2S_STATE_READY)
|
||||||
|
{
|
||||||
|
if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))
|
||||||
|
{
|
||||||
|
return HAL_ERROR;
|
||||||
|
}
|
||||||
|
|
||||||
|
hi2s->pTxBuffPtr = pTxData;
|
||||||
|
hi2s->pRxBuffPtr = pRxData;
|
||||||
|
|
||||||
|
tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
|
||||||
|
tmp2 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
|
||||||
|
/* Check the Data format: When a 16-bit data frame or a 16-bit data frame extended
|
||||||
|
is selected during the I2S configuration phase, the Size parameter means the number
|
||||||
|
of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data
|
||||||
|
frame is selected the Size parameter means the number of 16-bit data length. */
|
||||||
|
if((tmp1 == I2S_DATAFORMAT_24B)||\
|
||||||
|
(tmp2 == I2S_DATAFORMAT_32B))
|
||||||
|
{
|
||||||
|
hi2s->TxXferSize = Size*2;
|
||||||
|
hi2s->TxXferCount = Size*2;
|
||||||
|
hi2s->RxXferSize = Size*2;
|
||||||
|
hi2s->RxXferCount = Size*2;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
hi2s->TxXferSize = Size;
|
||||||
|
hi2s->TxXferCount = Size;
|
||||||
|
hi2s->RxXferSize = Size;
|
||||||
|
hi2s->RxXferCount = Size;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Process Locked */
|
||||||
|
__HAL_LOCK(hi2s);
|
||||||
|
|
||||||
|
hi2s->State = HAL_I2S_STATE_BUSY_TX_RX;
|
||||||
|
hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
|
||||||
|
|
||||||
|
tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
|
||||||
|
tmp2 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
|
||||||
|
/* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */
|
||||||
|
if((tmp1 == I2S_MODE_MASTER_TX) || (tmp2 == I2S_MODE_SLAVE_TX))
|
||||||
|
{
|
||||||
|
/* Enable I2Sext RXNE and ERR interrupts */
|
||||||
|
I2SxEXT(hi2s->Instance)->CR2 |= (I2S_IT_RXNE | I2S_IT_ERR);
|
||||||
|
|
||||||
|
/* Enable I2Sx TXE and ERR interrupts */
|
||||||
|
__HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
|
||||||
|
|
||||||
|
/* Check if the I2S is already enabled */
|
||||||
|
if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
|
||||||
|
{
|
||||||
|
/* Enable I2Sext(receiver) before enabling I2Sx peripheral */
|
||||||
|
I2SxEXT(hi2s->Instance)->I2SCFGR |= SPI_I2SCFGR_I2SE;
|
||||||
|
|
||||||
|
/* Enable I2Sx peripheral */
|
||||||
|
__HAL_I2S_ENABLE(hi2s);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
/* The I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX Mode is selected */
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* Enable I2Sext TXE and ERR interrupts */
|
||||||
|
I2SxEXT(hi2s->Instance)->CR2 |= (I2S_IT_TXE |I2S_IT_ERR);
|
||||||
|
|
||||||
|
/* Enable I2Sext RXNE and ERR interrupts */
|
||||||
|
__HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
|
||||||
|
|
||||||
|
/* Check if the I2S is already enabled */
|
||||||
|
if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
|
||||||
|
{
|
||||||
|
/* Check if the I2S_MODE_MASTER_RX is selected */
|
||||||
|
if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
|
||||||
|
{
|
||||||
|
/* Prepare the First Data before enabling the I2S */
|
||||||
|
if(hi2s->TxXferCount != 0)
|
||||||
|
{
|
||||||
|
/* Transmit First data */
|
||||||
|
I2SxEXT(hi2s->Instance)->DR = (*hi2s->pTxBuffPtr++);
|
||||||
|
hi2s->TxXferCount--;
|
||||||
|
|
||||||
|
if(hi2s->TxXferCount == 0)
|
||||||
|
{
|
||||||
|
/* Disable I2Sext TXE interrupt */
|
||||||
|
I2SxEXT(hi2s->Instance)->CR2 &= ~I2S_IT_TXE;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
/* Enable I2S peripheral */
|
||||||
|
__HAL_I2S_ENABLE(hi2s);
|
||||||
|
|
||||||
|
/* Enable I2Sext(transmitter) after enabling I2Sx peripheral */
|
||||||
|
I2SxEXT(hi2s->Instance)->I2SCFGR |= SPI_I2SCFGR_I2SE;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
/* Process Unlocked */
|
||||||
|
__HAL_UNLOCK(hi2s);
|
||||||
|
|
||||||
|
return HAL_OK;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
return HAL_BUSY;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Full-Duplex Transmit/Receive data in non-blocking mode using DMA
|
||||||
|
* @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for I2S module
|
||||||
|
* @param pTxData: a 16-bit pointer to the Transmit data buffer.
|
||||||
|
* @param pRxData: a 16-bit pointer to the Receive data buffer.
|
||||||
|
* @param Size: number of data sample to be sent:
|
||||||
|
* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
|
||||||
|
* configuration phase, the Size parameter means the number of 16-bit data length
|
||||||
|
* in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
|
||||||
|
* the Size parameter means the number of 16-bit data length.
|
||||||
|
* @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
|
||||||
|
* between Master and Slave(example: audio streaming).
|
||||||
|
* @retval HAL status
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size)
|
||||||
|
{
|
||||||
|
uint32_t *tmp;
|
||||||
|
uint32_t tmp1 = 0, tmp2 = 0;
|
||||||
|
|
||||||
|
if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))
|
||||||
|
{
|
||||||
|
return HAL_ERROR;
|
||||||
|
}
|
||||||
|
|
||||||
|
if(hi2s->State == HAL_I2S_STATE_READY)
|
||||||
|
{
|
||||||
|
hi2s->pTxBuffPtr = pTxData;
|
||||||
|
hi2s->pRxBuffPtr = pRxData;
|
||||||
|
|
||||||
|
tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
|
||||||
|
tmp2 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
|
||||||
|
/* Check the Data format: When a 16-bit data frame or a 16-bit data frame extended
|
||||||
|
is selected during the I2S configuration phase, the Size parameter means the number
|
||||||
|
of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data
|
||||||
|
frame is selected the Size parameter means the number of 16-bit data length. */
|
||||||
|
if((tmp1 == I2S_DATAFORMAT_24B)||\
|
||||||
|
(tmp2 == I2S_DATAFORMAT_32B))
|
||||||
|
{
|
||||||
|
hi2s->TxXferSize = Size*2;
|
||||||
|
hi2s->TxXferCount = Size*2;
|
||||||
|
hi2s->RxXferSize = Size*2;
|
||||||
|
hi2s->RxXferCount = Size*2;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
hi2s->TxXferSize = Size;
|
||||||
|
hi2s->TxXferCount = Size;
|
||||||
|
hi2s->RxXferSize = Size;
|
||||||
|
hi2s->RxXferCount = Size;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Process Locked */
|
||||||
|
__HAL_LOCK(hi2s);
|
||||||
|
|
||||||
|
hi2s->State = HAL_I2S_STATE_BUSY_TX_RX;
|
||||||
|
hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
|
||||||
|
|
||||||
|
/* Set the I2S Rx DMA Half transfert complete callback */
|
||||||
|
hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt;
|
||||||
|
|
||||||
|
/* Set the I2S Rx DMA transfert complete callback */
|
||||||
|
hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt;
|
||||||
|
|
||||||
|
/* Set the I2S Rx DMA error callback */
|
||||||
|
hi2s->hdmarx->XferErrorCallback = I2S_DMAError;
|
||||||
|
|
||||||
|
/* Set the I2S Tx DMA Half transfert complete callback */
|
||||||
|
hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt;
|
||||||
|
|
||||||
|
/* Set the I2S Tx DMA transfert complete callback */
|
||||||
|
hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt;
|
||||||
|
|
||||||
|
/* Set the I2S Tx DMA error callback */
|
||||||
|
hi2s->hdmatx->XferErrorCallback = I2S_DMAError;
|
||||||
|
|
||||||
|
tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
|
||||||
|
tmp2 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
|
||||||
|
/* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */
|
||||||
|
if((tmp1 == I2S_MODE_MASTER_TX) || (tmp2 == I2S_MODE_SLAVE_TX))
|
||||||
|
{
|
||||||
|
/* Enable the Rx DMA Stream */
|
||||||
|
tmp = (uint32_t*)&pRxData;
|
||||||
|
HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&I2SxEXT(hi2s->Instance)->DR, *(uint32_t*)tmp, hi2s->RxXferSize);
|
||||||
|
|
||||||
|
/* Enable Rx DMA Request */
|
||||||
|
I2SxEXT(hi2s->Instance)->CR2 |= SPI_CR2_RXDMAEN;
|
||||||
|
|
||||||
|
/* Enable the Tx DMA Stream */
|
||||||
|
tmp = (uint32_t*)&pTxData;
|
||||||
|
HAL_DMA_Start_IT(hi2s->hdmatx, *(uint32_t*)tmp, (uint32_t)&hi2s->Instance->DR, hi2s->TxXferSize);
|
||||||
|
|
||||||
|
/* Enable Tx DMA Request */
|
||||||
|
hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN;
|
||||||
|
|
||||||
|
/* Check if the I2S is already enabled */
|
||||||
|
if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
|
||||||
|
{
|
||||||
|
/* Enable I2Sext(receiver) before enabling I2Sx peripheral */
|
||||||
|
I2SxEXT(hi2s->Instance)->I2SCFGR |= SPI_I2SCFGR_I2SE;
|
||||||
|
|
||||||
|
/* Enable I2S peripheral after the I2Sext */
|
||||||
|
__HAL_I2S_ENABLE(hi2s);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* Enable the Tx DMA Stream */
|
||||||
|
tmp = (uint32_t*)&pTxData;
|
||||||
|
HAL_DMA_Start_IT(hi2s->hdmatx, *(uint32_t*)tmp, (uint32_t)&I2SxEXT(hi2s->Instance)->DR, hi2s->TxXferSize);
|
||||||
|
|
||||||
|
/* Enable Tx DMA Request */
|
||||||
|
I2SxEXT(hi2s->Instance)->CR2 |= SPI_CR2_TXDMAEN;
|
||||||
|
|
||||||
|
/* Enable the Rx DMA Stream */
|
||||||
|
tmp = (uint32_t*)&pRxData;
|
||||||
|
HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, *(uint32_t*)tmp, hi2s->RxXferSize);
|
||||||
|
|
||||||
|
/* Enable Rx DMA Request */
|
||||||
|
hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN;
|
||||||
|
|
||||||
|
/* Check if the I2S is already enabled */
|
||||||
|
if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
|
||||||
|
{
|
||||||
|
/* Enable I2S peripheral before the I2Sext */
|
||||||
|
__HAL_I2S_ENABLE(hi2s);
|
||||||
|
|
||||||
|
/* Enable I2Sext(transmitter) after enabling I2Sx peripheral */
|
||||||
|
I2SxEXT(hi2s->Instance)->I2SCFGR |= SPI_I2SCFGR_I2SE;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* Check if Master Receiver mode is selected */
|
||||||
|
if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
|
||||||
|
{
|
||||||
|
/* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
|
||||||
|
access to the SPI_SR register. */
|
||||||
|
__HAL_I2S_CLEAR_OVRFLAG(hi2s);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Process Unlocked */
|
||||||
|
__HAL_UNLOCK(hi2s);
|
||||||
|
|
||||||
|
return HAL_OK;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
return HAL_BUSY;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Full-Duplex Transmit/Receive data in non-blocking mode using Interrupt
|
||||||
|
* @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for I2S module
|
||||||
|
* @retval HAL status
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s)
|
||||||
|
{
|
||||||
|
uint32_t tmp1 = 0, tmp2 = 0;
|
||||||
|
|
||||||
|
if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
|
||||||
|
{
|
||||||
|
/* Process Locked */
|
||||||
|
__HAL_LOCK(hi2s);
|
||||||
|
|
||||||
|
tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
|
||||||
|
tmp2 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
|
||||||
|
/* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */
|
||||||
|
if((tmp1 == I2S_MODE_MASTER_TX) || (tmp2 == I2S_MODE_SLAVE_TX))
|
||||||
|
{
|
||||||
|
if(hi2s->TxXferCount != 0)
|
||||||
|
{
|
||||||
|
if(__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_TXE) != RESET)
|
||||||
|
{
|
||||||
|
/* Transmit data */
|
||||||
|
hi2s->Instance->DR = (*hi2s->pTxBuffPtr++);
|
||||||
|
hi2s->TxXferCount--;
|
||||||
|
|
||||||
|
if(hi2s->TxXferCount == 0)
|
||||||
|
{
|
||||||
|
/* Disable TXE interrupt */
|
||||||
|
__HAL_I2S_DISABLE_IT(hi2s, I2S_IT_TXE);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
if(hi2s->RxXferCount != 0)
|
||||||
|
{
|
||||||
|
if((I2SxEXT(hi2s->Instance)->SR & SPI_SR_RXNE) == SPI_SR_RXNE)
|
||||||
|
{
|
||||||
|
/* Receive data */
|
||||||
|
(*hi2s->pRxBuffPtr++) = I2SxEXT(hi2s->Instance)->DR;
|
||||||
|
hi2s->RxXferCount--;
|
||||||
|
|
||||||
|
if(hi2s->RxXferCount == 0)
|
||||||
|
{
|
||||||
|
/* Disable I2Sext RXNE interrupt */
|
||||||
|
I2SxEXT(hi2s->Instance)->CR2 &= ~I2S_IT_RXNE;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
/* The I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX Mode is selected */
|
||||||
|
else
|
||||||
|
{
|
||||||
|
if(hi2s->TxXferCount != 0)
|
||||||
|
{
|
||||||
|
if((I2SxEXT(hi2s->Instance)->SR & SPI_SR_TXE) == SPI_SR_TXE)
|
||||||
|
{
|
||||||
|
/* Transmit data */
|
||||||
|
I2SxEXT(hi2s->Instance)->DR = (*hi2s->pTxBuffPtr++);
|
||||||
|
hi2s->TxXferCount--;
|
||||||
|
|
||||||
|
if(hi2s->TxXferCount == 0)
|
||||||
|
{
|
||||||
|
/* Disable I2Sext TXE interrupt */
|
||||||
|
I2SxEXT(hi2s->Instance)->CR2 &= ~I2S_IT_TXE;
|
||||||
|
|
||||||
|
HAL_I2S_TxCpltCallback(hi2s);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
if(hi2s->RxXferCount != 0)
|
||||||
|
{
|
||||||
|
if(__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_RXNE) != RESET)
|
||||||
|
{
|
||||||
|
/* Receive data */
|
||||||
|
(*hi2s->pRxBuffPtr++) = hi2s->Instance->DR;
|
||||||
|
hi2s->RxXferCount--;
|
||||||
|
|
||||||
|
if(hi2s->RxXferCount == 0)
|
||||||
|
{
|
||||||
|
/* Disable RXNE interrupt */
|
||||||
|
__HAL_I2S_DISABLE_IT(hi2s, I2S_IT_RXNE);
|
||||||
|
|
||||||
|
HAL_I2S_RxCpltCallback(hi2s);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
tmp1 = hi2s->RxXferCount;
|
||||||
|
tmp2 = hi2s->TxXferCount;
|
||||||
|
if((tmp1 == 0) && (tmp2 == 0))
|
||||||
|
{
|
||||||
|
/* Disable I2Sx ERR interrupt */
|
||||||
|
__HAL_I2S_DISABLE_IT(hi2s, I2S_IT_ERR);
|
||||||
|
/* Disable I2Sext ERR interrupt */
|
||||||
|
I2SxEXT(hi2s->Instance)->CR2 &= ~I2S_IT_ERR;
|
||||||
|
|
||||||
|
hi2s->State = HAL_I2S_STATE_READY;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Process Unlocked */
|
||||||
|
__HAL_UNLOCK(hi2s);
|
||||||
|
|
||||||
|
return HAL_OK;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
return HAL_BUSY;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#endif /* HAL_I2S_MODULE_ENABLED */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
Loading…
Reference in New Issue
Block a user