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[#4701] Correct DAC clock speed comments for SAMD21 and SAMD51

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Josh Gadeken 2021-10-04 22:18:26 -06:00
parent e8f21f012c
commit 881724b529
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1 changed files with 2 additions and 2 deletions
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ports/atmel-samd/common-hal/analogio/AnalogOut.c
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@ -85,8 +85,8 @@ void common_hal_analogio_analogout_construct(analogio_analogout_obj_t *self,
_pm_enable_bus_clock(PM_BUS_APBC, DAC); _pm_enable_bus_clock(PM_BUS_APBC, DAC);
#endif #endif
// SAMD21: This clock should be <= 12 MHz, per datasheet section 47.6.3. // SAMD21: This clock should be <= 350 kHz, per datasheet table 36-7.
// SAMD51: This clock should be <= 350kHz, per datasheet table 37-6. // SAMD51: This clock should be <= 12 MHz, per datasheet section 47.6.3.
_gclk_enable_channel(DAC_GCLK_ID, CONF_GCLK_DAC_SRC); _gclk_enable_channel(DAC_GCLK_ID, CONF_GCLK_DAC_SRC);
// Don't double init the DAC on the SAMD51 when both outputs are in use. We use the free state // Don't double init the DAC on the SAMD51 when both outputs are in use. We use the free state