From 881724b529a5d9ea9f50859e9d1d59a5495ad21f Mon Sep 17 00:00:00 2001 From: Josh Gadeken Date: Mon, 4 Oct 2021 22:18:26 -0600 Subject: [PATCH] [#4701] Correct DAC clock speed comments for SAMD21 and SAMD51 --- ports/atmel-samd/common-hal/analogio/AnalogOut.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/ports/atmel-samd/common-hal/analogio/AnalogOut.c b/ports/atmel-samd/common-hal/analogio/AnalogOut.c index 1fa67dc9a1..91782387b8 100644 --- a/ports/atmel-samd/common-hal/analogio/AnalogOut.c +++ b/ports/atmel-samd/common-hal/analogio/AnalogOut.c @@ -85,8 +85,8 @@ void common_hal_analogio_analogout_construct(analogio_analogout_obj_t *self, _pm_enable_bus_clock(PM_BUS_APBC, DAC); #endif - // SAMD21: This clock should be <= 12 MHz, per datasheet section 47.6.3. - // SAMD51: This clock should be <= 350kHz, per datasheet table 37-6. + // SAMD21: This clock should be <= 350 kHz, per datasheet table 36-7. + // SAMD51: This clock should be <= 12 MHz, per datasheet section 47.6.3. _gclk_enable_channel(DAC_GCLK_ID, CONF_GCLK_DAC_SRC); // Don't double init the DAC on the SAMD51 when both outputs are in use. We use the free state