Merge branch 'master' into stm32-temperature-us
This commit is contained in:
hierophect
GitHub
commit
4bc093675c
1
.github/workflows/build.yml
vendored
1
.github/workflows/build.yml
vendored
@ -219,6 +219,7 @@ jobs:
|
||||
- "stm32f411ce_blackpill"
|
||||
- "stm32f411ve_discovery"
|
||||
- "stm32f412zg_discovery"
|
||||
- "stm32f4_discovery"
|
||||
- "stringcar_m0_express"
|
||||
- "teensy40"
|
||||
- "teknikio_bluebird"
|
||||
|
||||
@ -22,7 +22,9 @@ MEMORY
|
||||
/* SoftDevice 6.1.0 with 5 connections and various increases takes just under 64kiB.
|
||||
/* To measure the minimum required amount of memory for given configuration, set this number
|
||||
high enough to work and then check the mutation of the value done by sd_ble_enable. */
|
||||
RAM (xrw) : ORIGIN = 0x20000000 + 64K, LENGTH = 256K - 64K
|
||||
SPIM3_RAM (rw) : ORIGIN = 0x20000000 + 64K, LENGTH = 8K
|
||||
RAM (xrw) : ORIGIN = 0x20000000 + 64K + 8K, LENGTH = 256K - 64K -8K
|
||||
|
||||
}
|
||||
|
||||
/* produce a link error if there is not this amount of RAM available */
|
||||
@ -37,6 +39,10 @@ _estack = ORIGIN(RAM) + LENGTH(RAM);
|
||||
_ram_end = ORIGIN(RAM) + LENGTH(RAM);
|
||||
_heap_end = 0x20020000; /* tunable */
|
||||
|
||||
/* nrf52840 SPIM3 needs its own area to work around hardware problems. Nothing else may use this space. */
|
||||
_spim3_ram = ORIGIN(SPIM3_RAM);
|
||||
_spim3_ram_end = ORIGIN(SPIM3_RAM) + LENGTH(RAM);
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||||
|
||||
/* define output sections */
|
||||
SECTIONS
|
||||
{
|
||||
|
||||
@ -22,6 +22,8 @@
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <string.h>
|
||||
|
||||
#include "shared-bindings/busio/SPI.h"
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||||
#include "py/mperrno.h"
|
||||
#include "py/runtime.h"
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||||
@ -29,33 +31,34 @@
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||||
#include "nrfx_spim.h"
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||||
#include "nrf_gpio.h"
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|
||||
// These are in order from ighest available frequency to lowest (32MHz first, then 8MHz).
|
||||
STATIC spim_peripheral_t spim_peripherals[] = {
|
||||
#if NRFX_CHECK(NRFX_SPIM3_ENABLED)
|
||||
// SPIM3 exists only on nRF52840 and supports 32MHz max. All other SPIM's are only 8MHz max.
|
||||
// Allocate SPIM3 first.
|
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{ .spim = NRFX_SPIM_INSTANCE(3),
|
||||
.max_frequency_MHz = 32,
|
||||
.max_frequency = 32000000,
|
||||
.max_xfer_size = SPIM3_EASYDMA_MAXCNT_SIZE,
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||||
},
|
||||
#endif
|
||||
#if NRFX_CHECK(NRFX_SPIM2_ENABLED)
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||||
// SPIM2 is not shared with a TWIM, so allocate before the shared ones.
|
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{ .spim = NRFX_SPIM_INSTANCE(2),
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||||
.max_frequency_MHz = 8,
|
||||
.max_frequency = 8000000,
|
||||
.max_xfer_size = SPIM2_EASYDMA_MAXCNT_SIZE,
|
||||
},
|
||||
#endif
|
||||
#if NRFX_CHECK(NRFX_SPIM1_ENABLED)
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||||
// SPIM1 and TWIM1 share an address.
|
||||
{ .spim = NRFX_SPIM_INSTANCE(1),
|
||||
.max_frequency_MHz = 8,
|
||||
.max_frequency = 8000000,
|
||||
.max_xfer_size = SPIM1_EASYDMA_MAXCNT_SIZE,
|
||||
},
|
||||
#endif
|
||||
#if NRFX_CHECK(NRFX_SPIM0_ENABLED)
|
||||
// SPIM0 and TWIM0 share an address.
|
||||
{ .spim = NRFX_SPIM_INSTANCE(0),
|
||||
.max_frequency_MHz = 8,
|
||||
.max_frequency = 8000000,
|
||||
.max_xfer_size = SPIM0_EASYDMA_MAXCNT_SIZE,
|
||||
},
|
||||
#endif
|
||||
@ -63,6 +66,11 @@ STATIC spim_peripheral_t spim_peripherals[] = {
|
||||
|
||||
STATIC bool never_reset[MP_ARRAY_SIZE(spim_peripherals)];
|
||||
|
||||
// Separate RAM area for SPIM3 transmit buffer to avoid SPIM3 hardware errata.
|
||||
// https://infocenter.nordicsemi.com/index.jsp?topic=%2Ferrata_nRF52840_Rev2%2FERR%2FnRF52840%2FRev2%2Flatest%2Fanomaly_840_198.html
|
||||
extern uint32_t _spim3_ram;
|
||||
STATIC uint8_t *spim3_transmit_buffer = (uint8_t *) &_spim3_ram;
|
||||
|
||||
void spi_reset(void) {
|
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for (size_t i = 0 ; i < MP_ARRAY_SIZE(spim_peripherals); i++) {
|
||||
if (never_reset[i]) {
|
||||
@ -122,7 +130,7 @@ static nrf_spim_frequency_t baudrate_to_spim_frequency(const uint32_t baudrate)
|
||||
}
|
||||
|
||||
void common_hal_busio_spi_construct(busio_spi_obj_t *self, const mcu_pin_obj_t * clock, const mcu_pin_obj_t * mosi, const mcu_pin_obj_t * miso) {
|
||||
// Find a free instance.
|
||||
// Find a free instance, with most desirable (highest freq and not shared) allocated first.
|
||||
self->spim_peripheral = NULL;
|
||||
for (size_t i = 0 ; i < MP_ARRAY_SIZE(spim_peripherals); i++) {
|
||||
if ((spim_peripherals[i].spim.p_reg->ENABLE & SPIM_ENABLE_ENABLE_Msk) == 0) {
|
||||
@ -137,7 +145,8 @@ void common_hal_busio_spi_construct(busio_spi_obj_t *self, const mcu_pin_obj_t *
|
||||
|
||||
nrfx_spim_config_t config = NRFX_SPIM_DEFAULT_CONFIG(NRFX_SPIM_PIN_NOT_USED, NRFX_SPIM_PIN_NOT_USED,
|
||||
NRFX_SPIM_PIN_NOT_USED, NRFX_SPIM_PIN_NOT_USED);
|
||||
config.frequency = NRF_SPIM_FREQ_8M;
|
||||
|
||||
config.frequency = baudrate_to_spim_frequency(self->spim_peripheral->max_frequency);
|
||||
|
||||
config.sck_pin = clock->number;
|
||||
self->clock_pin_number = clock->number;
|
||||
@ -189,8 +198,7 @@ bool common_hal_busio_spi_configure(busio_spi_obj_t *self, uint32_t baudrate, ui
|
||||
|
||||
// Set desired frequency, rounding down, and don't go above available frequency for this SPIM.
|
||||
nrf_spim_frequency_set(self->spim_peripheral->spim.p_reg,
|
||||
baudrate_to_spim_frequency(MIN(baudrate,
|
||||
self->spim_peripheral->max_frequency_MHz * 1000000)));
|
||||
baudrate_to_spim_frequency(MIN(baudrate, self->spim_peripheral->max_frequency)));
|
||||
|
||||
nrf_spim_mode_t mode = NRF_SPIM_MODE_0;
|
||||
if (polarity) {
|
||||
@ -224,21 +232,36 @@ void common_hal_busio_spi_unlock(busio_spi_obj_t *self) {
|
||||
}
|
||||
|
||||
bool common_hal_busio_spi_write(busio_spi_obj_t *self, const uint8_t *data, size_t len) {
|
||||
if (len == 0)
|
||||
if (len == 0) {
|
||||
return true;
|
||||
}
|
||||
|
||||
const bool is_spim3 = self->spim_peripheral->spim.p_reg == NRF_SPIM3;
|
||||
|
||||
const uint32_t max_xfer_size = self->spim_peripheral->max_xfer_size;
|
||||
const uint32_t parts = len / max_xfer_size;
|
||||
const uint32_t remainder = len % max_xfer_size;
|
||||
|
||||
for (uint32_t i = 0; i < parts; ++i) {
|
||||
const nrfx_spim_xfer_desc_t xfer = NRFX_SPIM_XFER_TX(data + i * max_xfer_size, max_xfer_size);
|
||||
uint8_t *start = (uint8_t *) (data + i * max_xfer_size);
|
||||
if (is_spim3) {
|
||||
// If SPIM3, copy into unused RAM block, and do DMA from there.
|
||||
memcpy(spim3_transmit_buffer, start, max_xfer_size);
|
||||
start = spim3_transmit_buffer;
|
||||
}
|
||||
const nrfx_spim_xfer_desc_t xfer = NRFX_SPIM_XFER_TX(start, max_xfer_size);
|
||||
if (nrfx_spim_xfer(&self->spim_peripheral->spim, &xfer, 0) != NRFX_SUCCESS)
|
||||
return false;
|
||||
}
|
||||
|
||||
if (remainder > 0) {
|
||||
const nrfx_spim_xfer_desc_t xfer = NRFX_SPIM_XFER_TX(data + parts * max_xfer_size, remainder);
|
||||
uint8_t *start = (uint8_t *) (data + parts * max_xfer_size);
|
||||
if (is_spim3) {
|
||||
// If SPIM3, copy into unused RAM block, and do DMA from there.
|
||||
memcpy(spim3_transmit_buffer, start, remainder);
|
||||
start = spim3_transmit_buffer;
|
||||
}
|
||||
const nrfx_spim_xfer_desc_t xfer = NRFX_SPIM_XFER_TX(start, remainder);
|
||||
if (nrfx_spim_xfer(&self->spim_peripheral->spim, &xfer, 0) != NRFX_SUCCESS)
|
||||
return false;
|
||||
}
|
||||
@ -247,8 +270,9 @@ bool common_hal_busio_spi_write(busio_spi_obj_t *self, const uint8_t *data, size
|
||||
}
|
||||
|
||||
bool common_hal_busio_spi_read(busio_spi_obj_t *self, uint8_t *data, size_t len, uint8_t write_value) {
|
||||
if (len == 0)
|
||||
if (len == 0) {
|
||||
return true;
|
||||
}
|
||||
|
||||
const uint32_t max_xfer_size = self->spim_peripheral->max_xfer_size;
|
||||
const uint32_t parts = len / max_xfer_size;
|
||||
@ -270,23 +294,37 @@ bool common_hal_busio_spi_read(busio_spi_obj_t *self, uint8_t *data, size_t len,
|
||||
}
|
||||
|
||||
bool common_hal_busio_spi_transfer(busio_spi_obj_t *self, uint8_t *data_out, uint8_t *data_in, size_t len) {
|
||||
if (len == 0)
|
||||
if (len == 0) {
|
||||
return true;
|
||||
}
|
||||
|
||||
const bool is_spim3 = self->spim_peripheral->spim.p_reg == NRF_SPIM3;
|
||||
|
||||
const uint32_t max_xfer_size = self->spim_peripheral->max_xfer_size;
|
||||
const uint32_t parts = len / max_xfer_size;
|
||||
const uint32_t remainder = len % max_xfer_size;
|
||||
|
||||
for (uint32_t i = 0; i < parts; ++i) {
|
||||
const nrfx_spim_xfer_desc_t xfer = NRFX_SPIM_SINGLE_XFER(data_out + i * max_xfer_size, max_xfer_size,
|
||||
uint8_t *out_start = (uint8_t *) (data_out + i * max_xfer_size);
|
||||
if (is_spim3) {
|
||||
// If SPIM3, copy into unused RAM block, and do DMA from there.
|
||||
memcpy(spim3_transmit_buffer, out_start, max_xfer_size);
|
||||
out_start = spim3_transmit_buffer;
|
||||
}
|
||||
const nrfx_spim_xfer_desc_t xfer = NRFX_SPIM_SINGLE_XFER(out_start, max_xfer_size,
|
||||
data_in + i * max_xfer_size, max_xfer_size);
|
||||
if (nrfx_spim_xfer(&self->spim_peripheral->spim, &xfer, 0) != NRFX_SUCCESS)
|
||||
return false;
|
||||
}
|
||||
|
||||
if (remainder > 0) {
|
||||
const nrfx_spim_xfer_desc_t xfer = NRFX_SPIM_SINGLE_XFER(data_out + parts * max_xfer_size, remainder,
|
||||
uint8_t *out_start = (uint8_t *) (data_out + parts * max_xfer_size);
|
||||
if (is_spim3) {
|
||||
// If SPIM3, copy into unused RAM block, and do DMA from there.
|
||||
memcpy(spim3_transmit_buffer, out_start, remainder);
|
||||
out_start = spim3_transmit_buffer;
|
||||
}
|
||||
const nrfx_spim_xfer_desc_t xfer = NRFX_SPIM_SINGLE_XFER(out_start, remainder,
|
||||
data_in + parts * max_xfer_size, remainder);
|
||||
if (nrfx_spim_xfer(&self->spim_peripheral->spim, &xfer, 0) != NRFX_SUCCESS)
|
||||
return false;
|
||||
@ -325,9 +363,9 @@ uint32_t common_hal_busio_spi_get_frequency(busio_spi_obj_t* self) {
|
||||
}
|
||||
|
||||
uint8_t common_hal_busio_spi_get_phase(busio_spi_obj_t* self) {
|
||||
return 0;
|
||||
return (self->spim_peripheral->spim.p_reg->CONFIG & SPIM_CONFIG_CPHA_Msk) >> SPIM_CONFIG_CPHA_Pos;
|
||||
}
|
||||
|
||||
uint8_t common_hal_busio_spi_get_polarity(busio_spi_obj_t* self) {
|
||||
return 0;
|
||||
return (self->spim_peripheral->spim.p_reg->CONFIG & SPIM_CONFIG_CPOL_Msk) >> SPIM_CONFIG_CPOL_Pos;
|
||||
}
|
||||
|
||||
@ -32,7 +32,7 @@
|
||||
|
||||
typedef struct {
|
||||
nrfx_spim_t spim;
|
||||
uint8_t max_frequency_MHz;
|
||||
uint32_t max_frequency;
|
||||
uint8_t max_xfer_size;
|
||||
} spim_peripheral_t;
|
||||
|
||||
|
||||
@ -26,10 +26,9 @@
|
||||
|
||||
// CIRCUITPY_NRF_NUM_I2C is 1 or 2 to choose how many I2C (TWIM) peripherals
|
||||
// to provide.
|
||||
// This can go away once we have SPIM3 working: then we can have two
|
||||
// I2C and two SPI.
|
||||
// With SPIM3 working we can have two I2C and two SPI.
|
||||
#ifndef CIRCUITPY_NRF_NUM_I2C
|
||||
#define CIRCUITPY_NRF_NUM_I2C 1
|
||||
#define CIRCUITPY_NRF_NUM_I2C 2
|
||||
#endif
|
||||
|
||||
#if CIRCUITPY_NRF_NUM_I2C != 1 && CIRCUITPY_NRF_NUM_I2C != 2
|
||||
@ -42,13 +41,12 @@
|
||||
#define NRFX_SPIM1_ENABLED 1
|
||||
#endif
|
||||
#define NRFX_SPIM2_ENABLED 1
|
||||
// DON'T ENABLE SPIM3 DUE TO ANOMALY WORKAROUND FAILURE (SEE ABOVE).
|
||||
// #ifdef NRF52840_XXAA
|
||||
// #define NRFX_SPIM_EXTENDED_ENABLED 1
|
||||
// #define NRFX_SPIM3_ENABLED 1
|
||||
// #else
|
||||
// #define NRFX_SPIM3_ENABLED 0
|
||||
// #endif
|
||||
#ifdef NRF52840_XXAA
|
||||
#define NRFX_SPIM_EXTENDED_ENABLED 1
|
||||
#define NRFX_SPIM3_ENABLED 1
|
||||
#else
|
||||
#define NRFX_SPIM3_ENABLED 0
|
||||
#endif
|
||||
|
||||
|
||||
#define NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY 7
|
||||
|
||||
108
ports/stm32f4/boards/STM32F407_fs.ld
Normal file
108
ports/stm32f4/boards/STM32F407_fs.ld
Normal file
@ -0,0 +1,108 @@
|
||||
/*
|
||||
GNU linker script for STM32F405 via Micropython
|
||||
*/
|
||||
|
||||
/* Specify the memory areas */
|
||||
MEMORY
|
||||
{
|
||||
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1024K /* entire flash */
|
||||
FLASH_ISR (rx) : ORIGIN = 0x08000000, LENGTH = 16K /* sector 0 */
|
||||
FLASH_FS (rx) : ORIGIN = 0x08004000, LENGTH = 48K /* sectors 1,2,3 are 16K */
|
||||
FLASH_TEXT (rx) : ORIGIN = 0x08010000, LENGTH = 960K /* sector 4 is 64K, sectors 5,6,7 are 128K */
|
||||
CCMRAM (xrw) : ORIGIN = 0x10000000, LENGTH = 64K
|
||||
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K
|
||||
}
|
||||
|
||||
/* produce a link error if there is not this amount of RAM for these sections */
|
||||
_minimum_stack_size = 2K;
|
||||
_minimum_heap_size = 16K;
|
||||
|
||||
/* Define tho top end of the stack. The stack is full descending so begins just
|
||||
above last byte of RAM. Note that EABI requires the stack to be 8-byte
|
||||
aligned for a call. */
|
||||
_estack = ORIGIN(RAM) + LENGTH(RAM);
|
||||
|
||||
/* RAM extents for the garbage collector */
|
||||
_ram_start = ORIGIN(RAM);
|
||||
_ram_end = ORIGIN(RAM) + LENGTH(RAM);
|
||||
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
/* define output sections */
|
||||
SECTIONS
|
||||
{
|
||||
/* The startup code goes first into FLASH */
|
||||
.isr_vector :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.isr_vector)) /* Startup code */
|
||||
|
||||
/* This first flash block is 16K annd the isr vectors only take up
|
||||
about 400 bytes. Micropython pads this with files, but this didn't
|
||||
work with the size of Circuitpython's ff object. */
|
||||
|
||||
. = ALIGN(4);
|
||||
} >FLASH_ISR
|
||||
|
||||
/* The program code and other data goes into FLASH */
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.text*) /* .text* sections (code) */
|
||||
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||
/* *(.glue_7) */ /* glue arm to thumb code */
|
||||
/* *(.glue_7t) */ /* glue thumb to arm code */
|
||||
|
||||
. = ALIGN(4);
|
||||
_etext = .; /* define a global symbol at end of code */
|
||||
} >FLASH_TEXT
|
||||
|
||||
/* used by the startup to initialize data */
|
||||
_sidata = LOADADDR(.data);
|
||||
|
||||
/* This is the initialized data section
|
||||
The program executes knowing that the data is in the RAM
|
||||
but the loader puts the initial values in the FLASH (inidata).
|
||||
It is one task of the startup to copy the initial values from FLASH to RAM. */
|
||||
.data :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sdata = .; /* create a global symbol at data start; used by startup code in order to initialise the .data section in RAM */
|
||||
*(.data*) /* .data* sections */
|
||||
|
||||
. = ALIGN(4);
|
||||
_edata = .; /* define a global symbol at data end; used by startup code in order to initialise the .data section in RAM */
|
||||
} >RAM AT> FLASH_TEXT
|
||||
|
||||
/* Uninitialized data section */
|
||||
.bss :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sbss = .; /* define a global symbol at bss start; used by startup code */
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
|
||||
. = ALIGN(4);
|
||||
_ebss = .; /* define a global symbol at bss end; used by startup code and GC */
|
||||
} >RAM
|
||||
|
||||
/* this is to define the start of the heap, and make sure we have a minimum size */
|
||||
.heap :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
. = . + _minimum_heap_size;
|
||||
. = ALIGN(4);
|
||||
} >RAM
|
||||
|
||||
/* this just checks there is enough RAM for the stack */
|
||||
.stack :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
. = . + _minimum_stack_size;
|
||||
. = ALIGN(4);
|
||||
} >RAM
|
||||
|
||||
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||
}
|
||||
|
||||
|
||||
@ -34,6 +34,8 @@
|
||||
|
||||
#define MICROPY_HW_NEOPIXEL (&pin_PC00)
|
||||
|
||||
#define BOARD_OSC_DIV 12
|
||||
|
||||
// On-board flash
|
||||
#define SPI_FLASH_MOSI_PIN (&pin_PB05)
|
||||
#define SPI_FLASH_MISO_PIN (&pin_PB04)
|
||||
|
||||
@ -32,6 +32,7 @@
|
||||
#define FLASH_SIZE (0x100000)
|
||||
#define FLASH_PAGE_SIZE (0x4000)
|
||||
|
||||
#define BOARD_OSC_DIV 12
|
||||
|
||||
#define DEFAULT_I2C_BUS_SCL (&pin_PB06)
|
||||
#define DEFAULT_I2C_BUS_SDA (&pin_PB07)
|
||||
|
||||
516
ports/stm32f4/boards/startup_stm32f407xx.s
Normal file
516
ports/stm32f4/boards/startup_stm32f407xx.s
Normal file
@ -0,0 +1,516 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file startup_stm32f405xx.s
|
||||
* @author MCD Application Team
|
||||
* @brief STM32F405xx Devices vector table for GCC based toolchains.
|
||||
* This module performs:
|
||||
* - Set the initial SP
|
||||
* - Set the initial PC == Reset_Handler,
|
||||
* - Set the vector table entries with the exceptions ISR address
|
||||
* - Branches to main in the C library (which eventually
|
||||
* calls main()).
|
||||
* After Reset the Cortex-M4 processor is in Thread mode,
|
||||
* priority is Privileged, and the Stack is set to Main.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
.syntax unified
|
||||
.cpu cortex-m4
|
||||
.fpu softvfp
|
||||
.thumb
|
||||
|
||||
.global g_pfnVectors
|
||||
.global Default_Handler
|
||||
|
||||
/* start address for the initialization values of the .data section.
|
||||
defined in linker script */
|
||||
.word _sidata
|
||||
/* start address for the .data section. defined in linker script */
|
||||
.word _sdata
|
||||
/* end address for the .data section. defined in linker script */
|
||||
.word _edata
|
||||
/* start address for the .bss section. defined in linker script */
|
||||
.word _sbss
|
||||
/* end address for the .bss section. defined in linker script */
|
||||
.word _ebss
|
||||
/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
|
||||
|
||||
/**
|
||||
* @brief This is the code that gets called when the processor first
|
||||
* starts execution following a reset event. Only the absolutely
|
||||
* necessary set is performed, after which the application
|
||||
* supplied main() routine is called.
|
||||
* @param None
|
||||
* @retval : None
|
||||
*/
|
||||
|
||||
.section .text.Reset_Handler
|
||||
.weak Reset_Handler
|
||||
.type Reset_Handler, %function
|
||||
Reset_Handler:
|
||||
ldr sp, =_estack /* set stack pointer */
|
||||
|
||||
/* Copy the data segment initializers from flash to SRAM */
|
||||
movs r1, #0
|
||||
b LoopCopyDataInit
|
||||
|
||||
CopyDataInit:
|
||||
ldr r3, =_sidata
|
||||
ldr r3, [r3, r1]
|
||||
str r3, [r0, r1]
|
||||
adds r1, r1, #4
|
||||
|
||||
LoopCopyDataInit:
|
||||
ldr r0, =_sdata
|
||||
ldr r3, =_edata
|
||||
adds r2, r0, r1
|
||||
cmp r2, r3
|
||||
bcc CopyDataInit
|
||||
ldr r2, =_sbss
|
||||
b LoopFillZerobss
|
||||
/* Zero fill the bss segment. */
|
||||
FillZerobss:
|
||||
movs r3, #0
|
||||
str r3, [r2], #4
|
||||
|
||||
LoopFillZerobss:
|
||||
ldr r3, = _ebss
|
||||
cmp r2, r3
|
||||
bcc FillZerobss
|
||||
|
||||
/* Call the clock system intitialization function.*/
|
||||
bl SystemInit
|
||||
/* Call static constructors */
|
||||
/* bl __libc_init_array */
|
||||
/* Call the application's entry point.*/
|
||||
bl main
|
||||
bx lr
|
||||
.size Reset_Handler, .-Reset_Handler
|
||||
|
||||
/**
|
||||
* @brief This is the code that gets called when the processor receives an
|
||||
* unexpected interrupt. This simply enters an infinite loop, preserving
|
||||
* the system state for examination by a debugger.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
.section .text.Default_Handler,"ax",%progbits
|
||||
Default_Handler:
|
||||
Infinite_Loop:
|
||||
b Infinite_Loop
|
||||
.size Default_Handler, .-Default_Handler
|
||||
/******************************************************************************
|
||||
*
|
||||
* The minimal vector table for a Cortex M3. Note that the proper constructs
|
||||
* must be placed on this to ensure that it ends up at physical address
|
||||
* 0x0000.0000.
|
||||
*
|
||||
*******************************************************************************/
|
||||
.section .isr_vector,"a",%progbits
|
||||
.type g_pfnVectors, %object
|
||||
.size g_pfnVectors, .-g_pfnVectors
|
||||
|
||||
|
||||
|
||||
g_pfnVectors:
|
||||
.word _estack
|
||||
.word Reset_Handler
|
||||
|
||||
.word NMI_Handler
|
||||
.word HardFault_Handler
|
||||
.word MemManage_Handler
|
||||
.word BusFault_Handler
|
||||
.word UsageFault_Handler
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word SVC_Handler
|
||||
.word DebugMon_Handler
|
||||
.word 0
|
||||
.word PendSV_Handler
|
||||
.word SysTick_Handler
|
||||
|
||||
/* External Interrupts */
|
||||
.word WWDG_IRQHandler /* Window WatchDog */
|
||||
.word PVD_IRQHandler /* PVD through EXTI Line detection */
|
||||
.word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
|
||||
.word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
|
||||
.word FLASH_IRQHandler /* FLASH */
|
||||
.word RCC_IRQHandler /* RCC */
|
||||
.word EXTI0_IRQHandler /* EXTI Line0 */
|
||||
.word EXTI1_IRQHandler /* EXTI Line1 */
|
||||
.word EXTI2_IRQHandler /* EXTI Line2 */
|
||||
.word EXTI3_IRQHandler /* EXTI Line3 */
|
||||
.word EXTI4_IRQHandler /* EXTI Line4 */
|
||||
.word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
|
||||
.word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
|
||||
.word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
|
||||
.word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
|
||||
.word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
|
||||
.word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
|
||||
.word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
|
||||
.word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
|
||||
.word CAN1_TX_IRQHandler /* CAN1 TX */
|
||||
.word CAN1_RX0_IRQHandler /* CAN1 RX0 */
|
||||
.word CAN1_RX1_IRQHandler /* CAN1 RX1 */
|
||||
.word CAN1_SCE_IRQHandler /* CAN1 SCE */
|
||||
.word EXTI9_5_IRQHandler /* External Line[9:5]s */
|
||||
.word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */
|
||||
.word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */
|
||||
.word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */
|
||||
.word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
|
||||
.word TIM2_IRQHandler /* TIM2 */
|
||||
.word TIM3_IRQHandler /* TIM3 */
|
||||
.word TIM4_IRQHandler /* TIM4 */
|
||||
.word I2C1_EV_IRQHandler /* I2C1 Event */
|
||||
.word I2C1_ER_IRQHandler /* I2C1 Error */
|
||||
.word I2C2_EV_IRQHandler /* I2C2 Event */
|
||||
.word I2C2_ER_IRQHandler /* I2C2 Error */
|
||||
.word SPI1_IRQHandler /* SPI1 */
|
||||
.word SPI2_IRQHandler /* SPI2 */
|
||||
.word USART1_IRQHandler /* USART1 */
|
||||
.word USART2_IRQHandler /* USART2 */
|
||||
.word USART3_IRQHandler /* USART3 */
|
||||
.word EXTI15_10_IRQHandler /* External Line[15:10]s */
|
||||
.word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
|
||||
.word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */
|
||||
.word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
|
||||
.word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
|
||||
.word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
|
||||
.word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
|
||||
.word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
|
||||
.word FSMC_IRQHandler /* FSMC */
|
||||
.word SDIO_IRQHandler /* SDIO */
|
||||
.word TIM5_IRQHandler /* TIM5 */
|
||||
.word SPI3_IRQHandler /* SPI3 */
|
||||
.word UART4_IRQHandler /* UART4 */
|
||||
.word UART5_IRQHandler /* UART5 */
|
||||
.word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
|
||||
.word TIM7_IRQHandler /* TIM7 */
|
||||
.word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
|
||||
.word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
|
||||
.word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
|
||||
.word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
|
||||
.word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word CAN2_TX_IRQHandler /* CAN2 TX */
|
||||
.word CAN2_RX0_IRQHandler /* CAN2 RX0 */
|
||||
.word CAN2_RX1_IRQHandler /* CAN2 RX1 */
|
||||
.word CAN2_SCE_IRQHandler /* CAN2 SCE */
|
||||
.word OTG_FS_IRQHandler /* USB OTG FS */
|
||||
.word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
|
||||
.word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
|
||||
.word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
|
||||
.word USART6_IRQHandler /* USART6 */
|
||||
.word I2C3_EV_IRQHandler /* I2C3 event */
|
||||
.word I2C3_ER_IRQHandler /* I2C3 error */
|
||||
.word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
|
||||
.word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
|
||||
.word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
|
||||
.word OTG_HS_IRQHandler /* USB OTG HS */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word HASH_RNG_IRQHandler /* Hash and Rng */
|
||||
.word FPU_IRQHandler /* FPU */
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||
* As they are weak aliases, any function with the same name will override
|
||||
* this definition.
|
||||
*
|
||||
*******************************************************************************/
|
||||
.weak NMI_Handler
|
||||
.thumb_set NMI_Handler,Default_Handler
|
||||
|
||||
.weak HardFault_Handler
|
||||
.thumb_set HardFault_Handler,Default_Handler
|
||||
|
||||
.weak MemManage_Handler
|
||||
.thumb_set MemManage_Handler,Default_Handler
|
||||
|
||||
.weak BusFault_Handler
|
||||
.thumb_set BusFault_Handler,Default_Handler
|
||||
|
||||
.weak UsageFault_Handler
|
||||
.thumb_set UsageFault_Handler,Default_Handler
|
||||
|
||||
.weak SVC_Handler
|
||||
.thumb_set SVC_Handler,Default_Handler
|
||||
|
||||
.weak DebugMon_Handler
|
||||
.thumb_set DebugMon_Handler,Default_Handler
|
||||
|
||||
.weak PendSV_Handler
|
||||
.thumb_set PendSV_Handler,Default_Handler
|
||||
|
||||
.weak SysTick_Handler
|
||||
.thumb_set SysTick_Handler,Default_Handler
|
||||
|
||||
.weak WWDG_IRQHandler
|
||||
.thumb_set WWDG_IRQHandler,Default_Handler
|
||||
|
||||
.weak PVD_IRQHandler
|
||||
.thumb_set PVD_IRQHandler,Default_Handler
|
||||
|
||||
.weak TAMP_STAMP_IRQHandler
|
||||
.thumb_set TAMP_STAMP_IRQHandler,Default_Handler
|
||||
|
||||
.weak RTC_WKUP_IRQHandler
|
||||
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak FLASH_IRQHandler
|
||||
.thumb_set FLASH_IRQHandler,Default_Handler
|
||||
|
||||
.weak RCC_IRQHandler
|
||||
.thumb_set RCC_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI0_IRQHandler
|
||||
.thumb_set EXTI0_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI1_IRQHandler
|
||||
.thumb_set EXTI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI2_IRQHandler
|
||||
.thumb_set EXTI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI3_IRQHandler
|
||||
.thumb_set EXTI3_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI4_IRQHandler
|
||||
.thumb_set EXTI4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream0_IRQHandler
|
||||
.thumb_set DMA1_Stream0_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream1_IRQHandler
|
||||
.thumb_set DMA1_Stream1_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream2_IRQHandler
|
||||
.thumb_set DMA1_Stream2_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream3_IRQHandler
|
||||
.thumb_set DMA1_Stream3_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream4_IRQHandler
|
||||
.thumb_set DMA1_Stream4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream5_IRQHandler
|
||||
.thumb_set DMA1_Stream5_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream6_IRQHandler
|
||||
.thumb_set DMA1_Stream6_IRQHandler,Default_Handler
|
||||
|
||||
.weak ADC_IRQHandler
|
||||
.thumb_set ADC_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN1_TX_IRQHandler
|
||||
.thumb_set CAN1_TX_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN1_RX0_IRQHandler
|
||||
.thumb_set CAN1_RX0_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN1_RX1_IRQHandler
|
||||
.thumb_set CAN1_RX1_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN1_SCE_IRQHandler
|
||||
.thumb_set CAN1_SCE_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI9_5_IRQHandler
|
||||
.thumb_set EXTI9_5_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_BRK_TIM9_IRQHandler
|
||||
.thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_UP_TIM10_IRQHandler
|
||||
.thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_TRG_COM_TIM11_IRQHandler
|
||||
.thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_CC_IRQHandler
|
||||
.thumb_set TIM1_CC_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM2_IRQHandler
|
||||
.thumb_set TIM2_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM3_IRQHandler
|
||||
.thumb_set TIM3_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM4_IRQHandler
|
||||
.thumb_set TIM4_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_EV_IRQHandler
|
||||
.thumb_set I2C1_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_ER_IRQHandler
|
||||
.thumb_set I2C1_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C2_EV_IRQHandler
|
||||
.thumb_set I2C2_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C2_ER_IRQHandler
|
||||
.thumb_set I2C2_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI1_IRQHandler
|
||||
.thumb_set SPI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI2_IRQHandler
|
||||
.thumb_set SPI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART1_IRQHandler
|
||||
.thumb_set USART1_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART2_IRQHandler
|
||||
.thumb_set USART2_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART3_IRQHandler
|
||||
.thumb_set USART3_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI15_10_IRQHandler
|
||||
.thumb_set EXTI15_10_IRQHandler,Default_Handler
|
||||
|
||||
.weak RTC_Alarm_IRQHandler
|
||||
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTG_FS_WKUP_IRQHandler
|
||||
.thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM8_BRK_TIM12_IRQHandler
|
||||
.thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM8_UP_TIM13_IRQHandler
|
||||
.thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM8_TRG_COM_TIM14_IRQHandler
|
||||
.thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM8_CC_IRQHandler
|
||||
.thumb_set TIM8_CC_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream7_IRQHandler
|
||||
.thumb_set DMA1_Stream7_IRQHandler,Default_Handler
|
||||
|
||||
.weak FSMC_IRQHandler
|
||||
.thumb_set FSMC_IRQHandler,Default_Handler
|
||||
|
||||
.weak SDIO_IRQHandler
|
||||
.thumb_set SDIO_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM5_IRQHandler
|
||||
.thumb_set TIM5_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI3_IRQHandler
|
||||
.thumb_set SPI3_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART4_IRQHandler
|
||||
.thumb_set UART4_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART5_IRQHandler
|
||||
.thumb_set UART5_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM6_DAC_IRQHandler
|
||||
.thumb_set TIM6_DAC_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM7_IRQHandler
|
||||
.thumb_set TIM7_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream0_IRQHandler
|
||||
.thumb_set DMA2_Stream0_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream1_IRQHandler
|
||||
.thumb_set DMA2_Stream1_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream2_IRQHandler
|
||||
.thumb_set DMA2_Stream2_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream3_IRQHandler
|
||||
.thumb_set DMA2_Stream3_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream4_IRQHandler
|
||||
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN2_TX_IRQHandler
|
||||
.thumb_set CAN2_TX_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN2_RX0_IRQHandler
|
||||
.thumb_set CAN2_RX0_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN2_RX1_IRQHandler
|
||||
.thumb_set CAN2_RX1_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN2_SCE_IRQHandler
|
||||
.thumb_set CAN2_SCE_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTG_FS_IRQHandler
|
||||
.thumb_set OTG_FS_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream5_IRQHandler
|
||||
.thumb_set DMA2_Stream5_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream6_IRQHandler
|
||||
.thumb_set DMA2_Stream6_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream7_IRQHandler
|
||||
.thumb_set DMA2_Stream7_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART6_IRQHandler
|
||||
.thumb_set USART6_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C3_EV_IRQHandler
|
||||
.thumb_set I2C3_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C3_ER_IRQHandler
|
||||
.thumb_set I2C3_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTG_HS_EP1_OUT_IRQHandler
|
||||
.thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTG_HS_EP1_IN_IRQHandler
|
||||
.thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTG_HS_WKUP_IRQHandler
|
||||
.thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTG_HS_IRQHandler
|
||||
.thumb_set OTG_HS_IRQHandler,Default_Handler
|
||||
|
||||
.weak HASH_RNG_IRQHandler
|
||||
.thumb_set HASH_RNG_IRQHandler,Default_Handler
|
||||
|
||||
.weak FPU_IRQHandler
|
||||
.thumb_set FPU_IRQHandler,Default_Handler
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
||||
|
||||
@ -32,5 +32,7 @@
|
||||
#define FLASH_SIZE (0x100000)
|
||||
#define FLASH_PAGE_SIZE (0x4000)
|
||||
|
||||
#define BOARD_OSC_DIV 8
|
||||
|
||||
#define DEFAULT_I2C_BUS_SCL (&pin_PB10)
|
||||
#define DEFAULT_I2C_BUS_SDA (&pin_PB09)
|
||||
|
||||
38
ports/stm32f4/boards/stm32f4_discovery/board.c
Normal file
38
ports/stm32f4/boards/stm32f4_discovery/board.c
Normal file
@ -0,0 +1,38 @@
|
||||
/*
|
||||
* This file is part of the MicroPython project, http://micropython.org/
|
||||
*
|
||||
* The MIT License (MIT)
|
||||
*
|
||||
* Copyright (c) 2017 Scott Shawcroft for Adafruit Industries
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#include "boards/board.h"
|
||||
|
||||
void board_init(void) {
|
||||
}
|
||||
|
||||
bool board_requests_safe_mode(void) {
|
||||
return false;
|
||||
}
|
||||
|
||||
void reset_board(void) {
|
||||
|
||||
}
|
||||
35
ports/stm32f4/boards/stm32f4_discovery/mpconfigboard.h
Normal file
35
ports/stm32f4/boards/stm32f4_discovery/mpconfigboard.h
Normal file
@ -0,0 +1,35 @@
|
||||
/*
|
||||
* This file is part of the MicroPython project, http://micropython.org/
|
||||
*
|
||||
* The MIT License (MIT)
|
||||
*
|
||||
* Copyright (c) 2020 Lucian Copeland for Adafruit Industries
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*/
|
||||
|
||||
//Micropython setup
|
||||
|
||||
#define MICROPY_HW_BOARD_NAME "STM32F4_DISCO"
|
||||
#define MICROPY_HW_MCU_NAME "STM32F407VG"
|
||||
|
||||
#define FLASH_SIZE (0x100000)
|
||||
#define FLASH_PAGE_SIZE (0x4000)
|
||||
|
||||
#define BOARD_OSC_DIV 8
|
||||
18
ports/stm32f4/boards/stm32f4_discovery/mpconfigboard.mk
Normal file
18
ports/stm32f4/boards/stm32f4_discovery/mpconfigboard.mk
Normal file
@ -0,0 +1,18 @@
|
||||
USB_VID = 0x239A
|
||||
USB_PID = 0x808A
|
||||
USB_PRODUCT = "STM32F407VG Discovery Board - CPy"
|
||||
USB_MANUFACTURER = "STMicroelectronics"
|
||||
USB_DEVICES = "CDC,MSC"
|
||||
|
||||
INTERNAL_FLASH_FILESYSTEM = 1
|
||||
LONGINT_IMPL = NONE
|
||||
|
||||
# This is technically a F407 but there's no difference
|
||||
# other than the camera and ethernet, which aren't supported.
|
||||
MCU_SERIES = m4
|
||||
MCU_VARIANT = stm32f4
|
||||
MCU_SUB_VARIANT = stm32f407xx
|
||||
MCU_PACKAGE = 100
|
||||
CMSIS_MCU = STM32F407xx
|
||||
LD_FILE = boards/STM32F407_fs.ld
|
||||
|
||||
107
ports/stm32f4/boards/stm32f4_discovery/pins.c
Normal file
107
ports/stm32f4/boards/stm32f4_discovery/pins.c
Normal file
@ -0,0 +1,107 @@
|
||||
#include "shared-bindings/board/__init__.h"
|
||||
|
||||
STATIC const mp_rom_map_elem_t board_module_globals_table[] = {
|
||||
//P1
|
||||
{ MP_ROM_QSTR(MP_QSTR_PC00), MP_ROM_PTR(&pin_PC00) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_PC01), MP_ROM_PTR(&pin_PC01) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_PC02), MP_ROM_PTR(&pin_PC02) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_PC03), MP_ROM_PTR(&pin_PC03) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_PA00), MP_ROM_PTR(&pin_PA00) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_PA01), MP_ROM_PTR(&pin_PA01) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_PA02), MP_ROM_PTR(&pin_PA02) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_PA03), MP_ROM_PTR(&pin_PA03) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_PA04), MP_ROM_PTR(&pin_PA04) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_PA05), MP_ROM_PTR(&pin_PA05) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_PA06), MP_ROM_PTR(&pin_PA06) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_PA07), MP_ROM_PTR(&pin_PA07) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_PC04), MP_ROM_PTR(&pin_PC04) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_PC05), MP_ROM_PTR(&pin_PC05) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_PB00), MP_ROM_PTR(&pin_PB00) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_PB01), MP_ROM_PTR(&pin_PB01) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_PB02), MP_ROM_PTR(&pin_PB02) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_PE07), MP_ROM_PTR(&pin_PE07) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_PE08), MP_ROM_PTR(&pin_PE08) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_PE09), MP_ROM_PTR(&pin_PE09) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_PE10), MP_ROM_PTR(&pin_PE10) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_PE11), MP_ROM_PTR(&pin_PE11) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_PE12), MP_ROM_PTR(&pin_PE12) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_PE13), MP_ROM_PTR(&pin_PE13) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_PE14), MP_ROM_PTR(&pin_PE14) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_PE15), MP_ROM_PTR(&pin_PE15) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_PB11), MP_ROM_PTR(&pin_PB11) }, // Differs from F411
|
||||
{ MP_ROM_QSTR(MP_QSTR_PB10), MP_ROM_PTR(&pin_PB10) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_PB12), MP_ROM_PTR(&pin_PB12) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_PB13), MP_ROM_PTR(&pin_PB13) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_PB14), MP_ROM_PTR(&pin_PB14) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_PB15), MP_ROM_PTR(&pin_PB15) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_PD08), MP_ROM_PTR(&pin_PD08) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_PD09), MP_ROM_PTR(&pin_PD09) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_PD10), MP_ROM_PTR(&pin_PD10) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_PD11), MP_ROM_PTR(&pin_PD11) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_PD12), MP_ROM_PTR(&pin_PD12) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_PD13), MP_ROM_PTR(&pin_PD13) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_PD14), MP_ROM_PTR(&pin_PD14) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_PD15), MP_ROM_PTR(&pin_PD15) },
|
||||
//P2
|
||||
{ MP_ROM_QSTR(MP_QSTR_PC14), MP_ROM_PTR(&pin_PC14) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_PC15), MP_ROM_PTR(&pin_PC15) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_PC13), MP_ROM_PTR(&pin_PC13) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_PE06), MP_ROM_PTR(&pin_PE06) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_PE05), MP_ROM_PTR(&pin_PE05) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_PE04), MP_ROM_PTR(&pin_PE04) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_PE03), MP_ROM_PTR(&pin_PE03) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_PE02), MP_ROM_PTR(&pin_PE02) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_PE01), MP_ROM_PTR(&pin_PE01) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_PE00), MP_ROM_PTR(&pin_PE00) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_PB09), MP_ROM_PTR(&pin_PB09) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_PB08), MP_ROM_PTR(&pin_PB08) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_PB07), MP_ROM_PTR(&pin_PB07) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_PB06), MP_ROM_PTR(&pin_PB06) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_PB05), MP_ROM_PTR(&pin_PB05) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_PB04), MP_ROM_PTR(&pin_PB04) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_PB03), MP_ROM_PTR(&pin_PB03) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_PD07), MP_ROM_PTR(&pin_PD07) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_PD06), MP_ROM_PTR(&pin_PD06) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_PD05), MP_ROM_PTR(&pin_PD05) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_PD04), MP_ROM_PTR(&pin_PD04) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_PD03), MP_ROM_PTR(&pin_PD03) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_PD02), MP_ROM_PTR(&pin_PD02) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_PD01), MP_ROM_PTR(&pin_PD01) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_PD00), MP_ROM_PTR(&pin_PD00) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_PC12), MP_ROM_PTR(&pin_PC12) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_PC11), MP_ROM_PTR(&pin_PC11) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_PC10), MP_ROM_PTR(&pin_PC10) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_PA15), MP_ROM_PTR(&pin_PA15) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_PA14), MP_ROM_PTR(&pin_PA14) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_PA13), MP_ROM_PTR(&pin_PA13) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_PA10), MP_ROM_PTR(&pin_PA10) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_PA09), MP_ROM_PTR(&pin_PA09) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_PA08), MP_ROM_PTR(&pin_PA08) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_PC09), MP_ROM_PTR(&pin_PC09) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_PC08), MP_ROM_PTR(&pin_PC08) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_PC07), MP_ROM_PTR(&pin_PC07) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_PC06), MP_ROM_PTR(&pin_PC06) },
|
||||
//ST LED names
|
||||
{ MP_ROM_QSTR(MP_QSTR_LD3), MP_ROM_PTR(&pin_PD13) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_LD4), MP_ROM_PTR(&pin_PD12) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_LD5), MP_ROM_PTR(&pin_PD14) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_LD6), MP_ROM_PTR(&pin_PD15) },
|
||||
//more useful LED names
|
||||
{ MP_ROM_QSTR(MP_QSTR_LED1), MP_ROM_PTR(&pin_PD13) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_LED2), MP_ROM_PTR(&pin_PD12) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_LED3), MP_ROM_PTR(&pin_PD14) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_LED4), MP_ROM_PTR(&pin_PD15) },
|
||||
//AnalogIO names
|
||||
{ MP_ROM_QSTR(MP_QSTR_A0), MP_ROM_PTR(&pin_PA00) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_A1), MP_ROM_PTR(&pin_PA01) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_A2), MP_ROM_PTR(&pin_PA02) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_A3), MP_ROM_PTR(&pin_PA03) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_A4), MP_ROM_PTR(&pin_PA04) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_A5), MP_ROM_PTR(&pin_PA05) },
|
||||
//actual LED names
|
||||
{ MP_ROM_QSTR(MP_QSTR_LED_ORANGE), MP_ROM_PTR(&pin_PD13) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_LED_GREEN), MP_ROM_PTR(&pin_PD12) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_LED_RED), MP_ROM_PTR(&pin_PD14) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_LED_BLUE), MP_ROM_PTR(&pin_PD15) },
|
||||
};
|
||||
MP_DEFINE_CONST_DICT(board_module_globals, board_module_globals_table);
|
||||
439
ports/stm32f4/boards/stm32f4_discovery/stm32f4xx_hal_conf.h
Normal file
439
ports/stm32f4/boards/stm32f4_discovery/stm32f4xx_hal_conf.h
Normal file
@ -0,0 +1,439 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f4xx_hal_conf_template.h
|
||||
* @author MCD Application Team
|
||||
* @brief HAL configuration template file.
|
||||
* This file should be copied to the application folder and renamed
|
||||
* to stm32f4xx_hal_conf.h.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F4xx_HAL_CONF_H
|
||||
#define __STM32F4xx_HAL_CONF_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/* ########################## Module Selection ############################## */
|
||||
/**
|
||||
* @brief This is the list of modules to be used in the HAL driver
|
||||
*/
|
||||
#define HAL_MODULE_ENABLED
|
||||
|
||||
#define HAL_ADC_MODULE_ENABLED
|
||||
/* #define HAL_CRYP_MODULE_ENABLED */
|
||||
/* #define HAL_CAN_MODULE_ENABLED */
|
||||
/* #define HAL_CRC_MODULE_ENABLED */
|
||||
/* #define HAL_CRYP_MODULE_ENABLED */
|
||||
#define HAL_DAC_MODULE_ENABLED
|
||||
/* #define HAL_DCMI_MODULE_ENABLED */
|
||||
/* #define HAL_DMA2D_MODULE_ENABLED */
|
||||
/* #define HAL_ETH_MODULE_ENABLED */
|
||||
/* #define HAL_NAND_MODULE_ENABLED */
|
||||
/* #define HAL_NOR_MODULE_ENABLED */
|
||||
/* #define HAL_PCCARD_MODULE_ENABLED */
|
||||
/* #define HAL_SRAM_MODULE_ENABLED */
|
||||
/* #define HAL_SDRAM_MODULE_ENABLED */
|
||||
/* #define HAL_HASH_MODULE_ENABLED */
|
||||
#define HAL_I2C_MODULE_ENABLED
|
||||
#define HAL_I2S_MODULE_ENABLED
|
||||
/* #define HAL_IWDG_MODULE_ENABLED */
|
||||
/* #define HAL_LTDC_MODULE_ENABLED */
|
||||
#define HAL_RNG_MODULE_ENABLED
|
||||
/* #define HAL_RTC_MODULE_ENABLED */
|
||||
/* #define HAL_SAI_MODULE_ENABLED */
|
||||
/* #define HAL_SD_MODULE_ENABLED */
|
||||
/* #define HAL_MMC_MODULE_ENABLED */
|
||||
#define HAL_SPI_MODULE_ENABLED
|
||||
#define HAL_TIM_MODULE_ENABLED
|
||||
#define HAL_UART_MODULE_ENABLED
|
||||
#define HAL_USART_MODULE_ENABLED
|
||||
/* #define HAL_IRDA_MODULE_ENABLED */
|
||||
/* #define HAL_SMARTCARD_MODULE_ENABLED */
|
||||
/* #define HAL_WWDG_MODULE_ENABLED */
|
||||
#define HAL_PCD_MODULE_ENABLED
|
||||
/* #define HAL_HCD_MODULE_ENABLED */
|
||||
/* #define HAL_DSI_MODULE_ENABLED */
|
||||
/* #define HAL_QSPI_MODULE_ENABLED */
|
||||
/* #define HAL_QSPI_MODULE_ENABLED */
|
||||
/* #define HAL_CEC_MODULE_ENABLED */
|
||||
/* #define HAL_FMPI2C_MODULE_ENABLED */
|
||||
/* #define HAL_SPDIFRX_MODULE_ENABLED */
|
||||
/* #define HAL_DFSDM_MODULE_ENABLED */
|
||||
/* #define HAL_LPTIM_MODULE_ENABLED */
|
||||
/* #define HAL_EXTI_MODULE_ENABLED */
|
||||
#define HAL_GPIO_MODULE_ENABLED
|
||||
#define HAL_EXTI_MODULE_ENABLED
|
||||
#define HAL_DMA_MODULE_ENABLED
|
||||
#define HAL_RCC_MODULE_ENABLED
|
||||
#define HAL_FLASH_MODULE_ENABLED
|
||||
#define HAL_PWR_MODULE_ENABLED
|
||||
#define HAL_CORTEX_MODULE_ENABLED
|
||||
|
||||
/* ########################## HSE/HSI Values adaptation ##################### */
|
||||
/**
|
||||
* @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
|
||||
* This value is used by the RCC HAL module to compute the system frequency
|
||||
* (when HSE is used as system clock source, directly or through the PLL).
|
||||
*/
|
||||
#if !defined (HSE_VALUE)
|
||||
#define HSE_VALUE ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */
|
||||
#endif /* HSE_VALUE */
|
||||
|
||||
#if !defined (HSE_STARTUP_TIMEOUT)
|
||||
#define HSE_STARTUP_TIMEOUT ((uint32_t)100U) /*!< Time out for HSE start up, in ms */
|
||||
#endif /* HSE_STARTUP_TIMEOUT */
|
||||
|
||||
/**
|
||||
* @brief Internal High Speed oscillator (HSI) value.
|
||||
* This value is used by the RCC HAL module to compute the system frequency
|
||||
* (when HSI is used as system clock source, directly or through the PLL).
|
||||
*/
|
||||
#if !defined (HSI_VALUE)
|
||||
#define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/
|
||||
#endif /* HSI_VALUE */
|
||||
|
||||
/**
|
||||
* @brief Internal Low Speed oscillator (LSI) value.
|
||||
*/
|
||||
#if !defined (LSI_VALUE)
|
||||
#define LSI_VALUE ((uint32_t)32000U) /*!< LSI Typical Value in Hz*/
|
||||
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
|
||||
The real value may vary depending on the variations
|
||||
in voltage and temperature.*/
|
||||
/**
|
||||
* @brief External Low Speed oscillator (LSE) value.
|
||||
*/
|
||||
#if !defined (LSE_VALUE)
|
||||
#define LSE_VALUE ((uint32_t)32768U) /*!< Value of the External Low Speed oscillator in Hz */
|
||||
#endif /* LSE_VALUE */
|
||||
|
||||
#if !defined (LSE_STARTUP_TIMEOUT)
|
||||
#define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */
|
||||
#endif /* LSE_STARTUP_TIMEOUT */
|
||||
|
||||
/**
|
||||
* @brief External clock source for I2S peripheral
|
||||
* This value is used by the I2S HAL module to compute the I2S clock source
|
||||
* frequency, this source is inserted directly through I2S_CKIN pad.
|
||||
*/
|
||||
#if !defined (EXTERNAL_CLOCK_VALUE)
|
||||
#define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000U) /*!< Value of the External audio frequency in Hz*/
|
||||
#endif /* EXTERNAL_CLOCK_VALUE */
|
||||
|
||||
/* Tip: To avoid modifying this file each time you need to use different HSE,
|
||||
=== you can define the HSE value in your toolchain compiler preprocessor. */
|
||||
|
||||
/* ########################### System Configuration ######################### */
|
||||
/**
|
||||
* @brief This is the HAL system configuration section
|
||||
*/
|
||||
#define VDD_VALUE ((uint32_t)3300U) /*!< Value of VDD in mv */
|
||||
#define TICK_INT_PRIORITY ((uint32_t)0U) /*!< tick interrupt priority */
|
||||
#define USE_RTOS 0U
|
||||
#define PREFETCH_ENABLE 1U
|
||||
#define INSTRUCTION_CACHE_ENABLE 1U
|
||||
#define DATA_CACHE_ENABLE 1U
|
||||
|
||||
/* ########################## Assert Selection ############################## */
|
||||
/**
|
||||
* @brief Uncomment the line below to expanse the "assert_param" macro in the
|
||||
* HAL drivers code
|
||||
*/
|
||||
/* #define USE_FULL_ASSERT 1U */
|
||||
|
||||
/* ################## Ethernet peripheral configuration ##################### */
|
||||
|
||||
/* Section 1 : Ethernet peripheral configuration */
|
||||
|
||||
/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
|
||||
#define MAC_ADDR0 2U
|
||||
#define MAC_ADDR1 0U
|
||||
#define MAC_ADDR2 0U
|
||||
#define MAC_ADDR3 0U
|
||||
#define MAC_ADDR4 0U
|
||||
#define MAC_ADDR5 0U
|
||||
|
||||
/* Definition of the Ethernet driver buffers size and count */
|
||||
#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */
|
||||
#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */
|
||||
#define ETH_RXBUFNB ((uint32_t)4U) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */
|
||||
#define ETH_TXBUFNB ((uint32_t)4U) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */
|
||||
|
||||
/* Section 2: PHY configuration section */
|
||||
|
||||
/* DP83848_PHY_ADDRESS Address*/
|
||||
#define DP83848_PHY_ADDRESS 0x01U
|
||||
/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
|
||||
#define PHY_RESET_DELAY ((uint32_t)0x000000FFU)
|
||||
/* PHY Configuration delay */
|
||||
#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFFU)
|
||||
|
||||
#define PHY_READ_TO ((uint32_t)0x0000FFFFU)
|
||||
#define PHY_WRITE_TO ((uint32_t)0x0000FFFFU)
|
||||
|
||||
/* Section 3: Common PHY Registers */
|
||||
|
||||
#define PHY_BCR ((uint16_t)0x0000U) /*!< Transceiver Basic Control Register */
|
||||
#define PHY_BSR ((uint16_t)0x0001U) /*!< Transceiver Basic Status Register */
|
||||
|
||||
#define PHY_RESET ((uint16_t)0x8000U) /*!< PHY Reset */
|
||||
#define PHY_LOOPBACK ((uint16_t)0x4000U) /*!< Select loop-back mode */
|
||||
#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100U) /*!< Set the full-duplex mode at 100 Mb/s */
|
||||
#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000U) /*!< Set the half-duplex mode at 100 Mb/s */
|
||||
#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100U) /*!< Set the full-duplex mode at 10 Mb/s */
|
||||
#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000U) /*!< Set the half-duplex mode at 10 Mb/s */
|
||||
#define PHY_AUTONEGOTIATION ((uint16_t)0x1000U) /*!< Enable auto-negotiation function */
|
||||
#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200U) /*!< Restart auto-negotiation function */
|
||||
#define PHY_POWERDOWN ((uint16_t)0x0800U) /*!< Select the power down mode */
|
||||
#define PHY_ISOLATE ((uint16_t)0x0400U) /*!< Isolate PHY from MII */
|
||||
|
||||
#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020U) /*!< Auto-Negotiation process completed */
|
||||
#define PHY_LINKED_STATUS ((uint16_t)0x0004U) /*!< Valid link established */
|
||||
#define PHY_JABBER_DETECTION ((uint16_t)0x0002U) /*!< Jabber condition detected */
|
||||
|
||||
/* Section 4: Extended PHY Registers */
|
||||
#define PHY_SR ((uint16_t)0x10U) /*!< PHY status register Offset */
|
||||
|
||||
#define PHY_SPEED_STATUS ((uint16_t)0x0002U) /*!< PHY Speed mask */
|
||||
#define PHY_DUPLEX_STATUS ((uint16_t)0x0004U) /*!< PHY Duplex mask */
|
||||
|
||||
/* ################## SPI peripheral configuration ########################## */
|
||||
|
||||
/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
|
||||
* Activated: CRC code is present inside driver
|
||||
* Deactivated: CRC code cleaned from driver
|
||||
*/
|
||||
|
||||
#define USE_SPI_CRC 0U
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
/**
|
||||
* @brief Include module's header file
|
||||
*/
|
||||
|
||||
#ifdef HAL_RCC_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_rcc.h"
|
||||
#endif /* HAL_RCC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_EXTI_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_exti.h"
|
||||
#endif /* HAL_EXTI_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_GPIO_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_gpio.h"
|
||||
#endif /* HAL_GPIO_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_DMA_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_dma.h"
|
||||
#endif /* HAL_DMA_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_CORTEX_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_cortex.h"
|
||||
#endif /* HAL_CORTEX_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_ADC_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_adc.h"
|
||||
#endif /* HAL_ADC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_CAN_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_can.h"
|
||||
#endif /* HAL_CAN_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_CRC_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_crc.h"
|
||||
#endif /* HAL_CRC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_CRYP_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_cryp.h"
|
||||
#endif /* HAL_CRYP_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_DMA2D_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_dma2d.h"
|
||||
#endif /* HAL_DMA2D_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_DAC_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_dac.h"
|
||||
#endif /* HAL_DAC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_DCMI_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_dcmi.h"
|
||||
#endif /* HAL_DCMI_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_ETH_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_eth.h"
|
||||
#endif /* HAL_ETH_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_FLASH_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_flash.h"
|
||||
#endif /* HAL_FLASH_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SRAM_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_sram.h"
|
||||
#endif /* HAL_SRAM_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_NOR_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_nor.h"
|
||||
#endif /* HAL_NOR_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_NAND_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_nand.h"
|
||||
#endif /* HAL_NAND_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_PCCARD_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_pccard.h"
|
||||
#endif /* HAL_PCCARD_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SDRAM_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_sdram.h"
|
||||
#endif /* HAL_SDRAM_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_HASH_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_hash.h"
|
||||
#endif /* HAL_HASH_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_I2C_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_i2c.h"
|
||||
#endif /* HAL_I2C_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_I2S_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_i2s.h"
|
||||
#endif /* HAL_I2S_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_IWDG_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_iwdg.h"
|
||||
#endif /* HAL_IWDG_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_LTDC_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_ltdc.h"
|
||||
#endif /* HAL_LTDC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_PWR_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_pwr.h"
|
||||
#endif /* HAL_PWR_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_RNG_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_rng.h"
|
||||
#endif /* HAL_RNG_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_RTC_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_rtc.h"
|
||||
#endif /* HAL_RTC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SAI_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_sai.h"
|
||||
#endif /* HAL_SAI_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SD_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_sd.h"
|
||||
#endif /* HAL_SD_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_MMC_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_mmc.h"
|
||||
#endif /* HAL_MMC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SPI_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_spi.h"
|
||||
#endif /* HAL_SPI_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_TIM_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_tim.h"
|
||||
#endif /* HAL_TIM_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_UART_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_uart.h"
|
||||
#endif /* HAL_UART_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_USART_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_usart.h"
|
||||
#endif /* HAL_USART_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_IRDA_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_irda.h"
|
||||
#endif /* HAL_IRDA_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SMARTCARD_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_smartcard.h"
|
||||
#endif /* HAL_SMARTCARD_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_WWDG_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_wwdg.h"
|
||||
#endif /* HAL_WWDG_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_PCD_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_pcd.h"
|
||||
#endif /* HAL_PCD_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_HCD_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_hcd.h"
|
||||
#endif /* HAL_HCD_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_DSI_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_dsi.h"
|
||||
#endif /* HAL_DSI_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_QSPI_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_qspi.h"
|
||||
#endif /* HAL_QSPI_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_CEC_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_cec.h"
|
||||
#endif /* HAL_CEC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_FMPI2C_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_fmpi2c.h"
|
||||
#endif /* HAL_FMPI2C_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SPDIFRX_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_spdifrx.h"
|
||||
#endif /* HAL_SPDIFRX_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_DFSDM_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_dfsdm.h"
|
||||
#endif /* HAL_DFSDM_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_LPTIM_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_lptim.h"
|
||||
#endif /* HAL_LPTIM_MODULE_ENABLED */
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
#ifdef USE_FULL_ASSERT
|
||||
/**
|
||||
* @brief The assert_param macro is used for function's parameters check.
|
||||
* @param expr: If expr is false, it calls assert_failed function
|
||||
* which reports the name of the source file and the source
|
||||
* line number of the call that failed.
|
||||
* If expr is true, it returns no value.
|
||||
* @retval None
|
||||
*/
|
||||
#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
void assert_failed(uint8_t* file, uint32_t line);
|
||||
#else
|
||||
#define assert_param(expr) ((void)0U)
|
||||
#endif /* USE_FULL_ASSERT */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F4xx_HAL_CONF_H */
|
||||
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@ -166,4 +166,10 @@ typedef struct {
|
||||
#include "stm32f405xx/periph.h"
|
||||
#endif
|
||||
|
||||
#ifdef STM32F407xx
|
||||
#define HAS_DAC 1
|
||||
#define HAS_TRNG 1
|
||||
#include "stm32f407xx/periph.h"
|
||||
#endif
|
||||
|
||||
#endif // __MICROPY_INCLUDED_STM32F4_PERIPHERALS_PERIPH_H__
|
||||
|
||||
@ -89,5 +89,8 @@ extern const mp_obj_type_t mcu_pin_type;
|
||||
#ifdef STM32F405xx
|
||||
#include "stm32f405xx/pins.h"
|
||||
#endif
|
||||
#ifdef STM32F407xx
|
||||
#include "stm32f407xx/pins.h"
|
||||
#endif
|
||||
|
||||
#endif // __MICROPY_INCLUDED_STM32F4_PERIPHERALS_PINS_H__
|
||||
|
||||
@ -25,6 +25,7 @@
|
||||
* THE SOFTWARE.
|
||||
*/
|
||||
#include "stm32f4xx_hal.h"
|
||||
#include "py/mpconfig.h"
|
||||
|
||||
void stm32f4_peripherals_clocks_init(void) {
|
||||
//TODO: All parameters must be moved to board level, due to relationship with HSE Osc.
|
||||
@ -46,7 +47,7 @@ void stm32f4_peripherals_clocks_init(void) {
|
||||
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
||||
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
|
||||
RCC_OscInitStruct.PLL.PLLM = 12;
|
||||
RCC_OscInitStruct.PLL.PLLM = BOARD_OSC_DIV;
|
||||
RCC_OscInitStruct.PLL.PLLN = 336;
|
||||
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
|
||||
RCC_OscInitStruct.PLL.PLLQ = 7;
|
||||
|
||||
64
ports/stm32f4/peripherals/stm32f4/stm32f407xx/clocks.c
Normal file
64
ports/stm32f4/peripherals/stm32f4/stm32f407xx/clocks.c
Normal file
@ -0,0 +1,64 @@
|
||||
|
||||
/*
|
||||
* This file is part of the Micro Python project, http://micropython.org/
|
||||
*
|
||||
* The MIT License (MIT)
|
||||
*
|
||||
* Copyright (c) 2019 Lucian Copeland for Adafruit Industries
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*/
|
||||
#include "stm32f4xx_hal.h"
|
||||
#include "py/mpconfig.h"
|
||||
|
||||
void stm32f4_peripherals_clocks_init(void) {
|
||||
//TODO: All parameters must be moved to board level, due to relationship with HSE Osc.
|
||||
|
||||
//System clock init
|
||||
RCC_ClkInitTypeDef RCC_ClkInitStruct;
|
||||
RCC_OscInitTypeDef RCC_OscInitStruct;
|
||||
|
||||
/* Enable Power Control clock */
|
||||
__HAL_RCC_PWR_CLK_ENABLE();
|
||||
|
||||
/* The voltage scaling allows optimizing the power consumption when the device is
|
||||
clocked below the maximum system frequency, to update the voltage scaling value
|
||||
regarding system frequency refer to product datasheet. */
|
||||
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
|
||||
|
||||
/* Enable HSE Oscillator and activate PLL with HSE as source */
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
|
||||
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
||||
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
|
||||
RCC_OscInitStruct.PLL.PLLM = BOARD_OSC_DIV;
|
||||
RCC_OscInitStruct.PLL.PLLN = 336;
|
||||
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
|
||||
RCC_OscInitStruct.PLL.PLLQ = 7;
|
||||
HAL_RCC_OscConfig(&RCC_OscInitStruct);
|
||||
|
||||
/* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2
|
||||
clocks dividers */
|
||||
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
|
||||
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
|
||||
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
|
||||
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
|
||||
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
|
||||
HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5);
|
||||
}
|
||||
56
ports/stm32f4/peripherals/stm32f4/stm32f407xx/gpio.c
Normal file
56
ports/stm32f4/peripherals/stm32f4/stm32f407xx/gpio.c
Normal file
@ -0,0 +1,56 @@
|
||||
/*
|
||||
* This file is part of the Micro Python project, http://micropython.org/
|
||||
*
|
||||
* The MIT License (MIT)
|
||||
*
|
||||
* Copyright (c) 2019 Lucian Copeland for Adafruit Industries
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#include "stm32f4xx_hal.h"
|
||||
#include "stm32f4/gpio.h"
|
||||
#include "common-hal/microcontroller/Pin.h"
|
||||
|
||||
void stm32f4_peripherals_gpio_init(void) {
|
||||
//Enable all GPIO for now
|
||||
__HAL_RCC_GPIOC_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOA_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOB_CLK_ENABLE();
|
||||
|
||||
//Never reset pins
|
||||
never_reset_pin_number(2,13); //PC13 anti tamp
|
||||
never_reset_pin_number(2,14); //PC14 OSC32_IN
|
||||
never_reset_pin_number(2,15); //PC15 OSC32_OUT
|
||||
never_reset_pin_number(0,13); //PA13 SWDIO
|
||||
never_reset_pin_number(0,14); //PA14 SWCLK
|
||||
// never_reset_pin_number(0,15); //PA15 JTDI
|
||||
// never_reset_pin_number(1,3); //PB3 JTDO
|
||||
// never_reset_pin_number(1,4); //PB4 JTRST
|
||||
|
||||
// Port H is not included in GPIO port array
|
||||
// never_reset_pin_number(5,0); //PH0 JTDO
|
||||
// never_reset_pin_number(5,1); //PH1 JTRST
|
||||
}
|
||||
|
||||
void stm32f4_peripherals_status_led(uint8_t led, uint8_t state) {
|
||||
|
||||
}
|
||||
|
||||
|
||||
194
ports/stm32f4/peripherals/stm32f4/stm32f407xx/periph.c
Normal file
194
ports/stm32f4/peripherals/stm32f4/stm32f407xx/periph.c
Normal file
@ -0,0 +1,194 @@
|
||||
/*
|
||||
* This file is part of the MicroPython project, http://micropython.org/
|
||||
*
|
||||
* The MIT License (MIT)
|
||||
*
|
||||
* Copyright (c) 2019 Lucian Copeland for Adafruit Industries
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#include "py/obj.h"
|
||||
#include "py/mphal.h"
|
||||
#include "stm32f4/pins.h"
|
||||
#include "stm32f4/periph.h"
|
||||
|
||||
// I2C
|
||||
|
||||
I2C_TypeDef * mcu_i2c_banks[3] = {I2C1, I2C2, I2C3};
|
||||
|
||||
const mcu_i2c_sda_obj_t mcu_i2c_sda_list[4] = {
|
||||
I2C_SDA(1, 4, &pin_PB07),
|
||||
I2C_SDA(1, 4, &pin_PB09),
|
||||
I2C_SDA(2, 4, &pin_PB11),
|
||||
I2C_SDA(3, 4, &pin_PC09),
|
||||
};
|
||||
|
||||
const mcu_i2c_scl_obj_t mcu_i2c_scl_list[4] = {
|
||||
I2C_SCL(1, 4, &pin_PB06),
|
||||
I2C_SCL(1, 4, &pin_PB08),
|
||||
I2C_SCL(2, 4, &pin_PB10),
|
||||
I2C_SCL(3, 4, &pin_PA08)
|
||||
};
|
||||
|
||||
SPI_TypeDef * mcu_spi_banks[3] = {SPI1, SPI2, SPI3};
|
||||
|
||||
const mcu_spi_sck_obj_t mcu_spi_sck_list[7] = {
|
||||
SPI(1, 5, &pin_PA05),
|
||||
SPI(1, 5, &pin_PB03),
|
||||
SPI(2, 5, &pin_PB10),
|
||||
SPI(2, 5, &pin_PB13),
|
||||
SPI(2, 5, &pin_PC07),
|
||||
SPI(3, 6, &pin_PB03),
|
||||
SPI(3, 6, &pin_PC10),
|
||||
};
|
||||
|
||||
const mcu_spi_mosi_obj_t mcu_spi_mosi_list[6] = {
|
||||
SPI(1, 5, &pin_PA07),
|
||||
SPI(1, 5, &pin_PB05),
|
||||
SPI(2, 5, &pin_PB15),
|
||||
SPI(2, 5, &pin_PC03),
|
||||
SPI(3, 6, &pin_PB05),
|
||||
SPI(3, 6, &pin_PC12),
|
||||
};
|
||||
|
||||
const mcu_spi_miso_obj_t mcu_spi_miso_list[6] = {
|
||||
SPI(1, 5, &pin_PA06),
|
||||
SPI(1, 5, &pin_PB04),
|
||||
SPI(2, 5, &pin_PB14),
|
||||
SPI(2, 5, &pin_PC02),
|
||||
SPI(3, 6, &pin_PB04),
|
||||
SPI(3, 6, &pin_PC11),
|
||||
};
|
||||
|
||||
const mcu_spi_nss_obj_t mcu_spi_nss_list[6] = {
|
||||
SPI(1, 5, &pin_PA04),
|
||||
SPI(1, 5, &pin_PA15),
|
||||
SPI(2, 5, &pin_PB09),
|
||||
SPI(2, 5, &pin_PB12),
|
||||
SPI(3, 6, &pin_PA04),
|
||||
SPI(3, 6, &pin_PA15),
|
||||
};
|
||||
|
||||
USART_TypeDef * mcu_uart_banks[MAX_UART] = {USART1, USART2, USART3, UART4, UART5, USART6};
|
||||
bool mcu_uart_has_usart[MAX_UART] = {true, true, true, false, false, true};
|
||||
|
||||
const mcu_uart_tx_obj_t mcu_uart_tx_list[12] = {
|
||||
UART(4, 8, &pin_PA00),
|
||||
UART(2, 7, &pin_PA02),
|
||||
UART(1, 7, &pin_PA09),
|
||||
UART(1, 7, &pin_PB06),
|
||||
UART(3, 7, &pin_PB10),
|
||||
UART(6, 8, &pin_PC06),
|
||||
UART(3, 7, &pin_PC10),
|
||||
UART(4, 8, &pin_PC10),
|
||||
UART(5, 8, &pin_PC12),
|
||||
UART(2, 7, &pin_PD05),
|
||||
UART(3, 7, &pin_PD08),
|
||||
UART(6, 8, &pin_PG14),
|
||||
};
|
||||
|
||||
const mcu_uart_rx_obj_t mcu_uart_rx_list[12] = {
|
||||
UART(4, 8, &pin_PA01),
|
||||
UART(2, 7, &pin_PA03),
|
||||
UART(1, 7, &pin_PA10),
|
||||
UART(1, 7, &pin_PB07),
|
||||
UART(3, 7, &pin_PB11),
|
||||
UART(6, 8, &pin_PC07),
|
||||
UART(3, 7, &pin_PC11),
|
||||
UART(4, 8, &pin_PC11),
|
||||
UART(5, 8, &pin_PD02),
|
||||
UART(2, 7, &pin_PD06),
|
||||
UART(3, 7, &pin_PD09),
|
||||
UART(6, 8, &pin_PG09),
|
||||
};
|
||||
|
||||
//Timers
|
||||
//TIM6 and TIM7 are basic timers that are only used by DAC, and don't have pins
|
||||
TIM_TypeDef * mcu_tim_banks[14] = {TIM1, TIM2, TIM3, TIM4, TIM5, NULL, NULL, TIM8, TIM9, TIM10,
|
||||
TIM11, TIM12, TIM13, TIM14};
|
||||
|
||||
const mcu_tim_pin_obj_t mcu_tim_pin_list[56] = {
|
||||
TIM(2,1,1,&pin_PA00),
|
||||
TIM(5,2,1,&pin_PA00),
|
||||
TIM(2,1,2,&pin_PA01),
|
||||
TIM(5,2,2,&pin_PA01),
|
||||
TIM(2,1,3,&pin_PA02),
|
||||
TIM(5,2,3,&pin_PA02),
|
||||
TIM(2,1,4,&pin_PA03),
|
||||
TIM(5,2,4,&pin_PA03),
|
||||
TIM(9,3,1,&pin_PA02),
|
||||
TIM(9,3,2,&pin_PA03),
|
||||
TIM(3,2,1,&pin_PA06),
|
||||
TIM(13,9,1,&pin_PA06),
|
||||
TIM(3,2,2,&pin_PA07),
|
||||
TIM(14,9,1,&pin_PA07),
|
||||
TIM(1,1,1,&pin_PA08),
|
||||
TIM(1,1,2,&pin_PA09),
|
||||
TIM(1,1,3,&pin_PA10),
|
||||
TIM(1,1,4,&pin_PA11),
|
||||
TIM(2,1,1,&pin_PA15),
|
||||
TIM(3,2,3,&pin_PB00),
|
||||
TIM(3,2,4,&pin_PB01),
|
||||
TIM(2,1,2,&pin_PB03),
|
||||
TIM(3,2,1,&pin_PB04),
|
||||
TIM(3,2,2,&pin_PB05),
|
||||
TIM(4,2,1,&pin_PB06),
|
||||
TIM(4,2,2,&pin_PB07),
|
||||
TIM(4,2,3,&pin_PB08),
|
||||
TIM(10,2,1,&pin_PB08),
|
||||
TIM(4,2,4,&pin_PB09),
|
||||
TIM(11,2,1,&pin_PB09),
|
||||
TIM(2,1,3,&pin_PB10),
|
||||
TIM(2,1,4,&pin_PB11),
|
||||
TIM(12,9,1,&pin_PB14),
|
||||
TIM(12,9,2,&pin_PB15),
|
||||
TIM(3,2,1,&pin_PC06),
|
||||
TIM(3,2,2,&pin_PC07),
|
||||
TIM(3,2,3,&pin_PC08),
|
||||
TIM(3,2,4,&pin_PC09),
|
||||
TIM(8,3,1,&pin_PC06),
|
||||
TIM(8,3,2,&pin_PC07),
|
||||
TIM(8,3,3,&pin_PC08),
|
||||
TIM(8,3,4,&pin_PC09),
|
||||
TIM(4,2,1,&pin_PD12),
|
||||
TIM(4,2,2,&pin_PD13),
|
||||
TIM(4,2,3,&pin_PD14),
|
||||
TIM(4,2,4,&pin_PD15),
|
||||
TIM(9,3,1,&pin_PE05),
|
||||
TIM(9,3,2,&pin_PE06),
|
||||
TIM(1,1,1,&pin_PE09),
|
||||
TIM(1,1,2,&pin_PE11),
|
||||
TIM(1,1,3,&pin_PE13),
|
||||
TIM(1,1,4,&pin_PE14),
|
||||
TIM(10,3,1,&pin_PF06),
|
||||
TIM(11,3,1,&pin_PF07),
|
||||
TIM(13,9,1,&pin_PF08),
|
||||
TIM(14,9,1,&pin_PF09),
|
||||
// TIM(12,9,1,&pin_PH06), //TODO: include these when pin map is expanded
|
||||
// TIM(12,9,2,&pin_PH09),
|
||||
// TIM(5,2,1,&pin_PH10),
|
||||
// TIM(5,2,2,&pin_PH11),
|
||||
// TIM(5,2,3,&pin_PH12),
|
||||
// TIM(5,2,4,&pin_PI00),
|
||||
// TIM(8,3,4,&pin_PI02),
|
||||
// TIM(8,3,1,&pin_PI05),
|
||||
// TIM(8,3,2,&pin_PI06),
|
||||
// TIM(8,3,3,&pin_PI07),
|
||||
};
|
||||
57
ports/stm32f4/peripherals/stm32f4/stm32f407xx/periph.h
Normal file
57
ports/stm32f4/peripherals/stm32f4/stm32f407xx/periph.h
Normal file
@ -0,0 +1,57 @@
|
||||
/*
|
||||
* This file is part of the MicroPython project, http://micropython.org/
|
||||
*
|
||||
* The MIT License (MIT)
|
||||
*
|
||||
* Copyright (c) 2019 Lucian Copeland for Adafruit Industries
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef MICROPY_INCLUDED_STM32F4_PERIPHERALS_STM32F405XX_PERIPH_H
|
||||
#define MICROPY_INCLUDED_STM32F4_PERIPHERALS_STM32F405XX_PERIPH_H
|
||||
|
||||
//I2C
|
||||
extern I2C_TypeDef * mcu_i2c_banks[3];
|
||||
|
||||
extern const mcu_i2c_sda_obj_t mcu_i2c_sda_list[4];
|
||||
extern const mcu_i2c_scl_obj_t mcu_i2c_scl_list[4];
|
||||
|
||||
//SPI
|
||||
extern SPI_TypeDef * mcu_spi_banks[3];
|
||||
|
||||
extern const mcu_spi_sck_obj_t mcu_spi_sck_list[7];
|
||||
extern const mcu_spi_mosi_obj_t mcu_spi_mosi_list[6];
|
||||
extern const mcu_spi_miso_obj_t mcu_spi_miso_list[6];
|
||||
extern const mcu_spi_nss_obj_t mcu_spi_nss_list[6];
|
||||
|
||||
//UART
|
||||
extern USART_TypeDef * mcu_uart_banks[MAX_UART];
|
||||
extern bool mcu_uart_has_usart[MAX_UART];
|
||||
|
||||
extern const mcu_uart_tx_obj_t mcu_uart_tx_list[12];
|
||||
extern const mcu_uart_rx_obj_t mcu_uart_rx_list[12];
|
||||
|
||||
//Timers
|
||||
#define TIM_BANK_ARRAY_LEN 14
|
||||
#define TIM_PIN_ARRAY_LEN 56
|
||||
TIM_TypeDef * mcu_tim_banks[TIM_BANK_ARRAY_LEN];
|
||||
const mcu_tim_pin_obj_t mcu_tim_pin_list[TIM_PIN_ARRAY_LEN];
|
||||
|
||||
#endif // MICROPY_INCLUDED_STM32F4_PERIPHERALS_STM32F405XX_PERIPH_H
|
||||
161
ports/stm32f4/peripherals/stm32f4/stm32f407xx/pins.c
Normal file
161
ports/stm32f4/peripherals/stm32f4/stm32f407xx/pins.c
Normal file
@ -0,0 +1,161 @@
|
||||
/*
|
||||
* This file is part of the MicroPython project, http://micropython.org/
|
||||
*
|
||||
* The MIT License (MIT)
|
||||
*
|
||||
* Copyright (c) 2019 Lucian Copeland for Adafruit Industries
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#include "py/obj.h"
|
||||
#include "py/mphal.h"
|
||||
#include "stm32f4/pins.h"
|
||||
|
||||
const mcu_pin_obj_t pin_PE02 = PIN(4, 2, NO_ADC);
|
||||
const mcu_pin_obj_t pin_PE03 = PIN(4, 3, NO_ADC);
|
||||
const mcu_pin_obj_t pin_PE04 = PIN(4, 4, NO_ADC);
|
||||
const mcu_pin_obj_t pin_PE05 = PIN(4, 5, NO_ADC);
|
||||
const mcu_pin_obj_t pin_PE06 = PIN(4, 6, NO_ADC);
|
||||
|
||||
const mcu_pin_obj_t pin_PC13 = PIN(2, 13, NO_ADC); //anti-tamp
|
||||
const mcu_pin_obj_t pin_PC14 = PIN(2, 14, NO_ADC); //OSC32_IN
|
||||
const mcu_pin_obj_t pin_PC15 = PIN(2, 15, NO_ADC); //OSC32_OUT
|
||||
|
||||
const mcu_pin_obj_t pin_PF00 = PIN(5, 0, NO_ADC); // 144 only
|
||||
const mcu_pin_obj_t pin_PF01 = PIN(5, 1, NO_ADC); // 144 only
|
||||
const mcu_pin_obj_t pin_PF02 = PIN(5, 2, NO_ADC); // 144 only
|
||||
const mcu_pin_obj_t pin_PF03 = PIN(5, 3, ADC_INPUT(ADC_3,9)); // 144 only
|
||||
const mcu_pin_obj_t pin_PF04 = PIN(5, 4, ADC_INPUT(ADC_3,14)); // 144 only
|
||||
const mcu_pin_obj_t pin_PF05 = PIN(5, 5, ADC_INPUT(ADC_3,15)); // 144 only
|
||||
const mcu_pin_obj_t pin_PF06 = PIN(5, 6, ADC_INPUT(ADC_3,4)); // 144 only
|
||||
const mcu_pin_obj_t pin_PF07 = PIN(5, 7, ADC_INPUT(ADC_3,5)); // 144 only
|
||||
const mcu_pin_obj_t pin_PF08 = PIN(5, 8, ADC_INPUT(ADC_3,6)); // 144 only
|
||||
const mcu_pin_obj_t pin_PF09 = PIN(5, 9, ADC_INPUT(ADC_3,7)); // 144 only
|
||||
const mcu_pin_obj_t pin_PF10 = PIN(5, 10, ADC_INPUT(ADC_3,8)); // 144 only
|
||||
|
||||
const mcu_pin_obj_t pin_PC00 = PIN(2, 0, ADC_INPUT(ADC_123,10));
|
||||
const mcu_pin_obj_t pin_PC01 = PIN(2, 1, ADC_INPUT(ADC_123,11));
|
||||
const mcu_pin_obj_t pin_PC02 = PIN(2, 2, ADC_INPUT(ADC_123,12));
|
||||
const mcu_pin_obj_t pin_PC03 = PIN(2, 3, ADC_INPUT(ADC_123,13));
|
||||
|
||||
const mcu_pin_obj_t pin_PA00 = PIN(0, 0, ADC_INPUT(ADC_123,0));
|
||||
const mcu_pin_obj_t pin_PA01 = PIN(0, 1, ADC_INPUT(ADC_123,1));
|
||||
const mcu_pin_obj_t pin_PA02 = PIN(0, 2, ADC_INPUT(ADC_123,2));
|
||||
const mcu_pin_obj_t pin_PA03 = PIN(0, 3, ADC_INPUT(ADC_123,3));
|
||||
const mcu_pin_obj_t pin_PA04 = PIN(0, 4, ADC_INPUT(ADC_12,4));
|
||||
const mcu_pin_obj_t pin_PA05 = PIN(0, 5, ADC_INPUT(ADC_12,5));
|
||||
const mcu_pin_obj_t pin_PA06 = PIN(0, 6, ADC_INPUT(ADC_12,6));
|
||||
const mcu_pin_obj_t pin_PA07 = PIN(0, 7, ADC_INPUT(ADC_12,7));
|
||||
|
||||
const mcu_pin_obj_t pin_PC04 = PIN(2, 4, ADC_INPUT(ADC_12,14));
|
||||
const mcu_pin_obj_t pin_PC05 = PIN(2, 5, ADC_INPUT(ADC_12,15));
|
||||
|
||||
const mcu_pin_obj_t pin_PB00 = PIN(1, 0, ADC_INPUT(ADC_12,8));
|
||||
const mcu_pin_obj_t pin_PB01 = PIN(1, 1, ADC_INPUT(ADC_12,9));
|
||||
const mcu_pin_obj_t pin_PB02 = PIN(1, 2, NO_ADC); //BOOT1
|
||||
|
||||
const mcu_pin_obj_t pin_PF11 = PIN(5, 11, NO_ADC); // 144 only
|
||||
const mcu_pin_obj_t pin_PF12 = PIN(5, 12, NO_ADC); // 144 only
|
||||
const mcu_pin_obj_t pin_PF13 = PIN(5, 13, NO_ADC); // 144 only
|
||||
const mcu_pin_obj_t pin_PF14 = PIN(5, 14, NO_ADC); // 144 only
|
||||
const mcu_pin_obj_t pin_PF15 = PIN(5, 15, NO_ADC); // 144 only
|
||||
|
||||
const mcu_pin_obj_t pin_PG00 = PIN(6, 0, NO_ADC); // 144 only
|
||||
const mcu_pin_obj_t pin_PG01 = PIN(6, 1, NO_ADC); // 144 only
|
||||
|
||||
const mcu_pin_obj_t pin_PE07 = PIN(4, 7, NO_ADC);
|
||||
const mcu_pin_obj_t pin_PE08 = PIN(4, 8, NO_ADC);
|
||||
const mcu_pin_obj_t pin_PE09 = PIN(4, 9, NO_ADC);
|
||||
const mcu_pin_obj_t pin_PE10 = PIN(4, 10, NO_ADC);
|
||||
const mcu_pin_obj_t pin_PE11 = PIN(4, 11, NO_ADC);
|
||||
const mcu_pin_obj_t pin_PE12 = PIN(4, 12, NO_ADC);
|
||||
const mcu_pin_obj_t pin_PE13 = PIN(4, 13, NO_ADC);
|
||||
const mcu_pin_obj_t pin_PE14 = PIN(4, 14, NO_ADC);
|
||||
const mcu_pin_obj_t pin_PE15 = PIN(4, 15, NO_ADC);
|
||||
|
||||
const mcu_pin_obj_t pin_PB10 = PIN(1, 10, NO_ADC);
|
||||
const mcu_pin_obj_t pin_PB11 = PIN(1, 11, NO_ADC);
|
||||
const mcu_pin_obj_t pin_PB12 = PIN(1, 12, NO_ADC);
|
||||
const mcu_pin_obj_t pin_PB13 = PIN(1, 13, NO_ADC);
|
||||
const mcu_pin_obj_t pin_PB14 = PIN(1, 14, NO_ADC);
|
||||
const mcu_pin_obj_t pin_PB15 = PIN(1, 15, NO_ADC);
|
||||
|
||||
const mcu_pin_obj_t pin_PD08 = PIN(3, 8, NO_ADC);
|
||||
const mcu_pin_obj_t pin_PD09 = PIN(3, 9, NO_ADC);
|
||||
const mcu_pin_obj_t pin_PD10 = PIN(3, 10, NO_ADC);
|
||||
const mcu_pin_obj_t pin_PD11 = PIN(3, 11, NO_ADC);
|
||||
const mcu_pin_obj_t pin_PD12 = PIN(3, 12, NO_ADC);
|
||||
const mcu_pin_obj_t pin_PD13 = PIN(3, 13, NO_ADC);
|
||||
const mcu_pin_obj_t pin_PD14 = PIN(3, 14, NO_ADC);
|
||||
const mcu_pin_obj_t pin_PD15 = PIN(3, 15, NO_ADC);
|
||||
|
||||
const mcu_pin_obj_t pin_PG02 = PIN(6, 2, NO_ADC); // 144 only
|
||||
const mcu_pin_obj_t pin_PG03 = PIN(6, 3, NO_ADC); // 144 only
|
||||
const mcu_pin_obj_t pin_PG04 = PIN(6, 4, NO_ADC); // 144 only
|
||||
const mcu_pin_obj_t pin_PG05 = PIN(6, 5, NO_ADC); // 144 only
|
||||
const mcu_pin_obj_t pin_PG06 = PIN(6, 6, NO_ADC); // 144 only
|
||||
const mcu_pin_obj_t pin_PG07 = PIN(6, 7, NO_ADC); // 144 only
|
||||
const mcu_pin_obj_t pin_PG08 = PIN(6, 8, NO_ADC); // 144 only
|
||||
|
||||
const mcu_pin_obj_t pin_PC06 = PIN(2, 6, NO_ADC);
|
||||
const mcu_pin_obj_t pin_PC07 = PIN(2, 7, NO_ADC);
|
||||
const mcu_pin_obj_t pin_PC08 = PIN(2, 8, NO_ADC);
|
||||
const mcu_pin_obj_t pin_PC09 = PIN(2, 9, NO_ADC);
|
||||
|
||||
const mcu_pin_obj_t pin_PA08 = PIN(0, 8, NO_ADC);
|
||||
const mcu_pin_obj_t pin_PA09 = PIN(0, 9, NO_ADC);
|
||||
const mcu_pin_obj_t pin_PA10 = PIN(0, 10, NO_ADC);
|
||||
const mcu_pin_obj_t pin_PA11 = PIN(0, 11, NO_ADC);
|
||||
const mcu_pin_obj_t pin_PA12 = PIN(0, 12, NO_ADC);
|
||||
const mcu_pin_obj_t pin_PA13 = PIN(0, 13, NO_ADC);
|
||||
const mcu_pin_obj_t pin_PA14 = PIN(0, 14, NO_ADC);
|
||||
const mcu_pin_obj_t pin_PA15 = PIN(0, 15, NO_ADC);
|
||||
|
||||
const mcu_pin_obj_t pin_PC10 = PIN(2, 10, NO_ADC);
|
||||
const mcu_pin_obj_t pin_PC11 = PIN(2, 11, NO_ADC);
|
||||
const mcu_pin_obj_t pin_PC12 = PIN(2, 12, NO_ADC);
|
||||
|
||||
const mcu_pin_obj_t pin_PD00 = PIN(3, 0, NO_ADC);
|
||||
const mcu_pin_obj_t pin_PD01 = PIN(3, 1, NO_ADC);
|
||||
const mcu_pin_obj_t pin_PD02 = PIN(3, 2, NO_ADC);
|
||||
const mcu_pin_obj_t pin_PD03 = PIN(3, 3, NO_ADC);
|
||||
const mcu_pin_obj_t pin_PD04 = PIN(3, 4, NO_ADC);
|
||||
const mcu_pin_obj_t pin_PD05 = PIN(3, 5, NO_ADC);
|
||||
const mcu_pin_obj_t pin_PD06 = PIN(3, 6, NO_ADC);
|
||||
const mcu_pin_obj_t pin_PD07 = PIN(3, 7, NO_ADC);
|
||||
|
||||
const mcu_pin_obj_t pin_PG09 = PIN(6, 9, NO_ADC); // 144 only
|
||||
const mcu_pin_obj_t pin_PG10 = PIN(6, 10, NO_ADC); // 144 only
|
||||
const mcu_pin_obj_t pin_PG11 = PIN(6, 11, NO_ADC); // 144 only
|
||||
const mcu_pin_obj_t pin_PG12 = PIN(6, 12, NO_ADC); // 144 only
|
||||
const mcu_pin_obj_t pin_PG13 = PIN(6, 13, NO_ADC); // 144 only
|
||||
const mcu_pin_obj_t pin_PG14 = PIN(6, 14, NO_ADC); // 144 only
|
||||
const mcu_pin_obj_t pin_PG15 = PIN(6, 15, NO_ADC); // 144 only
|
||||
|
||||
const mcu_pin_obj_t pin_PB03 = PIN(1, 3, NO_ADC);
|
||||
const mcu_pin_obj_t pin_PB04 = PIN(1, 4, NO_ADC);
|
||||
const mcu_pin_obj_t pin_PB05 = PIN(1, 5, NO_ADC);
|
||||
const mcu_pin_obj_t pin_PB06 = PIN(1, 6, NO_ADC);
|
||||
const mcu_pin_obj_t pin_PB07 = PIN(1, 7, NO_ADC);
|
||||
const mcu_pin_obj_t pin_PB08 = PIN(1, 8, NO_ADC);
|
||||
const mcu_pin_obj_t pin_PB09 = PIN(1, 9, NO_ADC);
|
||||
|
||||
const mcu_pin_obj_t pin_PE00 = PIN(4, 0, NO_ADC);
|
||||
const mcu_pin_obj_t pin_PE01 = PIN(4, 1, NO_ADC);
|
||||
158
ports/stm32f4/peripherals/stm32f4/stm32f407xx/pins.h
Normal file
158
ports/stm32f4/peripherals/stm32f4/stm32f407xx/pins.h
Normal file
@ -0,0 +1,158 @@
|
||||
/*
|
||||
* This file is part of the MicroPython project, http://micropython.org/
|
||||
*
|
||||
* The MIT License (MIT)
|
||||
*
|
||||
* Copyright (c) 2019 Lucian Copeland for Adafruit Industries
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef MICROPY_INCLUDED_STM32F4_PERIPHERALS_STM32F412ZG_PINS_H
|
||||
#define MICROPY_INCLUDED_STM32F4_PERIPHERALS_STM32F412ZG_PINS_H
|
||||
|
||||
//Pins in datasheet order: DocID028087 Rev 7 page 50. LQFP100 only
|
||||
//pg 50
|
||||
extern const mcu_pin_obj_t pin_PE02;
|
||||
extern const mcu_pin_obj_t pin_PE03;
|
||||
extern const mcu_pin_obj_t pin_PE04;
|
||||
extern const mcu_pin_obj_t pin_PE05;
|
||||
extern const mcu_pin_obj_t pin_PE06;
|
||||
extern const mcu_pin_obj_t pin_PC13;
|
||||
extern const mcu_pin_obj_t pin_PC14;
|
||||
//pg 51
|
||||
extern const mcu_pin_obj_t pin_PC15;
|
||||
extern const mcu_pin_obj_t pin_PF00; // 144 only
|
||||
extern const mcu_pin_obj_t pin_PF01; // 144 only
|
||||
extern const mcu_pin_obj_t pin_PF02; // 144 only
|
||||
extern const mcu_pin_obj_t pin_PF03; // 144 only
|
||||
extern const mcu_pin_obj_t pin_PF04; // 144 only
|
||||
extern const mcu_pin_obj_t pin_PF05; // 144 only
|
||||
extern const mcu_pin_obj_t pin_PF06; // 144 only
|
||||
extern const mcu_pin_obj_t pin_PF07; // 144 only
|
||||
extern const mcu_pin_obj_t pin_PF08; // 144 only
|
||||
extern const mcu_pin_obj_t pin_PF09; // 144 only
|
||||
extern const mcu_pin_obj_t pin_PF10; // 144 only
|
||||
//pg 52
|
||||
extern const mcu_pin_obj_t pin_PC00;
|
||||
extern const mcu_pin_obj_t pin_PC01;
|
||||
extern const mcu_pin_obj_t pin_PC02;
|
||||
extern const mcu_pin_obj_t pin_PC03;
|
||||
extern const mcu_pin_obj_t pin_PA00;
|
||||
extern const mcu_pin_obj_t pin_PA01;
|
||||
extern const mcu_pin_obj_t pin_PA02;
|
||||
//pg 53
|
||||
extern const mcu_pin_obj_t pin_PA03;
|
||||
extern const mcu_pin_obj_t pin_PA04;
|
||||
extern const mcu_pin_obj_t pin_PA05;
|
||||
extern const mcu_pin_obj_t pin_PA06;
|
||||
extern const mcu_pin_obj_t pin_PA07;
|
||||
extern const mcu_pin_obj_t pin_PC04;
|
||||
//pg 54
|
||||
extern const mcu_pin_obj_t pin_PC05;
|
||||
extern const mcu_pin_obj_t pin_PB00;
|
||||
extern const mcu_pin_obj_t pin_PB01;
|
||||
extern const mcu_pin_obj_t pin_PB02;
|
||||
extern const mcu_pin_obj_t pin_PF11; // 144 only
|
||||
extern const mcu_pin_obj_t pin_PF12; // 144 only
|
||||
extern const mcu_pin_obj_t pin_PF13; // 144 only
|
||||
extern const mcu_pin_obj_t pin_PF14; // 144 only
|
||||
extern const mcu_pin_obj_t pin_PF15; // 144 only
|
||||
extern const mcu_pin_obj_t pin_PG00; // 144 only
|
||||
extern const mcu_pin_obj_t pin_PG01; // 144 only
|
||||
//pg 55
|
||||
extern const mcu_pin_obj_t pin_PE07;
|
||||
extern const mcu_pin_obj_t pin_PE08;
|
||||
extern const mcu_pin_obj_t pin_PE09;
|
||||
extern const mcu_pin_obj_t pin_PE10;
|
||||
extern const mcu_pin_obj_t pin_PE11;
|
||||
extern const mcu_pin_obj_t pin_PE12;
|
||||
extern const mcu_pin_obj_t pin_PE13;
|
||||
extern const mcu_pin_obj_t pin_PE14;
|
||||
//pg 56
|
||||
extern const mcu_pin_obj_t pin_PE15;
|
||||
extern const mcu_pin_obj_t pin_PB10;
|
||||
extern const mcu_pin_obj_t pin_PB11; // 144 only
|
||||
extern const mcu_pin_obj_t pin_PB12;
|
||||
extern const mcu_pin_obj_t pin_PB13;
|
||||
//pg 57
|
||||
extern const mcu_pin_obj_t pin_PB14;
|
||||
extern const mcu_pin_obj_t pin_PB15;
|
||||
extern const mcu_pin_obj_t pin_PD08;
|
||||
extern const mcu_pin_obj_t pin_PD09;
|
||||
extern const mcu_pin_obj_t pin_PD10;
|
||||
extern const mcu_pin_obj_t pin_PD11;
|
||||
extern const mcu_pin_obj_t pin_PD12;
|
||||
//pg 58
|
||||
extern const mcu_pin_obj_t pin_PD13;
|
||||
extern const mcu_pin_obj_t pin_PD14;
|
||||
extern const mcu_pin_obj_t pin_PD15;
|
||||
extern const mcu_pin_obj_t pin_PG02; // 144 only
|
||||
extern const mcu_pin_obj_t pin_PG03; // 144 only
|
||||
extern const mcu_pin_obj_t pin_PG04; // 144 only
|
||||
extern const mcu_pin_obj_t pin_PG05; // 144 only
|
||||
extern const mcu_pin_obj_t pin_PG06; // 144 only
|
||||
extern const mcu_pin_obj_t pin_PG07; // 144 only
|
||||
extern const mcu_pin_obj_t pin_PG08; // 144 only
|
||||
//pg 59
|
||||
extern const mcu_pin_obj_t pin_PC06;
|
||||
extern const mcu_pin_obj_t pin_PC07;
|
||||
extern const mcu_pin_obj_t pin_PC08;
|
||||
extern const mcu_pin_obj_t pin_PC09;
|
||||
extern const mcu_pin_obj_t pin_PA08;
|
||||
extern const mcu_pin_obj_t pin_PA09;
|
||||
extern const mcu_pin_obj_t pin_PA10;
|
||||
//pg 60
|
||||
extern const mcu_pin_obj_t pin_PA11;
|
||||
extern const mcu_pin_obj_t pin_PA12;
|
||||
extern const mcu_pin_obj_t pin_PA13;
|
||||
extern const mcu_pin_obj_t pin_PA14;
|
||||
extern const mcu_pin_obj_t pin_PA15;
|
||||
extern const mcu_pin_obj_t pin_PC10;
|
||||
extern const mcu_pin_obj_t pin_PC11;
|
||||
//pg 61
|
||||
extern const mcu_pin_obj_t pin_PC12;
|
||||
extern const mcu_pin_obj_t pin_PD00;
|
||||
extern const mcu_pin_obj_t pin_PD01;
|
||||
extern const mcu_pin_obj_t pin_PD02;
|
||||
extern const mcu_pin_obj_t pin_PD03;
|
||||
extern const mcu_pin_obj_t pin_PD04;
|
||||
extern const mcu_pin_obj_t pin_PD05;
|
||||
extern const mcu_pin_obj_t pin_PD06;
|
||||
extern const mcu_pin_obj_t pin_PD07;
|
||||
//pg 62
|
||||
extern const mcu_pin_obj_t pin_PG09; // 144 only
|
||||
extern const mcu_pin_obj_t pin_PG10; // 144 only
|
||||
extern const mcu_pin_obj_t pin_PG11; // 144 only
|
||||
extern const mcu_pin_obj_t pin_PG12; // 144 only
|
||||
extern const mcu_pin_obj_t pin_PG13; // 144 only
|
||||
extern const mcu_pin_obj_t pin_PG14; // 144 only
|
||||
extern const mcu_pin_obj_t pin_PG15; // 144 only
|
||||
extern const mcu_pin_obj_t pin_PB03;
|
||||
extern const mcu_pin_obj_t pin_PB04;
|
||||
//pg 63
|
||||
extern const mcu_pin_obj_t pin_PB05;
|
||||
extern const mcu_pin_obj_t pin_PB06;
|
||||
extern const mcu_pin_obj_t pin_PB07;
|
||||
extern const mcu_pin_obj_t pin_PB08;
|
||||
extern const mcu_pin_obj_t pin_PB09;
|
||||
extern const mcu_pin_obj_t pin_PE00;
|
||||
extern const mcu_pin_obj_t pin_PE01;
|
||||
|
||||
#endif // MICROPY_INCLUDED_STM32F4_PERIPHERALS_STM32F412ZG_PINS_H
|
||||
@ -25,6 +25,7 @@
|
||||
* THE SOFTWARE.
|
||||
*/
|
||||
#include "stm32f4xx_hal.h"
|
||||
#include "py/mpconfig.h"
|
||||
|
||||
void stm32f4_peripherals_clocks_init(void) {
|
||||
//System clock init
|
||||
@ -46,7 +47,7 @@ void stm32f4_peripherals_clocks_init(void) {
|
||||
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
||||
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
|
||||
RCC_OscInitStruct.PLL.PLLM = 8;
|
||||
RCC_OscInitStruct.PLL.PLLM = BOARD_OSC_DIV;
|
||||
RCC_OscInitStruct.PLL.PLLN = 200;
|
||||
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
|
||||
RCC_OscInitStruct.PLL.PLLQ = 7;
|
||||
|
||||
@ -52,6 +52,11 @@
|
||||
#define INTERNAL_FLASH_FILESYSTEM_SIZE 0xC000 //48KiB
|
||||
#endif
|
||||
|
||||
#ifdef STM32F407xx
|
||||
#define STM32_FLASH_SIZE 0x100000 //1MB
|
||||
#define INTERNAL_FLASH_FILESYSTEM_SIZE 0xC000 //48KiB
|
||||
#endif
|
||||
|
||||
#define STM32_FLASH_OFFSET 0x8000000 //All STM32 chips map to this flash location
|
||||
|
||||
#define INTERNAL_FLASH_FILESYSTEM_START_ADDR 0x08004000
|
||||
|
||||
@ -57,6 +57,13 @@
|
||||
//|
|
||||
//| Construct an SPI object on the given pins.
|
||||
//|
|
||||
//| ..note:: The SPI peripherals allocated in order of desirability, if possible,
|
||||
//| such as highest speed and not shared use first. For instance, on the nRF52840,
|
||||
//| there is a single 32MHz SPI peripheral, and multiple 8MHz peripherals,
|
||||
//| some of which may also be used for I2C. The 32MHz SPI peripheral is returned
|
||||
//| first, then the exclusive 8MHz SPI peripheral, and finally the shared 8MHz
|
||||
//| peripherals.
|
||||
//|
|
||||
//| .. seealso:: Using this class directly requires careful lock management.
|
||||
//| Instead, use :class:`~adafruit_bus_device.spi_device.SPIDevice` to
|
||||
//| manage locks.
|
||||
|
||||
Loading…
Reference in New Issue
Block a user