atmel-samd/clocks: Split out samd21_clocks.c and samd51_clocks.c

Enhance readability by separating the samd21 and samd51 clock code.

This patch should not introduce any functional changes.

ports/atmel-samd/Makefile

@@ -225,6 +225,7 @@ SRC_C = \
 	audio_dma.c \
 	background.c \
 	clocks.c \
+	$(CHIP_FAMILY)_clocks.c \
 	events.c \
 	fatfs_port.c \
 	flash_api.c \

ports/atmel-samd/clocks.c

@@ -56,77 +56,6 @@ uint8_t find_free_gclk(uint16_t divisor) {
     return 0xff;
 }
 
-bool gclk_enabled(uint8_t gclk) {
-    #ifdef SAMD51
-    return GCLK->GENCTRL[gclk].bit.GENEN;
-    #endif
-    #ifdef SAMD21
-    common_hal_mcu_disable_interrupts();
-    // Explicitly do a byte write so the peripheral knows we're just wanting to read the channel
-    // rather than write to it.
-    *((uint8_t*) &GCLK->GENCTRL.reg) = gclk;
-    while (GCLK->STATUS.bit.SYNCBUSY == 1) {}
-    bool enabled = GCLK->GENCTRL.bit.GENEN;
-    common_hal_mcu_enable_interrupts();
-    return enabled;
-    #endif
-}
-
-void disable_gclk(uint8_t gclk) {
-    #ifdef SAMD51
-    while ((GCLK->SYNCBUSY.vec.GENCTRL & (1 << gclk)) != 0) {}
-    GCLK->GENCTRL[gclk].bit.GENEN = false;
-    while ((GCLK->SYNCBUSY.vec.GENCTRL & (1 << gclk)) != 0) {}
-    #endif
-    #ifdef SAMD21
-    while (GCLK->STATUS.bit.SYNCBUSY == 1) {}
-    GCLK->GENCTRL.reg = GCLK_GENCTRL_ID(gclk);
-    while (GCLK->STATUS.bit.SYNCBUSY == 1) {}
-    #endif
-}
-
-void connect_gclk_to_peripheral(uint8_t gclk, uint8_t peripheral) {
-    #ifdef SAMD21
-    GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID(peripheral) | GCLK_CLKCTRL_GEN(gclk) | GCLK_CLKCTRL_CLKEN;
-    #endif
-    #ifdef SAMD51
-    GCLK->PCHCTRL[peripheral].reg = GCLK_PCHCTRL_CHEN | GCLK_PCHCTRL_GEN(gclk);
-    while(GCLK->SYNCBUSY.reg != 0) {}
-    #endif
-}
-
-void disconnect_gclk_from_peripheral(uint8_t gclk, uint8_t peripheral) {
-    #ifdef SAMD21
-    GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID(peripheral) | GCLK_CLKCTRL_GEN(gclk);
-    #endif
-    #ifdef SAMD51
-    GCLK->PCHCTRL[peripheral].reg = 0;
-    #endif
-}
-
-void enable_clock_generator(uint8_t gclk, uint8_t source, uint16_t divisor) {
-    #ifdef SAMD21
-    GCLK->GENDIV.reg = GCLK_GENDIV_ID(gclk) | GCLK_GENDIV_DIV(divisor);
-    GCLK->GENCTRL.reg = GCLK_GENCTRL_ID(gclk) | GCLK_GENCTRL_SRC(source) | GCLK_GENCTRL_GENEN;
-    while (GCLK->STATUS.bit.SYNCBUSY != 0) {}
-    #endif
-    #ifdef SAMD51
-    GCLK->GENCTRL[gclk].reg = GCLK_GENCTRL_SRC(source) | GCLK_GENCTRL_DIV(divisor) | GCLK_GENCTRL_GENEN;
-    while ((GCLK->SYNCBUSY.vec.GENCTRL & (1 << gclk)) != 0) {}
-    #endif
-}
-
-void disable_clock_generator(uint8_t gclk) {
-    #ifdef SAMD21
-    GCLK->GENCTRL.reg = GCLK_GENCTRL_ID(gclk);
-    while (GCLK->STATUS.bit.SYNCBUSY != 0) {}
-    #endif
-    #ifdef SAMD51
-    GCLK->GENCTRL[gclk].reg = 0;
-    while ((GCLK->SYNCBUSY.vec.GENCTRL & (1 << gclk)) != 0) {}
-    #endif
-}
-
 void reset_gclks(void) {
     // Never reset GCLK0 because its used for the core
     #if CONF_GCLK_GEN_1_GENEN == 0

ports/atmel-samd/clocks.h

@@ -44,6 +44,7 @@
 uint8_t find_free_gclk(uint16_t divisor);
 
 bool gclk_enabled(uint8_t gclk);
+void disable_gclk(uint8_t gclk);
 void reset_gclks(void);
 
 void connect_gclk_to_peripheral(uint8_t gclk, uint8_t peripheral);

ports/atmel-samd/samd21_clocks.c

@@ -0,0 +1,69 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2018 Scott Shawcroft for Adafruit Industries
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "clocks.h"
+
+#include "hpl_gclk_config.h"
+
+#include "shared-bindings/microcontroller/__init__.h"
+
+#include "py/runtime.h"
+
+bool gclk_enabled(uint8_t gclk) {
+    common_hal_mcu_disable_interrupts();
+    // Explicitly do a byte write so the peripheral knows we're just wanting to read the channel
+    // rather than write to it.
+    *((uint8_t*) &GCLK->GENCTRL.reg) = gclk;
+    while (GCLK->STATUS.bit.SYNCBUSY == 1) {}
+    bool enabled = GCLK->GENCTRL.bit.GENEN;
+    common_hal_mcu_enable_interrupts();
+    return enabled;
+}
+
+void disable_gclk(uint8_t gclk) {
+    while (GCLK->STATUS.bit.SYNCBUSY == 1) {}
+    GCLK->GENCTRL.reg = GCLK_GENCTRL_ID(gclk);
+    while (GCLK->STATUS.bit.SYNCBUSY == 1) {}
+}
+
+void connect_gclk_to_peripheral(uint8_t gclk, uint8_t peripheral) {
+    GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID(peripheral) | GCLK_CLKCTRL_GEN(gclk) | GCLK_CLKCTRL_CLKEN;
+}
+
+void disconnect_gclk_from_peripheral(uint8_t gclk, uint8_t peripheral) {
+    GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID(peripheral) | GCLK_CLKCTRL_GEN(gclk);
+}
+
+void enable_clock_generator(uint8_t gclk, uint8_t source, uint16_t divisor) {
+    GCLK->GENDIV.reg = GCLK_GENDIV_ID(gclk) | GCLK_GENDIV_DIV(divisor);
+    GCLK->GENCTRL.reg = GCLK_GENCTRL_ID(gclk) | GCLK_GENCTRL_SRC(source) | GCLK_GENCTRL_GENEN;
+    while (GCLK->STATUS.bit.SYNCBUSY != 0) {}
+}
+
+void disable_clock_generator(uint8_t gclk) {
+    GCLK->GENCTRL.reg = GCLK_GENCTRL_ID(gclk);
+    while (GCLK->STATUS.bit.SYNCBUSY != 0) {}
+}

ports/atmel-samd/samd51_clocks.c

@@ -0,0 +1,62 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2018 Scott Shawcroft for Adafruit Industries
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "clocks.h"
+
+#include "hpl_gclk_config.h"
+
+#include "shared-bindings/microcontroller/__init__.h"
+
+#include "py/runtime.h"
+
+bool gclk_enabled(uint8_t gclk) {
+    return GCLK->GENCTRL[gclk].bit.GENEN;
+}
+
+void disable_gclk(uint8_t gclk) {
+    while ((GCLK->SYNCBUSY.vec.GENCTRL & (1 << gclk)) != 0) {}
+    GCLK->GENCTRL[gclk].bit.GENEN = false;
+    while ((GCLK->SYNCBUSY.vec.GENCTRL & (1 << gclk)) != 0) {}
+}
+
+void connect_gclk_to_peripheral(uint8_t gclk, uint8_t peripheral) {
+    GCLK->PCHCTRL[peripheral].reg = GCLK_PCHCTRL_CHEN | GCLK_PCHCTRL_GEN(gclk);
+    while(GCLK->SYNCBUSY.reg != 0) {}
+}
+
+void disconnect_gclk_from_peripheral(uint8_t gclk, uint8_t peripheral) {
+    GCLK->PCHCTRL[peripheral].reg = 0;
+}
+
+void enable_clock_generator(uint8_t gclk, uint8_t source, uint16_t divisor) {
+    GCLK->GENCTRL[gclk].reg = GCLK_GENCTRL_SRC(source) | GCLK_GENCTRL_DIV(divisor) | GCLK_GENCTRL_GENEN;
+    while ((GCLK->SYNCBUSY.vec.GENCTRL & (1 << gclk)) != 0) {}
+}
+
+void disable_clock_generator(uint8_t gclk) {
+    GCLK->GENCTRL[gclk].reg = 0;
+    while ((GCLK->SYNCBUSY.vec.GENCTRL & (1 << gclk)) != 0) {}
+}