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Merge pull request #2866 from hierophect/stm32-lsetimeout

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STM32: Fix LSE hang at startup
This commit is contained in:
Scott Shawcroft 2020-05-11 16:23:09 -07:00 committed by GitHub
commit 4937d5f1ca
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14 changed files with 73 additions and 27 deletions
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2
ports/stm/boards/STM32F401xd_fs.ld
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@ -13,7 +13,7 @@ MEMORY
} }
/* produce a link error if there is not this amount of RAM for these sections */ /* produce a link error if there is not this amount of RAM for these sections */
_minimum_stack_size = 2K; _minimum_stack_size = 24K;
_minimum_heap_size = 16K; _minimum_heap_size = 16K;
/* Define tho top end of the stack. The stack is full descending so begins just /* Define tho top end of the stack. The stack is full descending so begins just

2
ports/stm/boards/STM32F401xe_boot.ld
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@ -12,7 +12,7 @@ MEMORY
} }
/* produce a link error if there is not this amount of RAM for these sections */ /* produce a link error if there is not this amount of RAM for these sections */
_minimum_stack_size = 2K; _minimum_stack_size = 24K;
_minimum_heap_size = 16K; _minimum_heap_size = 16K;
/* Define tho top end of the stack. The stack is full descending so begins just /* Define tho top end of the stack. The stack is full descending so begins just

2
ports/stm/boards/STM32F401xe_fs.ld
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@ -13,7 +13,7 @@ MEMORY
} }
/* produce a link error if there is not this amount of RAM for these sections */ /* produce a link error if there is not this amount of RAM for these sections */
_minimum_stack_size = 2K; _minimum_stack_size = 24K;
_minimum_heap_size = 16K; _minimum_heap_size = 16K;
/* Define tho top end of the stack. The stack is full descending so begins just /* Define tho top end of the stack. The stack is full descending so begins just

2
ports/stm/boards/STM32F405_boot.ld
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@ -13,7 +13,7 @@ MEMORY
} }
/* produce a link error if there is not this amount of RAM for these sections */ /* produce a link error if there is not this amount of RAM for these sections */
_minimum_stack_size = 2K; _minimum_stack_size = 24K;
_minimum_heap_size = 16K; _minimum_heap_size = 16K;
/* Define the top end of the stack. The stack is full descending so begins just /* Define the top end of the stack. The stack is full descending so begins just

2
ports/stm/boards/STM32F405_default.ld
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@ -13,7 +13,7 @@ MEMORY
} }
/* produce a link error if there is not this amount of RAM for these sections */ /* produce a link error if there is not this amount of RAM for these sections */
_minimum_stack_size = 2K; _minimum_stack_size = 24K;
_minimum_heap_size = 16K; _minimum_heap_size = 16K;
/* Define tho top end of the stack. The stack is full descending so begins just /* Define tho top end of the stack. The stack is full descending so begins just

2
ports/stm/boards/STM32F405_fs.ld
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@ -14,7 +14,7 @@ MEMORY
} }
/* produce a link error if there is not this amount of RAM for these sections */ /* produce a link error if there is not this amount of RAM for these sections */
_minimum_stack_size = 2K; _minimum_stack_size = 24K;
_minimum_heap_size = 16K; _minimum_heap_size = 16K;
/* Define tho top end of the stack. The stack is full descending so begins just /* Define tho top end of the stack. The stack is full descending so begins just

2
ports/stm/boards/STM32F407_fs.ld
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@ -14,7 +14,7 @@ MEMORY
} }
/* produce a link error if there is not this amount of RAM for these sections */ /* produce a link error if there is not this amount of RAM for these sections */
_minimum_stack_size = 2K; _minimum_stack_size = 24K;
_minimum_heap_size = 16K; _minimum_heap_size = 16K;
/* Define tho top end of the stack. The stack is full descending so begins just /* Define tho top end of the stack. The stack is full descending so begins just

2
ports/stm/boards/STM32F411_fs.ld
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@ -13,7 +13,7 @@ MEMORY
} }
/* produce a link error if there is not this amount of RAM for these sections */ /* produce a link error if there is not this amount of RAM for these sections */
_minimum_stack_size = 2K; _minimum_stack_size = 24K;
_minimum_heap_size = 16K; _minimum_heap_size = 16K;
/* Define tho top end of the stack. The stack is full descending so begins just /* Define tho top end of the stack. The stack is full descending so begins just

2
ports/stm/boards/STM32F411_nvm.ld
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@ -14,7 +14,7 @@ MEMORY
} }
/* produce a link error if there is not this amount of RAM for these sections */ /* produce a link error if there is not this amount of RAM for these sections */
_minimum_stack_size = 2K; _minimum_stack_size = 24K;
_minimum_heap_size = 16K; _minimum_heap_size = 16K;
/* Define the top end of the stack. The stack is full descending so begins just /* Define the top end of the stack. The stack is full descending so begins just

2
ports/stm/boards/STM32F412_fs.ld
View File

@ -13,7 +13,7 @@ MEMORY
} }
/* produce a link error if there is not this amount of RAM for these sections */ /* produce a link error if there is not this amount of RAM for these sections */
_minimum_stack_size = 2K; _minimum_stack_size = 24K;
_minimum_heap_size = 16K; _minimum_heap_size = 16K;
/* Define tho top end of the stack. The stack is full descending so begins just /* Define tho top end of the stack. The stack is full descending so begins just

2
ports/stm/boards/STM32F746xG_fs.ld
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@ -38,7 +38,7 @@ MEMORY
} }
/* produce a link error if there is not this amount of RAM for these sections */ /* produce a link error if there is not this amount of RAM for these sections */
_minimum_stack_size = 2K; _minimum_stack_size = 24K;
_minimum_heap_size = 16K; _minimum_heap_size = 16K;
/* Define tho top end of the stack. The stack is full descending so begins just /* Define tho top end of the stack. The stack is full descending so begins just

2
ports/stm/boards/STM32F767_fs.ld
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@ -13,7 +13,7 @@ MEMORY
} }
/* produce a link error if there is not this amount of RAM for these sections */ /* produce a link error if there is not this amount of RAM for these sections */
_minimum_stack_size = 2K; _minimum_stack_size = 24K;
_minimum_heap_size = 16K; _minimum_heap_size = 16K;
/* Define tho top end of the stack. The stack is full descending so begins just /* Define tho top end of the stack. The stack is full descending so begins just

2
ports/stm/boards/STM32H743_fs.ld
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@ -22,7 +22,7 @@ MEMORY
} }
/* produce a link error if there is not this amount of RAM for these sections */ /* produce a link error if there is not this amount of RAM for these sections */
_minimum_stack_size = 2K; _minimum_stack_size = 24K; /*TODO: this can probably be bigger, but how big?*/
_minimum_heap_size = 16K; _minimum_heap_size = 16K;
/* brainless copy paste for stack code. Results in ambiguous hard crash */ /* brainless copy paste for stack code. Results in ambiguous hard crash */

74
ports/stm/supervisor/port.c
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@ -49,7 +49,7 @@
#include STM32_HAL_H #include STM32_HAL_H
//only enable the Reset Handler overwrite for the H7 for now //only enable the Reset Handler overwrite for the H7 for now
#if defined(STM32H7) #if (CPY_STM32H7)
// Device memories must be accessed in order. // Device memories must be accessed in order.
#define DEVICE 2 #define DEVICE 2
@ -153,16 +153,16 @@ __attribute__((used, naked)) void Reset_Handler(void) {
static RTC_HandleTypeDef _hrtc; static RTC_HandleTypeDef _hrtc;
#if BOARD_HAS_LOW_SPEED_CRYSTAL #if BOARD_HAS_LOW_SPEED_CRYSTAL
#define RTC_CLOCK_FREQUENCY LSE_VALUE static uint32_t rtc_clock_frequency = LSE_VALUE;
#else #else
#define RTC_CLOCK_FREQUENCY LSI_VALUE static uint32_t rtc_clock_frequency = LSI_VALUE;
#endif #endif
safe_mode_t port_init(void) { safe_mode_t port_init(void) {
HAL_Init(); HAL_Init();
__HAL_RCC_SYSCFG_CLK_ENABLE(); __HAL_RCC_SYSCFG_CLK_ENABLE();
#if defined(STM32F4) #if (CPY_STM32F4)
__HAL_RCC_PWR_CLK_ENABLE(); __HAL_RCC_PWR_CLK_ENABLE();
#endif #endif
@ -170,24 +170,70 @@ safe_mode_t port_init(void) {
stm32_peripherals_gpio_init(); stm32_peripherals_gpio_init();
HAL_PWR_EnableBkUpAccess(); HAL_PWR_EnableBkUpAccess();
// TODO: move all of this to clocks.c
#if BOARD_HAS_LOW_SPEED_CRYSTAL #if BOARD_HAS_LOW_SPEED_CRYSTAL
uint32_t tickstart = HAL_GetTick();
// H7/F7 untested with LSE, so autofail them until above move is done
#if (CPY_STM32F4)
bool lse_setupsuccess = true;
#else
bool lse_setupsuccess = false;
#endif
// Update LSE configuration in Backup Domain control register
// Requires to enable write access to Backup Domain of necessary
// TODO: should be using the HAL OSC initializer, otherwise we'll need
// preprocessor defines for every register to account for F7/H7
#if (CPY_STM32F4)
if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
{
// Enable write access to Backup domain
SET_BIT(PWR->CR, PWR_CR_DBP);
// Wait for Backup domain Write protection disable
tickstart = HAL_GetTick();
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
{
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
{
lse_setupsuccess = false;
}
}
}
#endif
__HAL_RCC_LSE_CONFIG(RCC_LSE_ON); __HAL_RCC_LSE_CONFIG(RCC_LSE_ON);
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) {} tickstart = HAL_GetTick();
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) {
if((HAL_GetTick() - tickstart ) > LSE_STARTUP_TIMEOUT)
{
lse_setupsuccess = false;
__HAL_RCC_LSE_CONFIG(RCC_LSE_OFF);
__HAL_RCC_LSI_ENABLE();
rtc_clock_frequency = LSI_VALUE;
break;
}
}
if (lse_setupsuccess) {
__HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSE);
} else {
__HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSI);
}
#else #else
__HAL_RCC_LSI_ENABLE(); __HAL_RCC_LSI_ENABLE();
#endif
#if BOARD_HAS_LOW_SPEED_CRYSTAL
__HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSE);
#else
__HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSI); __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSI);
#endif #endif
__HAL_RCC_RTC_ENABLE(); __HAL_RCC_RTC_ENABLE();
_hrtc.Instance = RTC; _hrtc.Instance = RTC;
_hrtc.Init.HourFormat = RTC_HOURFORMAT_24; _hrtc.Init.HourFormat = RTC_HOURFORMAT_24;
// Divide async as little as possible so that we have RTC_CLOCK_FREQUENCY count in subseconds. // Divide async as little as possible so that we have rtc_clock_frequency count in subseconds.
// This ensures our timing > 1 second is correct. // This ensures our timing > 1 second is correct.
_hrtc.Init.AsynchPrediv = 0x0; _hrtc.Init.AsynchPrediv = 0x0;
_hrtc.Init.SynchPrediv = RTC_CLOCK_FREQUENCY - 1; _hrtc.Init.SynchPrediv = rtc_clock_frequency - 1;
_hrtc.Init.OutPut = RTC_OUTPUT_DISABLE; _hrtc.Init.OutPut = RTC_OUTPUT_DISABLE;
HAL_RTC_Init(&_hrtc); HAL_RTC_Init(&_hrtc);
@ -293,7 +339,7 @@ volatile uint32_t cached_date = 0;
volatile uint32_t seconds_to_minute = 0; volatile uint32_t seconds_to_minute = 0;
volatile uint32_t cached_hours_minutes = 0; volatile uint32_t cached_hours_minutes = 0;
uint64_t port_get_raw_ticks(uint8_t* subticks) { uint64_t port_get_raw_ticks(uint8_t* subticks) {
uint32_t subseconds = RTC_CLOCK_FREQUENCY - (uint32_t)(RTC->SSR); uint32_t subseconds = rtc_clock_frequency - (uint32_t)(RTC->SSR);
uint32_t time = (uint32_t)(RTC->TR & RTC_TR_RESERVED_MASK); uint32_t time = (uint32_t)(RTC->TR & RTC_TR_RESERVED_MASK);
uint32_t date = (uint32_t)(RTC->DR & RTC_DR_RESERVED_MASK); uint32_t date = (uint32_t)(RTC->DR & RTC_DR_RESERVED_MASK);
if (date != cached_date) { if (date != cached_date) {
@ -341,7 +387,7 @@ void RTC_Alarm_IRQHandler(void) {
// Enable 1/1024 second tick. // Enable 1/1024 second tick.
void port_enable_tick(void) { void port_enable_tick(void) {
HAL_RTCEx_SetWakeUpTimer_IT(&_hrtc, RTC_CLOCK_FREQUENCY / 1024 / 2, RTC_WAKEUPCLOCK_RTCCLK_DIV2); HAL_RTCEx_SetWakeUpTimer_IT(&_hrtc, rtc_clock_frequency / 1024 / 2, RTC_WAKEUPCLOCK_RTCCLK_DIV2);
HAL_NVIC_SetPriority(RTC_WKUP_IRQn, 1, 0U); HAL_NVIC_SetPriority(RTC_WKUP_IRQn, 1, 0U);
HAL_NVIC_EnableIRQ(RTC_WKUP_IRQn); HAL_NVIC_EnableIRQ(RTC_WKUP_IRQn);
} }
@ -372,7 +418,7 @@ void port_interrupt_after_ticks(uint32_t ticks) {
alarm.AlarmMask = RTC_ALARMMASK_ALL; alarm.AlarmMask = RTC_ALARMMASK_ALL;
} }
alarm.AlarmTime.SubSeconds = RTC_CLOCK_FREQUENCY - alarm.AlarmTime.SubSeconds = rtc_clock_frequency -
((raw_ticks % 1024) * 32); ((raw_ticks % 1024) * 32);
alarm.AlarmTime.DayLightSaving = RTC_DAYLIGHTSAVING_NONE; alarm.AlarmTime.DayLightSaving = RTC_DAYLIGHTSAVING_NONE;
alarm.AlarmTime.StoreOperation = RTC_STOREOPERATION_SET; alarm.AlarmTime.StoreOperation = RTC_STOREOPERATION_SET;