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Add recovery domain write access, adjust stack

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This commit is contained in:
Lucian Copeland 2020-05-11 18:02:40 -04:00
parent 248704b262
commit 94949fb46f
14 changed files with 54 additions and 22 deletions
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2
ports/stm/boards/STM32F401xd_fs.ld
View File

@ -13,7 +13,7 @@ MEMORY
}
/* produce a link error if there is not this amount of RAM for these sections */
_minimum_stack_size = 2K;
_minimum_stack_size = 24K;
_minimum_heap_size = 16K;
/* Define tho top end of the stack. The stack is full descending so begins just

2
ports/stm/boards/STM32F401xe_boot.ld
View File

@ -12,7 +12,7 @@ MEMORY
}
/* produce a link error if there is not this amount of RAM for these sections */
_minimum_stack_size = 2K;
_minimum_stack_size = 24K;
_minimum_heap_size = 16K;
/* Define tho top end of the stack. The stack is full descending so begins just

2
ports/stm/boards/STM32F401xe_fs.ld
View File

@ -13,7 +13,7 @@ MEMORY
}
/* produce a link error if there is not this amount of RAM for these sections */
_minimum_stack_size = 2K;
_minimum_stack_size = 24K;
_minimum_heap_size = 16K;
/* Define tho top end of the stack. The stack is full descending so begins just

2
ports/stm/boards/STM32F405_boot.ld
View File

@ -13,7 +13,7 @@ MEMORY
}
/* produce a link error if there is not this amount of RAM for these sections */
_minimum_stack_size = 2K;
_minimum_stack_size = 24K;
_minimum_heap_size = 16K;
/* Define the top end of the stack. The stack is full descending so begins just

2
ports/stm/boards/STM32F405_default.ld
View File

@ -13,7 +13,7 @@ MEMORY
}
/* produce a link error if there is not this amount of RAM for these sections */
_minimum_stack_size = 2K;
_minimum_stack_size = 24K;
_minimum_heap_size = 16K;
/* Define tho top end of the stack. The stack is full descending so begins just

2
ports/stm/boards/STM32F405_fs.ld
View File

@ -14,7 +14,7 @@ MEMORY
}
/* produce a link error if there is not this amount of RAM for these sections */
_minimum_stack_size = 2K;
_minimum_stack_size = 24K;
_minimum_heap_size = 16K;
/* Define tho top end of the stack. The stack is full descending so begins just

2
ports/stm/boards/STM32F407_fs.ld
View File

@ -14,7 +14,7 @@ MEMORY
}
/* produce a link error if there is not this amount of RAM for these sections */
_minimum_stack_size = 2K;
_minimum_stack_size = 24K;
_minimum_heap_size = 16K;
/* Define tho top end of the stack. The stack is full descending so begins just

2
ports/stm/boards/STM32F411_fs.ld
View File

@ -13,7 +13,7 @@ MEMORY
}
/* produce a link error if there is not this amount of RAM for these sections */
_minimum_stack_size = 2K;
_minimum_stack_size = 24K;
_minimum_heap_size = 16K;
/* Define tho top end of the stack. The stack is full descending so begins just

2
ports/stm/boards/STM32F411_nvm.ld
View File

@ -14,7 +14,7 @@ MEMORY
}
/* produce a link error if there is not this amount of RAM for these sections */
_minimum_stack_size = 2K;
_minimum_stack_size = 24K;
_minimum_heap_size = 16K;
/* Define the top end of the stack. The stack is full descending so begins just

2
ports/stm/boards/STM32F412_fs.ld
View File

@ -13,7 +13,7 @@ MEMORY
}
/* produce a link error if there is not this amount of RAM for these sections */
_minimum_stack_size = 2K;
_minimum_stack_size = 24K;
_minimum_heap_size = 16K;
/* Define tho top end of the stack. The stack is full descending so begins just

2
ports/stm/boards/STM32F746xG_fs.ld
View File

@ -38,7 +38,7 @@ MEMORY
}
/* produce a link error if there is not this amount of RAM for these sections */
_minimum_stack_size = 2K;
_minimum_stack_size = 24K;
_minimum_heap_size = 16K;
/* Define tho top end of the stack. The stack is full descending so begins just

2
ports/stm/boards/STM32F767_fs.ld
View File

@ -13,7 +13,7 @@ MEMORY
}
/* produce a link error if there is not this amount of RAM for these sections */
_minimum_stack_size = 2K;
_minimum_stack_size = 24K;
_minimum_heap_size = 16K;
/* Define tho top end of the stack. The stack is full descending so begins just

2
ports/stm/boards/STM32H743_fs.ld
View File

@ -22,7 +22,7 @@ MEMORY
}
/* produce a link error if there is not this amount of RAM for these sections */
_minimum_stack_size = 2K;
_minimum_stack_size = 24K; /*TODO: this can probably be bigger, but how big?*/
_minimum_heap_size = 16K;
/* brainless copy paste for stack code. Results in ambiguous hard crash */

50
ports/stm/supervisor/port.c
View File

@ -49,7 +49,7 @@
#include STM32_HAL_H
//only enable the Reset Handler overwrite for the H7 for now
#if defined(STM32H7)
#if (CPY_STM32H7)
// Device memories must be accessed in order.
#define DEVICE 2
@ -162,7 +162,7 @@ safe_mode_t port_init(void) {
HAL_Init();
__HAL_RCC_SYSCFG_CLK_ENABLE();
#if defined(STM32F4)
#if (CPY_STM32F4)
__HAL_RCC_PWR_CLK_ENABLE();
#endif
@ -170,31 +170,63 @@ safe_mode_t port_init(void) {
stm32_peripherals_gpio_init();
HAL_PWR_EnableBkUpAccess();
// TODO: move all of this to clocks.c
#if BOARD_HAS_LOW_SPEED_CRYSTAL
__HAL_RCC_LSE_CONFIG(RCC_LSE_ON);
uint32_t tickstart = HAL_GetTick();
// H7/F7 untested with LSE, so autofail them until above move is done
#if (CPY_STM32F4)
bool lse_setupsuccess = true;
uint32_t i = 0;
#else
bool lse_setupsuccess = false;
#endif
// Update LSE configuration in Backup Domain control register
// Requires to enable write access to Backup Domain of necessary
// TODO: should be using the HAL OSC initializer, otherwise we'll need
// preprocessor defines for every register to account for F7/H7
#if (CPY_STM32F4)
if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
{
// Enable write access to Backup domain
SET_BIT(PWR->CR, PWR_CR_DBP);
// Wait for Backup domain Write protection disable
tickstart = HAL_GetTick();
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
{
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
{
lse_setupsuccess = false;
}
}
}
#endif
__HAL_RCC_LSE_CONFIG(RCC_LSE_ON);
tickstart = HAL_GetTick();
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) {
if ( ++i > 1000000 )
if((HAL_GetTick() - tickstart ) > LSE_STARTUP_TIMEOUT)
{
lse_setupsuccess = false;
__HAL_RCC_LSE_CONFIG(RCC_LSE_OFF);
__HAL_RCC_LSI_ENABLE();
rtc_clock_frequency = LSI_VALUE;
break;
}
}
#else
__HAL_RCC_LSI_ENABLE();
#endif
#if BOARD_HAS_LOW_SPEED_CRYSTAL
if (lse_setupsuccess) {
__HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSE);
} else {
__HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSI);
}
#else
__HAL_RCC_LSI_ENABLE();
__HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSI);
#endif
__HAL_RCC_RTC_ENABLE();
_hrtc.Instance = RTC;
_hrtc.Init.HourFormat = RTC_HOURFORMAT_24;