2021-08-04 19:27:54 -04:00
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/*
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* This file is part of the MicroPython project, http://micropython.org/
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2021 microDev
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "shared-bindings/busio/UART.h"
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#include "py/stream.h"
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#include "py/mperrno.h"
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#include "py/runtime.h"
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#include "supervisor/shared/tick.h"
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#include "shared/runtime/interrupt_char.h"
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#include "shared-bindings/microcontroller/Pin.h"
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#include "peripherals/broadcom/cpu.h"
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#include "peripherals/broadcom/defines.h"
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#include "peripherals/broadcom/gpio.h"
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#include "peripherals/broadcom/interrupts.h"
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#include "peripherals/broadcom/vcmailbox.h"
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#define NO_PIN 0xff
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2021-12-03 16:15:24 -05:00
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// UART1 is a different peripheral than the rest so it is hardcoded below.
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#if BCM_VERSION == 2711
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#define NUM_UART (6)
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STATIC ARM_UART_PL011_Type *uart[NUM_UART] = {UART0, NULL, UART2, UART3, UART4, UART5};
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#else
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#define NUM_UART (2)
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STATIC ARM_UART_PL011_Type *uart[NUM_UART] = {UART0, NULL};
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#endif
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2021-08-04 19:27:54 -04:00
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typedef enum {
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STATUS_FREE = 0,
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STATUS_BUSY,
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STATUS_NEVER_RESET
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} uart_status_t;
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2021-12-03 16:15:24 -05:00
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static uart_status_t uart_status[NUM_UART];
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static busio_uart_obj_t *active_uart[NUM_UART];
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2021-08-04 19:27:54 -04:00
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void reset_uart(void) {
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2021-12-03 16:15:24 -05:00
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bool any_pl011_active = false;
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for (uint8_t num = 0; num < NUM_UART; num++) {
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2021-08-04 19:27:54 -04:00
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if (uart_status[num] == STATUS_BUSY) {
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2021-12-03 16:15:24 -05:00
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if (num == 1) {
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UART1->IER_b.DATA_READY = false;
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UART1->CNTL = 0;
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COMPLETE_MEMORY_READS;
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AUX->ENABLES_b.UART_1 = false;
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} else {
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ARM_UART_PL011_Type *pl011 = uart[num];
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pl011->CR = 0;
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}
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active_uart[num] = NULL;
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2021-08-04 19:27:54 -04:00
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uart_status[num] = STATUS_FREE;
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2021-12-03 16:15:24 -05:00
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} else {
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any_pl011_active = any_pl011_active || (num != 1 && uart_status[num] == STATUS_NEVER_RESET);
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2021-08-04 19:27:54 -04:00
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}
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}
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2021-12-03 16:15:24 -05:00
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if (!any_pl011_active) {
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BP_DisableIRQ(UART_IRQn);
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}
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COMPLETE_MEMORY_READS;
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if (AUX->ENABLES == 0) {
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BP_DisableIRQ(AUX_IRQn);
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}
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2021-08-04 19:27:54 -04:00
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}
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2021-12-03 16:15:24 -05:00
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STATIC void fetch_all_from_fifo(busio_uart_obj_t *self) {
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if (self->uart_id == 1) {
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while (UART1->STAT_b.DATA_READY && ringbuf_num_empty(&self->ringbuf) > 0) {
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int c = UART1->IO_b.DATA;
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if (self->sigint_enabled && c == mp_interrupt_char) {
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mp_sched_keyboard_interrupt();
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continue;
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}
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ringbuf_put(&self->ringbuf, c);
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}
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} else {
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ARM_UART_PL011_Type *pl011 = uart[self->uart_id];
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while (!pl011->FR_b.RXFE && ringbuf_num_empty(&self->ringbuf) > 0) {
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int c = pl011->DR_b.DATA;
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if (self->sigint_enabled && c == mp_interrupt_char) {
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mp_sched_keyboard_interrupt();
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continue;
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}
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ringbuf_put(&self->ringbuf, c);
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}
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}
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}
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2021-08-04 19:27:54 -04:00
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void UART1_IRQHandler(void) {
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2021-12-03 16:15:24 -05:00
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fetch_all_from_fifo(active_uart[1]);
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2021-08-04 19:27:54 -04:00
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// We couldn't read all pending data (overrun) so clear the FIFO so that the interrupt
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// can finish.
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if (UART1->STAT_b.DATA_READY) {
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UART1->IIR_b.DATA_READY = 1;
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}
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}
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2021-12-03 16:15:24 -05:00
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void pl011_IRQHandler(uint8_t index) {
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fetch_all_from_fifo(active_uart[index]);
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// Clear the interrupt in case we weren't able to clear it by emptying the
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// FIFO. (This won't clear the FIFO.)
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ARM_UART_PL011_Type *pl011 = uart[index];
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pl011->ICR = UART0_ICR_RXIC_Msk;
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}
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void UART0_IRQHandler(void) {
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pl011_IRQHandler(0);
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}
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#if BCM_VERSION == 2711
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void UART2_IRQHandler(void) {
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pl011_IRQHandler(2);
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}
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void UART3_IRQHandler(void) {
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pl011_IRQHandler(3);
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}
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void UART4_IRQHandler(void) {
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pl011_IRQHandler(4);
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}
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void UART5_IRQHandler(void) {
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pl011_IRQHandler(5);
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}
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#endif
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2021-08-04 19:27:54 -04:00
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void common_hal_busio_uart_never_reset(busio_uart_obj_t *self) {
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uart_status[self->uart_id] = STATUS_NEVER_RESET;
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2021-12-07 21:07:38 -05:00
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common_hal_never_reset_pin(self->tx_pin);
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common_hal_never_reset_pin(self->rx_pin);
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common_hal_never_reset_pin(self->cts_pin);
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common_hal_never_reset_pin(self->rts_pin);
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2021-08-04 19:27:54 -04:00
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}
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void common_hal_busio_uart_construct(busio_uart_obj_t *self,
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const mcu_pin_obj_t *tx, const mcu_pin_obj_t *rx,
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const mcu_pin_obj_t *rts, const mcu_pin_obj_t *cts,
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const mcu_pin_obj_t *rs485_dir, bool rs485_invert,
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uint32_t baudrate, uint8_t bits, busio_uart_parity_t parity, uint8_t stop,
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mp_float_t timeout, uint16_t receiver_buffer_size, byte *receiver_buffer,
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bool sigint_enabled) {
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2022-05-13 15:33:43 -04:00
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mp_arg_validate_int_max(bits, 8, MP_QSTR_bits);
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mp_arg_validate_int_min(receiver_buffer_size, 1, MP_QSTR_receiver_buffer_size);
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2021-08-04 19:27:54 -04:00
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if ((rs485_dir != NULL) || (rs485_invert)) {
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mp_raise_NotImplementedError(translate("RS485 Not yet supported on this device"));
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}
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2021-12-03 16:15:24 -05:00
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size_t instance_index = NUM_UART;
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BP_Function_Enum tx_alt = 0;
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BP_Function_Enum rx_alt = 0;
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BP_Function_Enum rts_alt = 0;
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BP_Function_Enum cts_alt = 0;
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for (size_t i = 0; i < NUM_UART; i++) {
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if (uart_status[i] != STATUS_FREE) {
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continue;
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2021-08-04 19:27:54 -04:00
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}
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2021-12-03 16:15:24 -05:00
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if (tx != NULL) {
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if (!pin_find_alt(tx, PIN_FUNCTION_UART, i, UART_FUNCTION_TXD, &tx_alt)) {
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continue;
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}
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if (rts != NULL && !pin_find_alt(rts, PIN_FUNCTION_UART, i, UART_FUNCTION_RTS, &rts_alt)) {
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continue;
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}
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}
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if (rx != NULL) {
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if (!pin_find_alt(rx, PIN_FUNCTION_UART, i, UART_FUNCTION_RXD, &rx_alt)) {
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continue;
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}
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if (cts != NULL && !pin_find_alt(cts, PIN_FUNCTION_UART, i, UART_FUNCTION_CTS, &cts_alt)) {
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continue;
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}
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}
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instance_index = i;
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break;
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}
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if (instance_index == NUM_UART) {
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2022-05-13 15:33:43 -04:00
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raise_ValueError_invalid_pins();
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2021-08-04 19:27:54 -04:00
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}
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self->rx_pin = rx;
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self->tx_pin = tx;
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2021-12-03 16:15:24 -05:00
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self->rts_pin = rts;
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self->cts_pin = cts;
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self->sigint_enabled = sigint_enabled;
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2021-08-04 19:27:54 -04:00
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if (rx != NULL) {
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2022-09-16 18:46:02 -04:00
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// Use the provided buffer when given.
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2021-08-04 19:27:54 -04:00
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if (receiver_buffer != NULL) {
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2022-09-16 18:46:02 -04:00
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ringbuf_init(&self->ringbuf, receiver_buffer, receiver_buffer_size);
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2021-08-04 19:27:54 -04:00
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} else {
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// Initially allocate the UART's buffer in the long-lived part of the
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// heap. UARTs are generally long-lived objects, but the "make long-
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// lived" machinery is incapable of moving internal pointers like
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// self->buffer, so do it manually. (However, as long as internal
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// pointers like this are NOT moved, allocating the buffer
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// in the long-lived pool is not strictly necessary)
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if (!ringbuf_alloc(&self->ringbuf, receiver_buffer_size, true)) {
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2022-05-13 15:33:43 -04:00
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m_malloc_fail(receiver_buffer_size);
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2021-08-04 19:27:54 -04:00
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}
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}
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}
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2021-12-03 16:15:24 -05:00
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active_uart[self->uart_id] = self;
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ARM_UART_PL011_Type *pl011 = uart[self->uart_id];
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2021-08-04 19:27:54 -04:00
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if (self->uart_id == 1) {
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AUX->ENABLES_b.UART_1 = true;
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UART1->IER = 0;
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UART1->CNTL = 0;
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if (bits == 8) {
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UART1->LCR_b.DATA_SIZE = UART1_LCR_DATA_SIZE_MODE_8BIT;
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} else if (bits == 7) {
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UART1->LCR_b.DATA_SIZE = UART1_LCR_DATA_SIZE_MODE_7BIT;
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}
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UART1->MCR = 0;
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UART1->IER = 0;
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// Clear interrupts
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UART1->IIR = 0xff;
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2021-12-03 16:15:24 -05:00
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common_hal_busio_uart_set_baudrate(self, baudrate);
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2021-08-04 19:27:54 -04:00
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if (tx != NULL) {
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UART1->CNTL |= UART1_CNTL_TX_ENABLE_Msk;
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}
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if (rx != NULL) {
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UART1->CNTL |= UART1_CNTL_RX_ENABLE_Msk;
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}
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2021-12-03 16:15:24 -05:00
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} else {
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// Ensure the UART is disabled as we configure it.
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pl011->CR_b.UARTEN = false;
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pl011->IMSC = 0;
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pl011->ICR = 0x3ff;
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common_hal_busio_uart_set_baudrate(self, baudrate);
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uint32_t line_control = UART0_LCR_H_FEN_Msk;
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line_control |= (bits - 5) << UART0_LCR_H_WLEN_Pos;
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if (stop == 2) {
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line_control |= UART0_LCR_H_STP2_Msk;
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}
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if (parity != BUSIO_UART_PARITY_NONE) {
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line_control |= UART0_LCR_H_PEN_Msk;
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}
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if (parity == BUSIO_UART_PARITY_EVEN) {
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line_control |= UART0_LCR_H_EPS_Msk;
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}
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pl011->LCR_H = line_control;
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uint32_t control = UART0_CR_UARTEN_Msk;
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if (tx != NULL) {
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control |= UART0_CR_TXE_Msk;
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}
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if (rx != NULL) {
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control |= UART0_CR_RXE_Msk;
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}
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if (cts != NULL) {
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control |= UART0_CR_CTSEN_Msk;
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}
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if (rts != NULL) {
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control |= UART0_CR_RTSEN_Msk;
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}
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pl011->CR = control;
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}
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// Setup the pins after waiting for UART stuff
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COMPLETE_MEMORY_READS;
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if (tx != NULL) {
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gpio_set_pull(tx->number, BP_PULL_NONE);
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gpio_set_function(tx->number, tx_alt);
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}
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if (rx != NULL) {
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gpio_set_pull(rx->number, BP_PULL_NONE);
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gpio_set_function(rx->number, rx_alt);
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}
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if (rts != NULL) {
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gpio_set_pull(rts->number, BP_PULL_NONE);
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gpio_set_function(rts->number, rts_alt);
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}
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if (cts != NULL) {
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gpio_set_pull(cts->number, BP_PULL_NONE);
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gpio_set_function(cts->number, cts_alt);
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}
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// Turn on interrupts
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COMPLETE_MEMORY_READS;
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if (self->uart_id == 1) {
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2021-08-04 19:27:54 -04:00
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UART1->IER_b.DATA_READY = true;
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// Never disable this in case the SPIs are used. They can each be
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// disabled at the peripheral itself.
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BP_EnableIRQ(AUX_IRQn);
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2021-12-03 16:15:24 -05:00
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} else {
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pl011->IMSC_b.RXIM = true;
|
|
|
|
// Never disable this in case the other PL011 UARTs are used.
|
|
|
|
BP_EnableIRQ(UART_IRQn);
|
2021-08-04 19:27:54 -04:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
bool common_hal_busio_uart_deinited(busio_uart_obj_t *self) {
|
|
|
|
return self->tx_pin == NULL && self->rx_pin == NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
void common_hal_busio_uart_deinit(busio_uart_obj_t *self) {
|
|
|
|
if (common_hal_busio_uart_deinited(self)) {
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
if (self->uart_id == 1) {
|
|
|
|
UART1->IER_b.DATA_READY = false;
|
|
|
|
UART1->CNTL = 0;
|
|
|
|
AUX->ENABLES_b.UART_1 = false;
|
2021-12-03 16:15:24 -05:00
|
|
|
} else {
|
|
|
|
ARM_UART_PL011_Type *pl011 = uart[self->uart_id];
|
|
|
|
pl011->CR = 0;
|
2021-08-04 19:27:54 -04:00
|
|
|
}
|
2021-12-03 16:15:24 -05:00
|
|
|
active_uart[self->uart_id] = NULL;
|
2022-09-16 18:46:02 -04:00
|
|
|
ringbuf_deinit(&self->ringbuf);
|
2021-08-04 19:27:54 -04:00
|
|
|
uart_status[self->uart_id] = STATUS_FREE;
|
|
|
|
common_hal_reset_pin(self->tx_pin);
|
|
|
|
common_hal_reset_pin(self->rx_pin);
|
|
|
|
common_hal_reset_pin(self->cts_pin);
|
|
|
|
common_hal_reset_pin(self->rts_pin);
|
|
|
|
self->tx_pin = NULL;
|
|
|
|
self->rx_pin = NULL;
|
|
|
|
self->cts_pin = NULL;
|
|
|
|
self->rts_pin = NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Write characters.
|
|
|
|
size_t common_hal_busio_uart_write(busio_uart_obj_t *self, const uint8_t *data, size_t len, int *errcode) {
|
|
|
|
if (self->tx_pin == NULL) {
|
|
|
|
mp_raise_ValueError(translate("No TX pin"));
|
|
|
|
}
|
|
|
|
|
2021-12-03 16:15:24 -05:00
|
|
|
COMPLETE_MEMORY_READS;
|
|
|
|
ARM_UART_PL011_Type *pl011 = uart[self->uart_id];
|
|
|
|
for (size_t i = 0; i < len; i++) {
|
|
|
|
if (self->uart_id == 1) {
|
2021-08-04 19:27:54 -04:00
|
|
|
// Wait for the FIFO to have space.
|
|
|
|
while (!UART1->STAT_b.TX_READY) {
|
|
|
|
RUN_BACKGROUND_TASKS;
|
|
|
|
}
|
|
|
|
UART1->IO = data[i];
|
2021-12-03 16:15:24 -05:00
|
|
|
} else {
|
|
|
|
while (pl011->FR_b.TXFF) {
|
|
|
|
RUN_BACKGROUND_TASKS;
|
|
|
|
}
|
|
|
|
pl011->DR_b.DATA = data[i];
|
|
|
|
}
|
|
|
|
}
|
|
|
|
// Wait for the data to be shifted out
|
|
|
|
if (self->uart_id == 1) {
|
|
|
|
while (!UART1->STAT_b.TX_DONE) {
|
|
|
|
RUN_BACKGROUND_TASKS;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
while (pl011->FR_b.BUSY) {
|
|
|
|
RUN_BACKGROUND_TASKS;
|
2021-08-04 19:27:54 -04:00
|
|
|
}
|
|
|
|
}
|
2021-12-03 16:15:24 -05:00
|
|
|
COMPLETE_MEMORY_READS;
|
|
|
|
return len;
|
|
|
|
}
|
2021-08-04 19:27:54 -04:00
|
|
|
|
2021-12-03 16:15:24 -05:00
|
|
|
STATIC void disable_interrupt(busio_uart_obj_t *self) {
|
|
|
|
if (self->uart_id == 1) {
|
|
|
|
UART1->IER_b.DATA_READY = false;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
STATIC void enable_interrupt(busio_uart_obj_t *self) {
|
|
|
|
if (self->uart_id == 1) {
|
|
|
|
UART1->IER_b.DATA_READY = true;
|
|
|
|
}
|
2021-08-04 19:27:54 -04:00
|
|
|
}
|
|
|
|
|
|
|
|
// Read characters.
|
|
|
|
size_t common_hal_busio_uart_read(busio_uart_obj_t *self, uint8_t *data, size_t len, int *errcode) {
|
|
|
|
if (self->rx_pin == NULL) {
|
|
|
|
mp_raise_ValueError(translate("No RX pin"));
|
|
|
|
}
|
|
|
|
|
|
|
|
if (len == 0) {
|
|
|
|
// Nothing to read.
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
COMPLETE_MEMORY_READS;
|
|
|
|
|
|
|
|
// Prevent conflict with uart irq.
|
2021-12-03 16:15:24 -05:00
|
|
|
disable_interrupt(self);
|
2021-08-04 19:27:54 -04:00
|
|
|
|
|
|
|
// Copy as much received data as available, up to len bytes.
|
|
|
|
size_t total_read = ringbuf_get_n(&self->ringbuf, data, len);
|
|
|
|
|
|
|
|
// Check if we still need to read more data.
|
|
|
|
if (len > total_read) {
|
|
|
|
len -= total_read;
|
|
|
|
uint64_t start_ticks = supervisor_ticks_ms64();
|
|
|
|
// Busy-wait until timeout or until we've read enough chars.
|
|
|
|
while (len > 0 && (supervisor_ticks_ms64() - start_ticks < self->timeout_ms)) {
|
2021-12-03 16:15:24 -05:00
|
|
|
fetch_all_from_fifo(self);
|
|
|
|
size_t additional_read = ringbuf_get_n(&self->ringbuf, data + total_read, len);
|
|
|
|
len -= additional_read;
|
|
|
|
total_read += additional_read;
|
|
|
|
if (additional_read > 0) {
|
2021-08-04 19:27:54 -04:00
|
|
|
// Reset the timeout on every character read.
|
|
|
|
start_ticks = supervisor_ticks_ms64();
|
|
|
|
}
|
|
|
|
RUN_BACKGROUND_TASKS;
|
|
|
|
// Allow user to break out of a timeout with a KeyboardInterrupt.
|
|
|
|
if (mp_hal_is_interrupted()) {
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// Now that we've emptied the ringbuf some, fill it up with anything in the
|
|
|
|
// FIFO. This ensures that we'll empty the FIFO as much as possible and
|
|
|
|
// reset the interrupt when we catch up.
|
2021-12-03 16:15:24 -05:00
|
|
|
fetch_all_from_fifo(self);
|
2021-08-04 19:27:54 -04:00
|
|
|
|
|
|
|
// Re-enable irq.
|
2021-12-03 16:15:24 -05:00
|
|
|
enable_interrupt(self);
|
2021-08-04 19:27:54 -04:00
|
|
|
|
|
|
|
COMPLETE_MEMORY_READS;
|
|
|
|
if (total_read == 0) {
|
|
|
|
*errcode = EAGAIN;
|
|
|
|
return MP_STREAM_ERROR;
|
|
|
|
}
|
|
|
|
|
|
|
|
return total_read;
|
|
|
|
}
|
|
|
|
|
|
|
|
uint32_t common_hal_busio_uart_get_baudrate(busio_uart_obj_t *self) {
|
|
|
|
return self->baudrate;
|
|
|
|
}
|
|
|
|
|
|
|
|
void common_hal_busio_uart_set_baudrate(busio_uart_obj_t *self, uint32_t baudrate) {
|
2021-12-03 16:15:24 -05:00
|
|
|
if (self->uart_id == 1) {
|
|
|
|
uint32_t source_clock = vcmailbox_get_clock_rate_measured(VCMAILBOX_CLOCK_CORE);
|
|
|
|
UART1->BAUD = ((source_clock / (baudrate * 8)) - 1);
|
|
|
|
} else {
|
|
|
|
ARM_UART_PL011_Type *pl011 = uart[self->uart_id];
|
|
|
|
bool reenable = false;
|
|
|
|
if (pl011->CR_b.UARTEN) {
|
|
|
|
pl011->CR_b.UARTEN = false;
|
|
|
|
reenable = true;
|
|
|
|
}
|
|
|
|
uint32_t source_clock = vcmailbox_get_clock_rate_measured(VCMAILBOX_CLOCK_UART);
|
|
|
|
uint32_t divisor = 16 * baudrate;
|
|
|
|
pl011->IBRD = source_clock / divisor;
|
|
|
|
// The fractional divisor is 64ths.
|
|
|
|
uint32_t remainder = source_clock % divisor;
|
|
|
|
uint32_t per_tick = (divisor / 64) + 1;
|
|
|
|
uint32_t adjust = 0;
|
|
|
|
if (remainder % per_tick > 0) {
|
|
|
|
adjust = 1;
|
|
|
|
}
|
|
|
|
pl011->FBRD = remainder / per_tick + adjust;
|
|
|
|
if (reenable) {
|
|
|
|
pl011->CR_b.UARTEN = true;
|
|
|
|
}
|
|
|
|
}
|
2021-08-04 19:27:54 -04:00
|
|
|
self->baudrate = baudrate;
|
|
|
|
}
|
|
|
|
|
|
|
|
mp_float_t common_hal_busio_uart_get_timeout(busio_uart_obj_t *self) {
|
|
|
|
return (mp_float_t)(self->timeout_ms / 1000.0L);
|
|
|
|
}
|
|
|
|
|
|
|
|
void common_hal_busio_uart_set_timeout(busio_uart_obj_t *self, mp_float_t timeout) {
|
|
|
|
self->timeout_ms = timeout * 1000;
|
|
|
|
}
|
|
|
|
|
|
|
|
uint32_t common_hal_busio_uart_rx_characters_available(busio_uart_obj_t *self) {
|
2021-12-03 16:15:24 -05:00
|
|
|
fetch_all_from_fifo(self);
|
2021-08-04 19:27:54 -04:00
|
|
|
return ringbuf_num_filled(&self->ringbuf);
|
|
|
|
}
|
|
|
|
|
|
|
|
void common_hal_busio_uart_clear_rx_buffer(busio_uart_obj_t *self) {
|
|
|
|
ringbuf_clear(&self->ringbuf);
|
|
|
|
}
|
|
|
|
|
|
|
|
bool common_hal_busio_uart_ready_to_tx(busio_uart_obj_t *self) {
|
|
|
|
if (self->tx_pin == NULL) {
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
if (self->uart_id == 1) {
|
|
|
|
return UART1->STAT_b.TX_READY;
|
|
|
|
}
|
2021-12-03 16:15:24 -05:00
|
|
|
return !uart[self->uart_id]->FR_b.TXFF;
|
2021-08-04 19:27:54 -04:00
|
|
|
}
|