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circuitpython/ports/mimxrt/hal/pwm_backport.c

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mimxrt: Support PWM using the FLEXPWM and QTMR modules. Frequency range 15Hz/18Hz to > 1 MHz, with decreasing resolution of the duty cycle. The basic API is supported as documentated, except that keyword parameters are accepted for both the instatiaton and the PWM.init() call. Extensions: support PWM for channel pairs. Channel pairs are declared by supplying 2-element tuples for the pins. The two channels of a pair must be the A/B channel of a FLEXPWM module. These form than a complementary pair. Additional supported keyword arguments: - center=value Defines the center position of a pulse within the pulse cycle. The align keyword is actually shortcut for center. - sync=True|False: If set to True, the channels will be synchronized to a submodule 0 channel, which has already to be enabled. - align=PWM.MIDDLE | PMW.BEGIN | PWM.END. It defines, whether synchronized channels are Center-Aligned or Edge-aligned. The channels must be either complementary a channel pair or a group of synchronized channels. It may as well be applied to a single channel, but withiout any benefit. - invert= 0..3. Controls ouput inversion of the pins. Bit 0 controls the first pin, bit 1 the second. - deadtime=time_ns time of complementary channels for delaying the rising slope. - xor=0|1|2 xor causes the output of channel A and B to be xored. If applied to a X channel, it shows the value oif A ^ B. If applied to an A or B channel, both channel show the xored signal for xor=1. For xor=2, the xored signal is split between channels A and B. See also the Reference Manual, chapter about double pulses. The behavior of xor=2 can also be achieved using the center method for locating a pulse within a clock period. The output is enabled for board pins only. CPU pins may still be used for FLEXPWM, e.g. as sync source, but the signal will not be routed to the output. That applies only to FLEXPWM pins. The use of QTMR pins which are not board pins will be rejected. As part of this commit, the _WFE() statement is removed from ticks_delay_us64() to prevent PWM glitching during calls to sleep().
2021-07-26 06:48:25 -04:00
/*
* This file is part of the MicroPython project, http://micropython.org/
*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP *
* Copyright (c) 2021 Robert Hammelrath
* SPDX-License-Identifier: BSD-3-Clause
*
*/
// These are a few functions taken from the NXP-Lib
// for PWM, for
// - dealing with an u16 duty cycle setting,
// - setting the pulse center position, and
// - factoring out pure duty cycle change.
#include "py/runtime.h"
#include "hal/pwm_backport.h"
void PWM_UpdatePwmDutycycle_u16(
PWM_Type *base, pwm_submodule_t subModule, pwm_channels_t pwmSignal, uint16_t dutyCycle, uint16_t Center_u16) {
assert((uint16_t)pwmSignal < 2U);
uint16_t pulseCnt = 0, pwmHighPulse = 0;
uint16_t center;
// check and confine bounds for Center_u16
if ((Center_u16 + dutyCycle / 2) >= PWM_FULL_SCALE) {
Center_u16 = PWM_FULL_SCALE - dutyCycle / 2 - 1;
} else if (Center_u16 < (dutyCycle / 2)) {
Center_u16 = dutyCycle / 2;
}
pulseCnt = base->SM[subModule].VAL1 + 1;
// Calculate pulse width and center position
pwmHighPulse = (pulseCnt * dutyCycle) / PWM_FULL_SCALE;
center = (pulseCnt * Center_u16) / PWM_FULL_SCALE;
// Setup the PWM dutycycle of channel A or B
if (pwmSignal == kPWM_PwmA) {
base->SM[subModule].VAL2 = center - pwmHighPulse / 2;
base->SM[subModule].VAL3 = base->SM[subModule].VAL2 + pwmHighPulse;
} else {
base->SM[subModule].VAL4 = center - pwmHighPulse / 2;
base->SM[subModule].VAL5 = base->SM[subModule].VAL4 + pwmHighPulse;
}
}
void PWM_SetupPwm_u16(PWM_Type *base, pwm_submodule_t subModule, pwm_signal_param_u16_t *chnlParams,
uint32_t pwmFreq_Hz, uint32_t srcClock_Hz, bool output_enable) {
uint32_t pwmClock;
uint16_t pulseCnt = 0;
uint8_t polarityShift = 0, outputEnableShift = 0;
// Divide the clock by the prescale value
pwmClock = (srcClock_Hz / (1U << ((base->SM[subModule].CTRL & PWM_CTRL_PRSC_MASK) >> PWM_CTRL_PRSC_SHIFT)));
mimxrt/hal/pwm_backport: Make PWM symmetric, and round division calcs. Ensure the symmetry of PWM: the duty rate of X and Q channels was not 50%, when it should have been. That is evident at high frequencies, like 15Mhz or 37.5 MHz. At low frequencies the deviation mattered less. The A/B channels were fine. Also round up or down non-integer division factors. Before, always the floor value was used.
2022-02-25 14:18:24 -05:00
pulseCnt = (pwmClock + (pwmFreq_Hz - 1) / 2) / pwmFreq_Hz;
mimxrt: Support PWM using the FLEXPWM and QTMR modules. Frequency range 15Hz/18Hz to > 1 MHz, with decreasing resolution of the duty cycle. The basic API is supported as documentated, except that keyword parameters are accepted for both the instatiaton and the PWM.init() call. Extensions: support PWM for channel pairs. Channel pairs are declared by supplying 2-element tuples for the pins. The two channels of a pair must be the A/B channel of a FLEXPWM module. These form than a complementary pair. Additional supported keyword arguments: - center=value Defines the center position of a pulse within the pulse cycle. The align keyword is actually shortcut for center. - sync=True|False: If set to True, the channels will be synchronized to a submodule 0 channel, which has already to be enabled. - align=PWM.MIDDLE | PMW.BEGIN | PWM.END. It defines, whether synchronized channels are Center-Aligned or Edge-aligned. The channels must be either complementary a channel pair or a group of synchronized channels. It may as well be applied to a single channel, but withiout any benefit. - invert= 0..3. Controls ouput inversion of the pins. Bit 0 controls the first pin, bit 1 the second. - deadtime=time_ns time of complementary channels for delaying the rising slope. - xor=0|1|2 xor causes the output of channel A and B to be xored. If applied to a X channel, it shows the value oif A ^ B. If applied to an A or B channel, both channel show the xored signal for xor=1. For xor=2, the xored signal is split between channels A and B. See also the Reference Manual, chapter about double pulses. The behavior of xor=2 can also be achieved using the center method for locating a pulse within a clock period. The output is enabled for board pins only. CPU pins may still be used for FLEXPWM, e.g. as sync source, but the signal will not be routed to the output. That applies only to FLEXPWM pins. The use of QTMR pins which are not board pins will be rejected. As part of this commit, the _WFE() statement is removed from ticks_delay_us64() to prevent PWM glitching during calls to sleep().
2021-07-26 06:48:25 -04:00
base->SM[subModule].INIT = 0;
base->SM[subModule].VAL1 = pulseCnt - 1;
// Set up the Registers VAL2..VAL5 controlling the duty cycle of channel A/B
PWM_UpdatePwmDutycycle_u16(base, subModule, chnlParams->pwmChannel,
chnlParams->dutyCycle_u16, chnlParams->Center_u16);
// Setup register shift values based on the channel being configured.
// Also setup the deadtime value
if (chnlParams->pwmChannel == kPWM_PwmA) {
polarityShift = PWM_OCTRL_POLA_SHIFT;
outputEnableShift = PWM_OUTEN_PWMA_EN_SHIFT;
base->SM[subModule].DTCNT0 = PWM_DTCNT0_DTCNT0(chnlParams->deadtimeValue);
} else {
polarityShift = PWM_OCTRL_POLB_SHIFT;
outputEnableShift = PWM_OUTEN_PWMB_EN_SHIFT;
base->SM[subModule].DTCNT1 = PWM_DTCNT1_DTCNT1(chnlParams->deadtimeValue);
}
// Setup signal active level
if (chnlParams->level == kPWM_HighTrue) {
base->SM[subModule].OCTRL &= ~(1U << polarityShift);
} else {
base->SM[subModule].OCTRL |= (1U << polarityShift);
}
// Enable PWM output
if (output_enable) {
base->OUTEN |= (1U << (outputEnableShift + subModule));
}
}
void PWM_SetupPwmx_u16(PWM_Type *base, pwm_submodule_t subModule,
uint32_t pwmFreq_Hz, uint16_t duty_cycle, uint8_t invert, uint32_t srcClock_Hz) {
uint32_t pulseCnt;
uint32_t pwmClock;
// Divide the clock by the prescale value
pwmClock = (srcClock_Hz / (1U << ((base->SM[subModule].CTRL & PWM_CTRL_PRSC_MASK) >> PWM_CTRL_PRSC_SHIFT)));
mimxrt/hal/pwm_backport: Make PWM symmetric, and round division calcs. Ensure the symmetry of PWM: the duty rate of X and Q channels was not 50%, when it should have been. That is evident at high frequencies, like 15Mhz or 37.5 MHz. At low frequencies the deviation mattered less. The A/B channels were fine. Also round up or down non-integer division factors. Before, always the floor value was used.
2022-02-25 14:18:24 -05:00
pulseCnt = (pwmClock + (pwmFreq_Hz - 1) / 2) / pwmFreq_Hz;
mimxrt: Support PWM using the FLEXPWM and QTMR modules. Frequency range 15Hz/18Hz to > 1 MHz, with decreasing resolution of the duty cycle. The basic API is supported as documentated, except that keyword parameters are accepted for both the instatiaton and the PWM.init() call. Extensions: support PWM for channel pairs. Channel pairs are declared by supplying 2-element tuples for the pins. The two channels of a pair must be the A/B channel of a FLEXPWM module. These form than a complementary pair. Additional supported keyword arguments: - center=value Defines the center position of a pulse within the pulse cycle. The align keyword is actually shortcut for center. - sync=True|False: If set to True, the channels will be synchronized to a submodule 0 channel, which has already to be enabled. - align=PWM.MIDDLE | PMW.BEGIN | PWM.END. It defines, whether synchronized channels are Center-Aligned or Edge-aligned. The channels must be either complementary a channel pair or a group of synchronized channels. It may as well be applied to a single channel, but withiout any benefit. - invert= 0..3. Controls ouput inversion of the pins. Bit 0 controls the first pin, bit 1 the second. - deadtime=time_ns time of complementary channels for delaying the rising slope. - xor=0|1|2 xor causes the output of channel A and B to be xored. If applied to a X channel, it shows the value oif A ^ B. If applied to an A or B channel, both channel show the xored signal for xor=1. For xor=2, the xored signal is split between channels A and B. See also the Reference Manual, chapter about double pulses. The behavior of xor=2 can also be achieved using the center method for locating a pulse within a clock period. The output is enabled for board pins only. CPU pins may still be used for FLEXPWM, e.g. as sync source, but the signal will not be routed to the output. That applies only to FLEXPWM pins. The use of QTMR pins which are not board pins will be rejected. As part of this commit, the _WFE() statement is removed from ticks_delay_us64() to prevent PWM glitching during calls to sleep().
2021-07-26 06:48:25 -04:00
base->SM[subModule].INIT = 0;
mimxrt/hal/pwm_backport: Make PWM symmetric, and round division calcs. Ensure the symmetry of PWM: the duty rate of X and Q channels was not 50%, when it should have been. That is evident at high frequencies, like 15Mhz or 37.5 MHz. At low frequencies the deviation mattered less. The A/B channels were fine. Also round up or down non-integer division factors. Before, always the floor value was used.
2022-02-25 14:18:24 -05:00
base->SM[subModule].VAL0 = ((uint32_t)duty_cycle * pulseCnt) / PWM_FULL_SCALE - 1;
mimxrt: Support PWM using the FLEXPWM and QTMR modules. Frequency range 15Hz/18Hz to > 1 MHz, with decreasing resolution of the duty cycle. The basic API is supported as documentated, except that keyword parameters are accepted for both the instatiaton and the PWM.init() call. Extensions: support PWM for channel pairs. Channel pairs are declared by supplying 2-element tuples for the pins. The two channels of a pair must be the A/B channel of a FLEXPWM module. These form than a complementary pair. Additional supported keyword arguments: - center=value Defines the center position of a pulse within the pulse cycle. The align keyword is actually shortcut for center. - sync=True|False: If set to True, the channels will be synchronized to a submodule 0 channel, which has already to be enabled. - align=PWM.MIDDLE | PMW.BEGIN | PWM.END. It defines, whether synchronized channels are Center-Aligned or Edge-aligned. The channels must be either complementary a channel pair or a group of synchronized channels. It may as well be applied to a single channel, but withiout any benefit. - invert= 0..3. Controls ouput inversion of the pins. Bit 0 controls the first pin, bit 1 the second. - deadtime=time_ns time of complementary channels for delaying the rising slope. - xor=0|1|2 xor causes the output of channel A and B to be xored. If applied to a X channel, it shows the value oif A ^ B. If applied to an A or B channel, both channel show the xored signal for xor=1. For xor=2, the xored signal is split between channels A and B. See also the Reference Manual, chapter about double pulses. The behavior of xor=2 can also be achieved using the center method for locating a pulse within a clock period. The output is enabled for board pins only. CPU pins may still be used for FLEXPWM, e.g. as sync source, but the signal will not be routed to the output. That applies only to FLEXPWM pins. The use of QTMR pins which are not board pins will be rejected. As part of this commit, the _WFE() statement is removed from ticks_delay_us64() to prevent PWM glitching during calls to sleep().
2021-07-26 06:48:25 -04:00
base->SM[subModule].VAL1 = pulseCnt - 1;
base->SM[subModule].OCTRL = (base->SM[subModule].OCTRL & ~PWM_OCTRL_POLX_MASK) | PWM_OCTRL_POLX(!invert);
base->OUTEN |= (1U << subModule);
}
void PWM_SetupFaultDisableMap(PWM_Type *base, pwm_submodule_t subModule,
pwm_channels_t pwmChannel, pwm_fault_channels_t pwm_fault_channels, uint16_t value) {
uint16_t reg = base->SM[subModule].DISMAP[pwm_fault_channels];
switch (pwmChannel) {
case kPWM_PwmA:
reg &= ~((uint16_t)PWM_DISMAP_DIS0A_MASK);
reg |= (((uint16_t)(value) << (uint16_t)PWM_DISMAP_DIS0A_SHIFT) & (uint16_t)PWM_DISMAP_DIS0A_MASK);
break;
case kPWM_PwmB:
reg &= ~((uint16_t)PWM_DISMAP_DIS0B_MASK);
reg |= (((uint16_t)(value) << (uint16_t)PWM_DISMAP_DIS0B_SHIFT) & (uint16_t)PWM_DISMAP_DIS0B_MASK);
break;
case kPWM_PwmX:
reg &= ~((uint16_t)PWM_DISMAP_DIS0X_MASK);
reg |= (((uint16_t)(value) << (uint16_t)PWM_DISMAP_DIS0X_SHIFT) & (uint16_t)PWM_DISMAP_DIS0X_MASK);
break;
default:
assert(false);
break;
}
base->SM[subModule].DISMAP[pwm_fault_channels] = reg;
}
#ifdef FSL_FEATURE_SOC_TMR_COUNT
status_t QTMR_SetupPwm_u16(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t pwmFreqHz,
uint16_t dutyCycleU16, bool outputPolarity, uint32_t srcClock_Hz, bool is_init) {
uint32_t periodCount, highCount, lowCount, reg;
if (dutyCycleU16 >= PWM_FULL_SCALE) {
// Invalid dutycycle
return kStatus_Fail;
}
// Counter values to generate a PWM signal
mimxrt/hal/pwm_backport: Make PWM symmetric, and round division calcs. Ensure the symmetry of PWM: the duty rate of X and Q channels was not 50%, when it should have been. That is evident at high frequencies, like 15Mhz or 37.5 MHz. At low frequencies the deviation mattered less. The A/B channels were fine. Also round up or down non-integer division factors. Before, always the floor value was used.
2022-02-25 14:18:24 -05:00
periodCount = ((srcClock_Hz + (pwmFreqHz - 1) / 2) / pwmFreqHz) - 2;
mimxrt: Support PWM using the FLEXPWM and QTMR modules. Frequency range 15Hz/18Hz to > 1 MHz, with decreasing resolution of the duty cycle. The basic API is supported as documentated, except that keyword parameters are accepted for both the instatiaton and the PWM.init() call. Extensions: support PWM for channel pairs. Channel pairs are declared by supplying 2-element tuples for the pins. The two channels of a pair must be the A/B channel of a FLEXPWM module. These form than a complementary pair. Additional supported keyword arguments: - center=value Defines the center position of a pulse within the pulse cycle. The align keyword is actually shortcut for center. - sync=True|False: If set to True, the channels will be synchronized to a submodule 0 channel, which has already to be enabled. - align=PWM.MIDDLE | PMW.BEGIN | PWM.END. It defines, whether synchronized channels are Center-Aligned or Edge-aligned. The channels must be either complementary a channel pair or a group of synchronized channels. It may as well be applied to a single channel, but withiout any benefit. - invert= 0..3. Controls ouput inversion of the pins. Bit 0 controls the first pin, bit 1 the second. - deadtime=time_ns time of complementary channels for delaying the rising slope. - xor=0|1|2 xor causes the output of channel A and B to be xored. If applied to a X channel, it shows the value oif A ^ B. If applied to an A or B channel, both channel show the xored signal for xor=1. For xor=2, the xored signal is split between channels A and B. See also the Reference Manual, chapter about double pulses. The behavior of xor=2 can also be achieved using the center method for locating a pulse within a clock period. The output is enabled for board pins only. CPU pins may still be used for FLEXPWM, e.g. as sync source, but the signal will not be routed to the output. That applies only to FLEXPWM pins. The use of QTMR pins which are not board pins will be rejected. As part of this commit, the _WFE() statement is removed from ticks_delay_us64() to prevent PWM glitching during calls to sleep().
2021-07-26 06:48:25 -04:00
highCount = (periodCount * dutyCycleU16) / PWM_FULL_SCALE;
lowCount = periodCount - highCount;
// Setup the compare registers for PWM output
if (is_init == false) {
base->CHANNEL[channel].COMP1 = lowCount;
base->CHANNEL[channel].COMP2 = highCount;
}
// Setup the pre-load registers for PWM output
base->CHANNEL[channel].CMPLD1 = lowCount;
base->CHANNEL[channel].CMPLD2 = highCount;
reg = base->CHANNEL[channel].CSCTRL;
// Setup the compare load control for COMP1 and COMP2.
// Load COMP1 when CSCTRL[TCF2] is asserted, load COMP2 when CSCTRL[TCF1] is asserted
reg &= ~(TMR_CSCTRL_CL1_MASK | TMR_CSCTRL_CL2_MASK);
reg |= (TMR_CSCTRL_CL1(kQTMR_LoadOnComp2) | TMR_CSCTRL_CL2(kQTMR_LoadOnComp1));
base->CHANNEL[channel].CSCTRL = reg;
// Set OFLAG pin for output mode
base->CHANNEL[channel].SCTRL |= TMR_SCTRL_OEN_MASK;
if (outputPolarity) {
// Invert the polarity
base->CHANNEL[channel].SCTRL |= TMR_SCTRL_OPS_MASK;
} else {
// True polarity, no inversion
base->CHANNEL[channel].SCTRL &= ~TMR_SCTRL_OPS_MASK;
}
reg = base->CHANNEL[channel].CTRL;
reg &= ~(TMR_CTRL_OUTMODE_MASK);
// Count until compare value is reached and re-initialize the counter, toggle OFLAG output
// using alternating compare register
reg |= (TMR_CTRL_LENGTH_MASK | TMR_CTRL_OUTMODE(kQTMR_ToggleOnAltCompareReg));
base->CHANNEL[channel].CTRL = reg;
return kStatus_Success;
}
#endif // FSL_FEATURE_SOC_TMR_COUNT
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