mimxrt/hal/pwm_backport: Make PWM symmetric, and round division calcs.
Ensure the symmetry of PWM: the duty rate of X and Q channels was not 50%, when it should have been. That is evident at high frequencies, like 15Mhz or 37.5 MHz. At low frequencies the deviation mattered less. The A/B channels were fine. Also round up or down non-integer division factors. Before, always the floor value was used.
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@ -53,7 +53,7 @@ void PWM_SetupPwm_u16(PWM_Type *base, pwm_submodule_t subModule, pwm_signal_para
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// Divide the clock by the prescale value
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pwmClock = (srcClock_Hz / (1U << ((base->SM[subModule].CTRL & PWM_CTRL_PRSC_MASK) >> PWM_CTRL_PRSC_SHIFT)));
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pulseCnt = pwmClock / pwmFreq_Hz;
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pulseCnt = (pwmClock + (pwmFreq_Hz - 1) / 2) / pwmFreq_Hz;
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base->SM[subModule].INIT = 0;
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base->SM[subModule].VAL1 = pulseCnt - 1;
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@ -93,9 +93,9 @@ void PWM_SetupPwmx_u16(PWM_Type *base, pwm_submodule_t subModule,
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// Divide the clock by the prescale value
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pwmClock = (srcClock_Hz / (1U << ((base->SM[subModule].CTRL & PWM_CTRL_PRSC_MASK) >> PWM_CTRL_PRSC_SHIFT)));
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pulseCnt = pwmClock / pwmFreq_Hz;
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pulseCnt = (pwmClock + (pwmFreq_Hz - 1) / 2) / pwmFreq_Hz;
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base->SM[subModule].INIT = 0;
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base->SM[subModule].VAL0 = ((uint32_t)duty_cycle * pulseCnt) / PWM_FULL_SCALE;
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base->SM[subModule].VAL0 = ((uint32_t)duty_cycle * pulseCnt) / PWM_FULL_SCALE - 1;
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base->SM[subModule].VAL1 = pulseCnt - 1;
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base->SM[subModule].OCTRL = (base->SM[subModule].OCTRL & ~PWM_OCTRL_POLX_MASK) | PWM_OCTRL_POLX(!invert);
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@ -137,7 +137,7 @@ status_t QTMR_SetupPwm_u16(TMR_Type *base, qtmr_channel_selection_t channel, uin
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}
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// Counter values to generate a PWM signal
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periodCount = (srcClock_Hz / pwmFreqHz) - 1;
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periodCount = ((srcClock_Hz + (pwmFreqHz - 1) / 2) / pwmFreqHz) - 2;
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highCount = (periodCount * dutyCycleU16) / PWM_FULL_SCALE;
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lowCount = periodCount - highCount;
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