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circuitpython/ports/silabs/boards/devkit_xg24_brd2601b/pin_functions.csv

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Silabs' new Pull Request for submoduling the ports/silabs/tools/slc_cli_linux/ (#7874) Doing a squash merge to avoid having the `slc_cli_linux` .zip files in the history. They were added in one commit and removed and replaced with a submodule in another. * Initial commit for xg24 * Fix SLC issue * Fix SLC extract fail * Change board's name * Correct spelling of code Build immediately after slc generate * Remove VID and PID * Change creator and creation id * Apply new creator_id and creation_id * Update makefile, error message, mcu_processor function * Update mpconfigboard.mk * Update Board extensions, PORT_DEPS * Update makefile * Add exclude_patterns * Show java, jinja2 version * Show path for debugging CI * Add requirements-dev for slc * Add PATH slc_cli * Update background function * Add jinja2 PATH * Show PATH * Update jinja2 path * Update jinja2 path * Update jinja2 path * Update jinja2 path * Change slc folder * Change markupsafe folder * Add symbolic link for slc * Update makefile * Update makefile * Update MX25R3235F.toml from submodule nvm.toml * alphabetize the list * Remove slc_cli_linux folder * Update slc_cli submodule --------- Co-authored-by: Chat Nguyen <cvnguyen@silabs.com> Co-authored-by: silabs-ChatNguyen <chat.nguyen@silabs.com> Co-authored-by: silabs-ChatNguyen <126220343+silabs-ChatNguyen@users.noreply.github.com>
2023-04-18 12:42:16 -04:00
EUSART0_CS,PA0,PA4,PA5,PA6,PA7,PB0,PB1,PB2,PB3,,,,,,,,,,,,,,
EUSART0_RX,PA0,PA4,PA5,PA6,PA7,PB0,PB1,PB2,PB3,,,,,,,,,,,,,,
EUSART0_SCLK,PA0,PA4,PA5,PA6,PA7,PB0,PB1,PB2,PB3,,,,,,,,,,,,,,
EUSART0_TX,PA0,PA4,PA5,PA6,PA7,PB0,PB1,PB2,PB3,,,,,,,,,,,,,,
EUSART1_CS,PA0,PA4,PA5,PA6,PA7,PB0,PB1,PB2,PB3,PC0,PC1,PC2,PC3,PC4,PC5,PC9,PD2,PD3,PD4,PD5,,,
EUSART1_RX,PA0,PA4,PA5,PA6,PA7,PB0,PB1,PB2,PB3,PC0,PC1,PC2,PC3,PC4,PC5,PC9,PD2,PD3,PD4,PD5,,,
EUSART1_SCLK,PA0,PA4,PA5,PA6,PA7,PB0,PB1,PB2,PB3,PC0,PC1,PC2,PC3,PC4,PC5,PC9,PD2,PD3,PD4,PD5,,,
EUSART1_TX,PA0,PA4,PA5,PA6,PA7,PB0,PB1,PB2,PB3,PC0,PC1,PC2,PC3,PC4,PC5,PC9,PD2,PD3,PD4,PD5,,,
I2C0_SCL,PA0,PA4,PA5,PA6,PA7,PB0,PB1,PB2,PB3,PC0,PC1,PC2,PC3,PC4,PC5,PC9,PD2,PD3,PD4,PD5,,,
I2C0_SDA,PA0,PA4,PA5,PA6,PA7,PB0,PB1,PB2,PB3,PC0,PC1,PC2,PC3,PC4,PC5,PC9,PD2,PD3,PD4,PD5,,,
I2C1_SCL,,,,,,,,,,PC0,PC1,PC2,PC3,PC4,PC5,PC9,PD2,PD3,PD4,PD5,,,
I2C1_SDA,,,,,,,,,,PC0,PC1,PC2,PC3,PC4,PC5,PC9,PD2,PD3,PD4,PD5,,,
TIMER0_CC0,PA0,PA4,PA5,PA6,PA7,PB0,PB1,PB2,PB3,PC0,PC1,PC2,PC3,PC4,PC5,PC9,PD2,PD3,PD4,PD5,,,
TIMER0_CC1,PA0,PA4,PA5,PA6,PA7,PB0,PB1,PB2,PB3,PC0,PC1,PC2,PC3,PC4,PC5,PC9,PD2,PD3,PD4,PD5,,,
TIMER0_CC2,PA0,PA4,PA5,PA6,PA7,PB0,PB1,PB2,PB3,PC0,PC1,PC2,PC3,PC4,PC5,PC9,PD2,PD3,PD4,PD5,,,
TIMER1_CC0,PA0,PA4,PA5,PA6,PA7,PB0,PB1,PB2,PB3,PC0,PC1,PC2,PC3,PC4,PC5,PC9,PD2,PD3,PD4,PD5,,,
TIMER1_CC1,PA0,PA4,PA5,PA6,PA7,PB0,PB1,PB2,PB3,PC0,PC1,PC2,PC3,PC4,PC5,PC9,PD2,PD3,PD4,PD5,,,
TIMER1_CC2,PA0,PA4,PA5,PA6,PA7,PB0,PB1,PB2,PB3,PC0,PC1,PC2,PC3,PC4,PC5,PC9,PD2,PD3,PD4,PD5,,,
TIMER2_CC0,PA0,PA4,PA5,PA6,PA7,PB0,PB1,PB2,PB3,,,,,,,,,,,,,,
TIMER2_CC1,PA0,PA4,PA5,PA6,PA7,PB0,PB1,PB2,PB3,,,,,,,,,,,,,,
TIMER2_CC2,PA0,PA4,PA5,PA6,PA7,PB0,PB1,PB2,PB3,,,,,,,,,,,,,,
TIMER3_CC0,,,,,,,,,,PC0,PC1,PC2,PC3,PC4,PC5,PC9,PD2,PD3,PD4,PD5,,,
TIMER3_CC1,,,,,,,,,,PC0,PC1,PC2,PC3,PC4,PC5,PC9,PD2,PD3,PD4,PD5,,,
TIMER3_CC2,,,,,,,,,,PC0,PC1,PC2,PC3,PC4,PC5,PC9,PD2,PD3,PD4,PD5,,,
TIMER4_CC0,PA0,PA4,PA5,PA6,PA7,PB0,PB1,PB2,PB3,,,,,,,,,,,,,,
TIMER4_CC1,PA0,PA4,PA5,PA6,PA7,PB0,PB1,PB2,PB3,,,,,,,,,,,,,,
TIMER4_CC2,PA0,PA4,PA5,PA6,PA7,PB0,PB1,PB2,PB3,,,,,,,,,,,,,,
USART0_CLK,PA0,PA4,PA5,PA6,PA7,PB0,PB1,PB2,PB3,PC0,PC1,PC2,PC3,PC4,PC5,PC9,PD2,PD3,PD4,PD5,,,
USART0_CS,PA0,PA4,PA5,PA6,PA7,PB0,PB1,PB2,PB3,PC0,PC1,PC2,PC3,PC4,PC5,PC9,PD2,PD3,PD4,PD5,,,
USART0_RX,PA0,PA4,PA5,PA6,PA7,PB0,PB1,PB2,PB3,PC0,PC1,PC2,PC3,PC4,PC5,PC9,PD2,PD3,PD4,PD5,,,
USART0_TX,PA0,PA4,PA5,PA6,PA7,PB0,PB1,PB2,PB3,PC0,PC1,PC2,PC3,PC4,PC5,PC9,PD2,PD3,PD4,PD5,,,
VDAC0_CH0,,,,,,PB0,,,,,,,,,,,,,,,,,
VDAC0_CH1,,,,,,,PB1,,,,,,,,,,,,,,,,
VDAC1_CH0,,,,,,,,PB2,,,,,,,,,,,,,,,
VDAC1_CH1,,,,,,,,,PB3,,,,,,,,,,,,,,