2017-11-06 18:35:23 -05:00
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// Derived from: Auto-generated config file peripheral_clk_config.h
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// Boilerplate removed.
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2017-09-22 21:05:51 -04:00
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#ifndef PERIPHERAL_CLK_CONFIG_H
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#define PERIPHERAL_CLK_CONFIG_H
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2017-11-06 18:35:23 -05:00
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// ADC
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2017-09-22 21:05:51 -04:00
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#define CONF_GCLK_ADC0_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
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#define CONF_GCLK_ADC0_FREQUENCY 120000000
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2017-11-06 18:35:23 -05:00
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// DAC
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2017-09-22 21:05:51 -04:00
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#define CONF_GCLK_DAC_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
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#define CONF_GCLK_DAC_FREQUENCY 120000000
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2017-11-06 18:35:23 -05:00
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// EVSYS
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2017-09-22 21:05:51 -04:00
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#define CONF_GCLK_EVSYS_CHANNEL_0_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
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#define CONF_GCLK_EVSYS_CHANNEL_0_FREQUENCY 120000000.0
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#define CONF_GCLK_EVSYS_CHANNEL_1_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
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#define CONF_GCLK_EVSYS_CHANNEL_1_FREQUENCY 120000000.0
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#define CONF_GCLK_EVSYS_CHANNEL_2_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
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#define CONF_GCLK_EVSYS_CHANNEL_2_FREQUENCY 120000000.0
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#define CONF_GCLK_EVSYS_CHANNEL_3_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
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#define CONF_GCLK_EVSYS_CHANNEL_3_FREQUENCY 120000000.0
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#define CONF_GCLK_EVSYS_CHANNEL_4_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
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#define CONF_GCLK_EVSYS_CHANNEL_4_FREQUENCY 120000000.0
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#define CONF_GCLK_EVSYS_CHANNEL_5_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
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#define CONF_GCLK_EVSYS_CHANNEL_5_FREQUENCY 120000000.0
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#define CONF_GCLK_EVSYS_CHANNEL_6_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
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#define CONF_GCLK_EVSYS_CHANNEL_6_FREQUENCY 120000000.0
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#define CONF_GCLK_EVSYS_CHANNEL_7_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
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#define CONF_GCLK_EVSYS_CHANNEL_7_FREQUENCY 120000000.0
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#define CONF_GCLK_EVSYS_CHANNEL_8_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
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#define CONF_GCLK_EVSYS_CHANNEL_8_FREQUENCY 120000000.0
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#define CONF_GCLK_EVSYS_CHANNEL_9_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
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#define CONF_GCLK_EVSYS_CHANNEL_9_FREQUENCY 120000000.0
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#define CONF_GCLK_EVSYS_CHANNEL_10_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
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#define CONF_GCLK_EVSYS_CHANNEL_10_FREQUENCY 120000000.0
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#define CONF_GCLK_EVSYS_CHANNEL_11_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
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#define CONF_GCLK_EVSYS_CHANNEL_11_FREQUENCY 120000000.0
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2017-11-06 18:35:23 -05:00
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// CPU: 120 MHz
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2017-09-22 21:05:51 -04:00
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#define CONF_CPU_FREQUENCY 120000000
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2017-11-06 18:35:23 -05:00
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// RTC
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2017-09-22 21:05:51 -04:00
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#define CONF_GCLK_RTC_SRC RTC_CLOCK_SOURCE
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#define CONF_GCLK_RTC_FREQUENCY 1024
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2017-11-06 18:35:23 -05:00
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// SERCOM
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// Use 48 MHz clock for CORE, and 32kHz clock for SLOW.
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// 120 MHz is too fast for CORE.
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// Slow is only needed for SMBus, it appears.
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2017-09-22 21:05:51 -04:00
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2017-11-06 18:35:23 -05:00
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#define CONF_GCLK_SERCOM0_CORE_SRC GCLK_PCHCTRL_GEN_GCLK1_Val
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2017-09-22 21:05:51 -04:00
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#define CONF_GCLK_SERCOM0_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
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2017-11-06 18:35:23 -05:00
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#define CONF_GCLK_SERCOM0_CORE_FREQUENCY 48000000
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2017-09-22 21:05:51 -04:00
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#define CONF_GCLK_SERCOM0_SLOW_FREQUENCY 32768
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2017-11-06 18:35:23 -05:00
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#define CONF_GCLK_SERCOM1_CORE_SRC GCLK_PCHCTRL_GEN_GCLK1_Val
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2017-09-22 21:05:51 -04:00
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#define CONF_GCLK_SERCOM1_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
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2017-11-06 18:35:23 -05:00
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#define CONF_GCLK_SERCOM1_CORE_FREQUENCY 48000000
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2017-09-22 21:05:51 -04:00
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#define CONF_GCLK_SERCOM1_SLOW_FREQUENCY 32768
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2017-11-06 18:35:23 -05:00
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#define CONF_GCLK_SERCOM2_CORE_SRC GCLK_PCHCTRL_GEN_GCLK1_Val
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#define CONF_GCLK_SERCOM2_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
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#define CONF_GCLK_SERCOM2_CORE_FREQUENCY 48000000
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#define CONF_GCLK_SERCOM2_SLOW_FREQUENCY 32768
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#define CONF_GCLK_SERCOM3_CORE_SRC GCLK_PCHCTRL_GEN_GCLK1_Val
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#define CONF_GCLK_SERCOM3_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
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#define CONF_GCLK_SERCOM3_CORE_FREQUENCY 48000000
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#define CONF_GCLK_SERCOM3_SLOW_FREQUENCY 32768
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#define CONF_GCLK_SERCOM4_CORE_SRC GCLK_PCHCTRL_GEN_GCLK1_Val
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#define CONF_GCLK_SERCOM4_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
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#define CONF_GCLK_SERCOM4_CORE_FREQUENCY 48000000
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#define CONF_GCLK_SERCOM4_SLOW_FREQUENCY 32768
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#define CONF_GCLK_SERCOM5_CORE_SRC GCLK_PCHCTRL_GEN_GCLK1_Val
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#define CONF_GCLK_SERCOM5_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
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#define CONF_GCLK_SERCOM5_CORE_FREQUENCY 48000000
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#define CONF_GCLK_SERCOM5_SLOW_FREQUENCY 32768
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#define CONF_GCLK_SERCOM6_CORE_SRC GCLK_PCHCTRL_GEN_GCLK1_Val
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#define CONF_GCLK_SERCOM6_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
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#define CONF_GCLK_SERCOM6_CORE_FREQUENCY 48000000
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#define CONF_GCLK_SERCOM6_SLOW_FREQUENCY 32768
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#define CONF_GCLK_SERCOM7_CORE_SRC GCLK_PCHCTRL_GEN_GCLK1_Val
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#define CONF_GCLK_SERCOM7_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
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#define CONF_GCLK_SERCOM7_CORE_FREQUENCY 48000000
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#define CONF_GCLK_SERCOM7_SLOW_FREQUENCY 32768
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// TC
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2017-09-22 21:05:51 -04:00
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#define CONF_GCLK_TC0_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
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#define CONF_GCLK_TC0_FREQUENCY 12000000
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2017-11-06 18:35:23 -05:00
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// USB
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2017-09-22 21:05:51 -04:00
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#define CONF_GCLK_USB_SRC GCLK_PCHCTRL_GEN_GCLK1_Val
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#define CONF_GCLK_USB_FREQUENCY 48000000
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#endif // PERIPHERAL_CLK_CONFIG_H
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