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circuitpython/ports/mimxrt/boards/TEENSY41/mpconfigboard.h

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mimxrt/boards: Add board configuration files for Teensy 4.1. These are at the moment more or less identical to the Teensy 4.0 files, except for the pins.csv file and the flash size.
2021-06-01 14:15:55 -04:00
#define MICROPY_HW_BOARD_NAME "Teensy 4.1"
#define MICROPY_HW_MCU_NAME "MIMXRT1062DVJ6A"
// Teensy 4.1 has 1 board LED
#define MICROPY_HW_LED1_PIN (pin_GPIO_B0_03)
#define MICROPY_HW_LED_ON(pin) (mp_hal_pin_high(pin))
#define MICROPY_HW_LED_OFF(pin) (mp_hal_pin_low(pin))
mimxrt/machine_uart: Add the UART class to the machine module. The implementation uses the LPUARTx devices. Up to 8 UARTs can be used, given that the pins are accessible. E.g. 8 on Teensy 4.1, 5 on MIMXRT1020_EVK. For Tennsy 4.0 and 4.1 the UART numbers are as printed on the pinout 1..N. The MIMXRT10xx-EVK boards have only one UART named, which gets the number 1. All other UART are assigned to different Pins: MIMXRT1010-EVK: D0/D1 UART 1 D6/D7 UART 2 A0/D4 UART 3 MIMXRT1020-EVK: D0/D1 UART 1 D6/D9 UART 2 D10/D12 UART 3 D14/D15 UART 4 A0/A1 UART 5 MIMXRT1050-EVK, MIMXRT1060-EVK, MIMXRT1064-EVK: D0/D1 UART 1 D7/D6 UART 2 D8/D9 UART 3 A1/A0 UART 4
2021-05-30 12:18:33 -04:00
mimxrt/machine_pin: Implement pin.irq() functionality.
2021-06-05 08:06:04 -04:00
#define MICROPY_HW_NUM_PIN_IRQS (4 * 32 + 3)
mimxrt/machine_uart: Add the UART class to the machine module. The implementation uses the LPUARTx devices. Up to 8 UARTs can be used, given that the pins are accessible. E.g. 8 on Teensy 4.1, 5 on MIMXRT1020_EVK. For Tennsy 4.0 and 4.1 the UART numbers are as printed on the pinout 1..N. The MIMXRT10xx-EVK boards have only one UART named, which gets the number 1. All other UART are assigned to different Pins: MIMXRT1010-EVK: D0/D1 UART 1 D6/D7 UART 2 A0/D4 UART 3 MIMXRT1020-EVK: D0/D1 UART 1 D6/D9 UART 2 D10/D12 UART 3 D14/D15 UART 4 A0/A1 UART 5 MIMXRT1050-EVK, MIMXRT1060-EVK, MIMXRT1064-EVK: D0/D1 UART 1 D7/D6 UART 2 D8/D9 UART 3 A1/A0 UART 4
2021-05-30 12:18:33 -04:00
// UART config: 8 UARTs at the pins for Teensy 4.1
#define MICROPY_HW_UART_NUM (sizeof(uart_index_table) / sizeof(uart_index_table)[0])
#define MICROPY_HW_UART_INDEX { 0, 6, 4, 2, 3, 8, 1, 7, 5 }
#define IOMUX_TABLE_UART \
{ IOMUXC_GPIO_AD_B0_12_LPUART1_TX }, { IOMUXC_GPIO_AD_B0_13_LPUART1_RX }, \
{ IOMUXC_GPIO_AD_B1_02_LPUART2_TX }, { IOMUXC_GPIO_AD_B1_03_LPUART2_RX }, \
{ IOMUXC_GPIO_AD_B1_06_LPUART3_TX }, { IOMUXC_GPIO_AD_B1_07_LPUART3_RX }, \
{ IOMUXC_GPIO_B1_00_LPUART4_TX }, { IOMUXC_GPIO_B1_01_LPUART4_RX }, \
{ IOMUXC_GPIO_B1_12_LPUART5_TX }, { IOMUXC_GPIO_B1_13_LPUART5_RX }, \
{ IOMUXC_GPIO_AD_B0_02_LPUART6_TX }, { IOMUXC_GPIO_AD_B0_03_LPUART6_RX }, \
{ IOMUXC_GPIO_EMC_31_LPUART7_TX }, { IOMUXC_GPIO_EMC_32_LPUART7_RX }, \
{ IOMUXC_GPIO_AD_B1_10_LPUART8_TX }, { IOMUXC_GPIO_AD_B1_11_LPUART8_RX },
mimxrt/machine_spi: Add the SPI class to the machine module. This class supports SPI bus controller mode, with blocking transfers. SPI device numbers start at 0, to comply with the pinout of the Teensy boards. With the configured clock frequency the fastest baud rate is 33MHz. For messages longer 16 bytes DMA is used. The class uses the existing framework with extmod/machine_spi.c. Extended driver options: - drive=n with n being between 1 and 6 or PIN.POWER_1 to PIN.POWER_6. Since the pins used by the SPI are fixed, no Pin settings can be made. Thus the drive option is added allowing to control ringing and crosstalk on the connection. - gap_ns=nnnnn is the time between sent data items in a frame given in ns. Default is 2 clock cycles.
2021-06-09 04:47:18 -04:00
#define MICROPY_HW_SPI_INDEX { 4, 3, 1 }
#define IOMUX_TABLE_SPI \
{ IOMUXC_GPIO_SD_B0_00_LPSPI1_SCK }, { IOMUXC_GPIO_SD_B0_01_LPSPI1_PCS0 }, \
{ IOMUXC_GPIO_SD_B0_02_LPSPI1_SDO }, { IOMUXC_GPIO_SD_B0_03_LPSPI1_SDI }, \
mimxrt: Allow to select cs0 or cs1 for SPI. Using the keyword argument cs=nnn in the constructor. The cs1 pin has to be defined in mpconfigboard.h. Note: Only a few boards have the CS1 pin exposed to the connectors.
2022-01-10 12:14:40 -05:00
{ IOMUXC_GPIO_EMC_31_LPSPI1_PCS1 }, \
mimxrt/machine_spi: Add the SPI class to the machine module. This class supports SPI bus controller mode, with blocking transfers. SPI device numbers start at 0, to comply with the pinout of the Teensy boards. With the configured clock frequency the fastest baud rate is 33MHz. For messages longer 16 bytes DMA is used. The class uses the existing framework with extmod/machine_spi.c. Extended driver options: - drive=n with n being between 1 and 6 or PIN.POWER_1 to PIN.POWER_6. Since the pins used by the SPI are fixed, no Pin settings can be made. Thus the drive option is added allowing to control ringing and crosstalk on the connection. - gap_ns=nnnnn is the time between sent data items in a frame given in ns. Default is 2 clock cycles.
2021-06-09 04:47:18 -04:00
{ 0 }, { 0 }, \
{ 0 }, { 0 }, \
mimxrt: Allow to select cs0 or cs1 for SPI. Using the keyword argument cs=nnn in the constructor. The cs1 pin has to be defined in mpconfigboard.h. Note: Only a few boards have the CS1 pin exposed to the connectors.
2022-01-10 12:14:40 -05:00
{ 0 }, \
mimxrt/boards/TEENSY41: Use the same SPI1 pins for Teensy 4.0 and 4.1. Teensy 4.1 used different pins for SPI1 than Teensy 4.0, which made the boards unnecessarily different.
2022-02-03 12:37:54 -05:00
{ IOMUXC_GPIO_AD_B1_15_LPSPI3_SCK }, { IOMUXC_GPIO_AD_B0_03_LPSPI3_PCS0 }, \
{ IOMUXC_GPIO_AD_B1_14_LPSPI3_SDO }, { IOMUXC_GPIO_AD_B0_02_LPSPI3_SDI }, \
mimxrt: Allow to select cs0 or cs1 for SPI. Using the keyword argument cs=nnn in the constructor. The cs1 pin has to be defined in mpconfigboard.h. Note: Only a few boards have the CS1 pin exposed to the connectors.
2022-01-10 12:14:40 -05:00
{ 0 }, \
mimxrt/machine_spi: Add the SPI class to the machine module. This class supports SPI bus controller mode, with blocking transfers. SPI device numbers start at 0, to comply with the pinout of the Teensy boards. With the configured clock frequency the fastest baud rate is 33MHz. For messages longer 16 bytes DMA is used. The class uses the existing framework with extmod/machine_spi.c. Extended driver options: - drive=n with n being between 1 and 6 or PIN.POWER_1 to PIN.POWER_6. Since the pins used by the SPI are fixed, no Pin settings can be made. Thus the drive option is added allowing to control ringing and crosstalk on the connection. - gap_ns=nnnnn is the time between sent data items in a frame given in ns. Default is 2 clock cycles.
2021-06-09 04:47:18 -04:00
{ IOMUXC_GPIO_B0_03_LPSPI4_SCK }, { IOMUXC_GPIO_B0_00_LPSPI4_PCS0 }, \
mimxrt: Allow to select cs0 or cs1 for SPI. Using the keyword argument cs=nnn in the constructor. The cs1 pin has to be defined in mpconfigboard.h. Note: Only a few boards have the CS1 pin exposed to the connectors.
2022-01-10 12:14:40 -05:00
{ IOMUXC_GPIO_B0_02_LPSPI4_SDO }, { IOMUXC_GPIO_B0_01_LPSPI4_SDI }, \
{ IOMUXC_GPIO_B1_03_LPSPI4_PCS1 }
mimxrt/machine_spi: Add the SPI class to the machine module. This class supports SPI bus controller mode, with blocking transfers. SPI device numbers start at 0, to comply with the pinout of the Teensy boards. With the configured clock frequency the fastest baud rate is 33MHz. For messages longer 16 bytes DMA is used. The class uses the existing framework with extmod/machine_spi.c. Extended driver options: - drive=n with n being between 1 and 6 or PIN.POWER_1 to PIN.POWER_6. Since the pins used by the SPI are fixed, no Pin settings can be made. Thus the drive option is added allowing to control ringing and crosstalk on the connection. - gap_ns=nnnnn is the time between sent data items in a frame given in ns. Default is 2 clock cycles.
2021-06-09 04:47:18 -04:00
#define DMA_REQ_SRC_RX { 0, kDmaRequestMuxLPSPI1Rx, kDmaRequestMuxLPSPI2Rx, \
mimxrt: Rework flash configuration. - Moves definition of BOARD_FLASH_SIZE and other header files related to flash configuration into the Makefile. - Adds board specific clock_config.h. - Adds board.h, pin_mux.h, and peripherals.h as they are required by NXP MCU SDK in order to use our own clock_config.h. - Renames board specific FlexSPI configuration files. - Updates flash frequency of MIMXRT1020_EVK - Creates separated flash_config files for QSPI NOR and QSPI Hyper flash. - Unifies VFS start address to be @ 1M for 1010 and 1020 boards. - Unifies 1050EVK boards - Adds support to both NOR and HyperFlash on boards with both capabilities. - Adds automatic FlexRAM initialization to start-up code based on linker script and NXP HAL. - Applies code formatting to all files in mimxrt port. With this change the flash configuration is restructured and organized. This simplifies the configuration process and provides a better overview of each board's settings. With the integration of clock_config.h, board.h, pin_mux.h, and peripherals.h we gain better control of the settings and clock configurations. Furthermore the implementation of an explicit FlexRAM setup improves the system performance and allows for performance tuning. Signed-off-by: Philipp Ebensberger
2021-08-20 15:41:58 -04:00
kDmaRequestMuxLPSPI3Rx, kDmaRequestMuxLPSPI4Rx }
mimxrt/machine_spi: Add the SPI class to the machine module. This class supports SPI bus controller mode, with blocking transfers. SPI device numbers start at 0, to comply with the pinout of the Teensy boards. With the configured clock frequency the fastest baud rate is 33MHz. For messages longer 16 bytes DMA is used. The class uses the existing framework with extmod/machine_spi.c. Extended driver options: - drive=n with n being between 1 and 6 or PIN.POWER_1 to PIN.POWER_6. Since the pins used by the SPI are fixed, no Pin settings can be made. Thus the drive option is added allowing to control ringing and crosstalk on the connection. - gap_ns=nnnnn is the time between sent data items in a frame given in ns. Default is 2 clock cycles.
2021-06-09 04:47:18 -04:00
#define DMA_REQ_SRC_TX { 0, kDmaRequestMuxLPSPI1Tx, kDmaRequestMuxLPSPI2Tx, \
mimxrt: Rework flash configuration. - Moves definition of BOARD_FLASH_SIZE and other header files related to flash configuration into the Makefile. - Adds board specific clock_config.h. - Adds board.h, pin_mux.h, and peripherals.h as they are required by NXP MCU SDK in order to use our own clock_config.h. - Renames board specific FlexSPI configuration files. - Updates flash frequency of MIMXRT1020_EVK - Creates separated flash_config files for QSPI NOR and QSPI Hyper flash. - Unifies VFS start address to be @ 1M for 1010 and 1020 boards. - Unifies 1050EVK boards - Adds support to both NOR and HyperFlash on boards with both capabilities. - Adds automatic FlexRAM initialization to start-up code based on linker script and NXP HAL. - Applies code formatting to all files in mimxrt port. With this change the flash configuration is restructured and organized. This simplifies the configuration process and provides a better overview of each board's settings. With the integration of clock_config.h, board.h, pin_mux.h, and peripherals.h we gain better control of the settings and clock configurations. Furthermore the implementation of an explicit FlexRAM setup improves the system performance and allows for performance tuning. Signed-off-by: Philipp Ebensberger
2021-08-20 15:41:58 -04:00
kDmaRequestMuxLPSPI3Tx, kDmaRequestMuxLPSPI4Tx }
mimxrt/machine_i2c: Add hardware-based machine.I2C to machine module. It uses non-blocking transfer of data. Advantage over SoftI2C: - Higher data rate up to ~3 MHZ. - Full protocol support.
2021-06-19 16:09:40 -04:00
// Define mapping hardware I2C # to logical I2C #
// SDA/SCL HW-I2C Logical I2C
// 17/16 LPI2C3 -> 0
// 18/19 LPI2C1 -> 1
// 25/24 LPI2C4 -> 2
#define MICROPY_HW_I2C_INDEX { 1, 3, 4 }
#define IOMUX_TABLE_I2C \
{ IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL }, { IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA }, \
{ 0 }, { 0 }, \
{ IOMUXC_GPIO_AD_B1_07_LPI2C3_SCL }, { IOMUXC_GPIO_AD_B1_06_LPI2C3_SDA }, \
{ IOMUXC_GPIO_AD_B0_12_LPI2C4_SCL }, { IOMUXC_GPIO_AD_B0_13_LPI2C4_SDA },
mimxrt/sdcard: Implement SDCard driver. - Configures `PLL2->PFD0` with **198MHz** as base clock of `USDHCx` peripheral. - Adds guards for SDCard related files via `MICROPY_PY_MACHINE_SDCARD` - Adds creation of pin defines for SDCard to make-pins.py - Adds new configuration option for SDCard peripheral pinout to mpconfigport.h - Adds interrupt handling support instead of polling - Adds support for `ADMA2` powered data transfer - Configures SDCard to run in HS (high-speed mode) with **50MHz** only! SDCard support is optional and requires `USDHC` peripheral. Thus this driver is not available on `MIMXRT1010_EVK`. SDCard support is enabled by setting `MICROPY_PY_MACHINE_SDCARD = 1` in mpconfigboard.mk. Signed-off-by: Philipp Ebensberger
2021-08-01 05:20:39 -04:00
mixmrt/machine_i2s: Add I2S protocol support. This commit adds support for machine.I2S on the mimxrt port. The I2S API is consistent with the existing stm32, esp32, and rp2 implementations. I2S features: - controller transmit and controller receive - 16-bit and 32-bit sample sizes - mono and stereo formats - sampling frequencies from 8kHz to 48kHz - 3 modes of operation: - blocking - non-blocking with callback - uasyncio - configurable internal buffer - optional MCK Tested with the following development boards: - MIMXRT1010_EVK, MIMXRT1015_EVK, MIMXRT1020_EVK, MIMXRT1050_EVK - Teensy 4.0, Teensy 4.1 - Olimex RT1010 - Seeed ARCH MIX Tested with the following I2S hardware peripherals: - UDA1334 - GY-SPH0645LM4H - WM8960 codec on board the MIMXRT boards and separate breakout board - INMP441 - PCM5102 - SGTL5000 on the Teensy audio shield Signed-off-by: Mike Teachman <mike.teachman@gmail.com>
2021-11-29 12:50:34 -05:00
#define MICROPY_PY_MACHINE_I2S (1)
#define MICROPY_HW_I2S_NUM (2)
#define I2S_CLOCK_MUX { 0, kCLOCK_Sai1Mux, kCLOCK_Sai2Mux }
#define I2S_CLOCK_PRE_DIV { 0, kCLOCK_Sai1PreDiv, kCLOCK_Sai2PreDiv }
#define I2S_CLOCK_DIV { 0, kCLOCK_Sai1Div, kCLOCK_Sai2Div }
#define I2S_IOMUXC_GPR_MODE { 0, kIOMUXC_GPR_SAI1MClkOutputDir, kIOMUXC_GPR_SAI2MClkOutputDir }
#define I2S_DMA_REQ_SRC_RX { 0, kDmaRequestMuxSai1Rx, kDmaRequestMuxSai2Rx }
#define I2S_DMA_REQ_SRC_TX { 0, kDmaRequestMuxSai1Tx, kDmaRequestMuxSai2Tx }
mimxrt: Add support for MIMXRT1176 MCUs, and MIMXRT1170_EVK board. The RT1176 has two cores, but the actual firmware supports only the CM7. There are currently no good plans on how to use the CM4. The actual MIMXRT1170_EVK board is on par with the existing MIMXRT boards, with the following extensions: - Use 64 MB RAM for the heap. - Support both LAN interfaces as LAN(0) and LAN(1), with LAN(1) being the 1GB interface. The dual LAN port interface can eventually be adapted as well for the RT1062 MCU. This work was done in collaboration with @alphaFred.
2021-10-20 15:24:20 -04:00
#define I2S_AUDIO_PLL_CLOCK (2U)
mixmrt/machine_i2s: Add I2S protocol support. This commit adds support for machine.I2S on the mimxrt port. The I2S API is consistent with the existing stm32, esp32, and rp2 implementations. I2S features: - controller transmit and controller receive - 16-bit and 32-bit sample sizes - mono and stereo formats - sampling frequencies from 8kHz to 48kHz - 3 modes of operation: - blocking - non-blocking with callback - uasyncio - configurable internal buffer - optional MCK Tested with the following development boards: - MIMXRT1010_EVK, MIMXRT1015_EVK, MIMXRT1020_EVK, MIMXRT1050_EVK - Teensy 4.0, Teensy 4.1 - Olimex RT1010 - Seeed ARCH MIX Tested with the following I2S hardware peripherals: - UDA1334 - GY-SPH0645LM4H - WM8960 codec on board the MIMXRT boards and separate breakout board - INMP441 - PCM5102 - SGTL5000 on the Teensy audio shield Signed-off-by: Mike Teachman <mike.teachman@gmail.com>
2021-11-29 12:50:34 -05:00
#define I2S_GPIO(_hwid, _fn, _mode, _pin, _iomux) \
{ \
.hw_id = _hwid, \
.fn = _fn, \
.mode = _mode, \
.name = MP_QSTR_##_pin, \
.iomux = {_iomux}, \
}
#define I2S_GPIO_MAP \
{ \
I2S_GPIO(1, SCK, RX, GPIO_AD_B1_11, IOMUXC_GPIO_AD_B1_11_SAI1_RX_BCLK), /* pin 21 */ \
I2S_GPIO(1, WS, RX, GPIO_AD_B1_10, IOMUXC_GPIO_AD_B1_10_SAI1_RX_SYNC), /* pin 20 */ \
I2S_GPIO(1, SD, RX, GPIO_AD_B1_12, IOMUXC_GPIO_AD_B1_12_SAI1_RX_DATA00), /* pin 38 */ \
I2S_GPIO(1, SD, RX, GPIO_B1_00, IOMUXC_GPIO_B1_00_SAI1_RX_DATA00), /* pin 8 */ \
I2S_GPIO(1, SCK, TX, GPIO_AD_B1_14, IOMUXC_GPIO_AD_B1_14_SAI1_TX_BCLK), /* pin 26 */ \
I2S_GPIO(1, SCK, TX, GPIO_B1_02, IOMUXC_GPIO_B1_02_SAI1_TX_BCLK), /* pin 36 */ \
I2S_GPIO(1, WS, TX, GPIO_AD_B1_15, IOMUXC_GPIO_AD_B1_15_SAI1_TX_SYNC), /* pin 27 */ \
I2S_GPIO(1, WS, TX, GPIO_B1_03, IOMUXC_GPIO_B1_03_SAI1_TX_SYNC), /* pin 37 */ \
I2S_GPIO(1, SD, TX, GPIO_AD_B1_13, IOMUXC_GPIO_AD_B1_13_SAI1_TX_DATA00), /* pin 39 */ \
I2S_GPIO(1, SD, TX, GPIO_B1_01, IOMUXC_GPIO_B1_01_SAI1_TX_DATA00), /* pin 7 */ \
I2S_GPIO(1, MCK, TX, GPIO_AD_B1_09, IOMUXC_GPIO_AD_B1_09_SAI1_MCLK), /* pin 23 */ \
I2S_GPIO(2, SCK, TX, GPIO_EMC_06, IOMUXC_GPIO_EMC_06_SAI2_TX_BCLK), /* pin 4 */ \
I2S_GPIO(2, WS, TX, GPIO_EMC_05, IOMUXC_GPIO_EMC_05_SAI2_TX_SYNC), /* pin 3 */ \
I2S_GPIO(2, SD, TX, GPIO_EMC_04, IOMUXC_GPIO_EMC_04_SAI2_TX_DATA), /* pin 2 */ \
I2S_GPIO(2, MCK, TX, GPIO_EMC_07, IOMUXC_GPIO_EMC_07_SAI2_MCLK) /* pin 33 */ \
}
mimxrt/sdcard: Implement SDCard driver. - Configures `PLL2->PFD0` with **198MHz** as base clock of `USDHCx` peripheral. - Adds guards for SDCard related files via `MICROPY_PY_MACHINE_SDCARD` - Adds creation of pin defines for SDCard to make-pins.py - Adds new configuration option for SDCard peripheral pinout to mpconfigport.h - Adds interrupt handling support instead of polling - Adds support for `ADMA2` powered data transfer - Configures SDCard to run in HS (high-speed mode) with **50MHz** only! SDCard support is optional and requires `USDHC` peripheral. Thus this driver is not available on `MIMXRT1010_EVK`. SDCard support is enabled by setting `MICROPY_PY_MACHINE_SDCARD = 1` in mpconfigboard.mk. Signed-off-by: Philipp Ebensberger
2021-08-01 05:20:39 -04:00
#define USDHC_DUMMY_PIN NULL, 0
#define MICROPY_USDHC1 \
{ \
.cmd = {GPIO_SD_B0_00_USDHC1_CMD}, \
.clk = { GPIO_SD_B0_01_USDHC1_CLK }, \
mimxrt: Rework flash configuration. - Moves definition of BOARD_FLASH_SIZE and other header files related to flash configuration into the Makefile. - Adds board specific clock_config.h. - Adds board.h, pin_mux.h, and peripherals.h as they are required by NXP MCU SDK in order to use our own clock_config.h. - Renames board specific FlexSPI configuration files. - Updates flash frequency of MIMXRT1020_EVK - Creates separated flash_config files for QSPI NOR and QSPI Hyper flash. - Unifies VFS start address to be @ 1M for 1010 and 1020 boards. - Unifies 1050EVK boards - Adds support to both NOR and HyperFlash on boards with both capabilities. - Adds automatic FlexRAM initialization to start-up code based on linker script and NXP HAL. - Applies code formatting to all files in mimxrt port. With this change the flash configuration is restructured and organized. This simplifies the configuration process and provides a better overview of each board's settings. With the integration of clock_config.h, board.h, pin_mux.h, and peripherals.h we gain better control of the settings and clock configurations. Furthermore the implementation of an explicit FlexRAM setup improves the system performance and allows for performance tuning. Signed-off-by: Philipp Ebensberger
2021-08-20 15:41:58 -04:00
.cd_b = { USDHC_DUMMY_PIN }, \
.data0 = { GPIO_SD_B0_02_USDHC1_DATA0 }, \
.data1 = { GPIO_SD_B0_03_USDHC1_DATA1 }, \
.data2 = { GPIO_SD_B0_04_USDHC1_DATA2 }, \
.data3 = { GPIO_SD_B0_05_USDHC1_DATA3 }, \
mimxrt/sdcard: Implement SDCard driver. - Configures `PLL2->PFD0` with **198MHz** as base clock of `USDHCx` peripheral. - Adds guards for SDCard related files via `MICROPY_PY_MACHINE_SDCARD` - Adds creation of pin defines for SDCard to make-pins.py - Adds new configuration option for SDCard peripheral pinout to mpconfigport.h - Adds interrupt handling support instead of polling - Adds support for `ADMA2` powered data transfer - Configures SDCard to run in HS (high-speed mode) with **50MHz** only! SDCard support is optional and requires `USDHC` peripheral. Thus this driver is not available on `MIMXRT1010_EVK`. SDCard support is enabled by setting `MICROPY_PY_MACHINE_SDCARD = 1` in mpconfigboard.mk. Signed-off-by: Philipp Ebensberger
2021-08-01 05:20:39 -04:00
}
mimxrt/eth: Add LAN support and integrate the network module. This commit implements 10/100 Mbit Ethernet support in the mimxrt port. The following boards are configured without ETH network: - MIMXRT1010_EVK - Teensy 4.0 The following boards are configured with ETH network: - MIMXRT1020_EVK - MIMXRT1050_EVK - MIMXRT1060_EVK - MIMXRT1064_EVK - Teensy 4.1 Ethernet support tested with TEENSY 4.1, MIMRTX1020_EVK and MIMXRT1050_EVK. Build tested with Teensy 4.0 and MIMXRT1010_EVK to be still working. Compiles and builds properly for MIMXRT1060_EVK and MIMXRT1064_EVK, but not tested lacking suitable boards. Tested functions are: - ping works bothway - simple UDP transfer works bothway - ntptime works - the ftp server works - secure socker works - telnet and webrepl works The MAC address is 0x02 plus 5 bytes from the manifacturing info field, which can be considered as unique per device. Some boards do not wire the RESET and INT pin of the PHY transceiver. For operation, these are not required. If they are defined, they will be used.
2021-07-03 12:39:17 -04:00
// Network definitions
// Transceiver Phy Address & Type
#define ENET_PHY_ADDRESS (0)
#define ENET_PHY_OPS phydp83825_ops
// Ethernet PIN definitions
mimxrt: Add support for MIMXRT1176 MCUs, and MIMXRT1170_EVK board. The RT1176 has two cores, but the actual firmware supports only the CM7. There are currently no good plans on how to use the CM4. The actual MIMXRT1170_EVK board is on par with the existing MIMXRT boards, with the following extensions: - Use 64 MB RAM for the heap. - Support both LAN interfaces as LAN(0) and LAN(1), with LAN(1) being the 1GB interface. The dual LAN port interface can eventually be adapted as well for the RT1062 MCU. This work was done in collaboration with @alphaFred.
2021-10-20 15:24:20 -04:00
#define ENET_RESET_PIN &pin_GPIO_B0_14
#define ENET_INT_PIN &pin_GPIO_B0_15
mimxrt/eth: Add LAN support and integrate the network module. This commit implements 10/100 Mbit Ethernet support in the mimxrt port. The following boards are configured without ETH network: - MIMXRT1010_EVK - Teensy 4.0 The following boards are configured with ETH network: - MIMXRT1020_EVK - MIMXRT1050_EVK - MIMXRT1060_EVK - MIMXRT1064_EVK - Teensy 4.1 Ethernet support tested with TEENSY 4.1, MIMRTX1020_EVK and MIMXRT1050_EVK. Build tested with Teensy 4.0 and MIMXRT1010_EVK to be still working. Compiles and builds properly for MIMXRT1060_EVK and MIMXRT1064_EVK, but not tested lacking suitable boards. Tested functions are: - ping works bothway - simple UDP transfer works bothway - ntptime works - the ftp server works - secure socker works - telnet and webrepl works The MAC address is 0x02 plus 5 bytes from the manifacturing info field, which can be considered as unique per device. Some boards do not wire the RESET and INT pin of the PHY transceiver. For operation, these are not required. If they are defined, they will be used.
2021-07-03 12:39:17 -04:00
#define IOMUX_TABLE_ENET \
{ IOMUXC_GPIO_B1_04_ENET_RX_DATA00, 0, 0xB0E9u }, \
{ IOMUXC_GPIO_B1_05_ENET_RX_DATA01, 0, 0xB0E9u }, \
{ IOMUXC_GPIO_B1_06_ENET_RX_EN, 0, 0xB0E9u }, \
{ IOMUXC_GPIO_B1_07_ENET_TX_DATA00, 0, 0xB0E9u }, \
{ IOMUXC_GPIO_B1_08_ENET_TX_DATA01, 0, 0xB0E9u }, \
{ IOMUXC_GPIO_B1_09_ENET_TX_EN, 0, 0xB0E9u }, \
{ IOMUXC_GPIO_B1_10_ENET_REF_CLK, 1, 0x71u }, \
{ IOMUXC_GPIO_B1_11_ENET_RX_ER, 0, 0xB0E9u }, \
{ IOMUXC_GPIO_B1_15_ENET_MDIO, 0, 0xB0E9u }, \
{ IOMUXC_GPIO_B1_14_ENET_MDC, 0, 0xB0E9u },
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