circuitpython/ports/mimxrt10xx/supervisor/port.c

/*
 * This file is part of the MicroPython project, http://micropython.org/
 *
 * The MIT License (MIT)
 *
 * Copyright (c) 2020 Scott Shawcroft for Adafruit Industries
 * Copyright (c) 2020 Artur Pacholec
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
/*
 * Copyright 2018 NXP
 * All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */

#include "boards/board.h"
#include "supervisor/port.h"

#include "fsl_device_registers.h"

#include "common-hal/microcontroller/Pin.h"
#include "common-hal/pulseio/PulseIn.h"
#include "common-hal/pulseio/PulseOut.h"
#include "common-hal/pulseio/PWMOut.h"
#include "common-hal/rtc/RTC.h"

#include "reset.h"
#include "tick.h"

#include "tusb.h"

#if CIRCUITPY_GAMEPAD
#include "shared-module/gamepad/__init__.h"
#endif
#if CIRCUITPY_GAMEPADSHIFT
#include "shared-module/gamepadshift/__init__.h"
#endif
#include "shared-module/_pew/PewPew.h"

#include "clocks.h"

#include "fsl_gpio.h"
#include "fsl_lpuart.h"

// Device memories must be accessed in order.
#define DEVICE 2
// Normal memory can have accesses reorder and prefetched.
#define NORMAL 0

// Prevents instruction access.
#define NO_EXECUTION 1
#define EXECUTION 0

// Shareable if the memory system manages coherency.
#define NOT_SHAREABLE 0
#define SHAREABLE 1

//
#define NOT_CACHEABLE 0
#define CACHEABLE 1

#define NOT_BUFFERABLE 0
#define BUFFERABLE 1

#define NO_SUBREGIONS 0

extern uint32_t _ld_flash_size;

extern uint8_t _ld_dtcm_bss_start;
extern uint8_t _ld_dtcm_bss_end;
extern uint8_t _ld_dtcm_data_destination;
extern uint8_t _ld_dtcm_data_size;
extern uint8_t _ld_dtcm_data_flash_copy;
extern uint8_t _ld_itcm_destination;
extern uint8_t _ld_itcm_size;
extern uint8_t _ld_itcm_flash_copy;

// This is called before RAM is setup! Be very careful what you do here.
void SystemInitHook(void) {
    // asm("bkpt");
    /* Disable I cache and D cache */
    if (SCB_CCR_IC_Msk == (SCB_CCR_IC_Msk & SCB->CCR))
    {
        SCB_DisableICache();
    }
    if (SCB_CCR_DC_Msk == (SCB_CCR_DC_Msk & SCB->CCR))
    {
        SCB_DisableDCache();
    }
    // Configure FlexRAM. The e is one block of ITCM (0b11) and DTCM (0b10). The rest is two OCRAM
    // (0b01). We shift in zeroes for all unimplemented banks.
    IOMUXC_GPR->GPR17 = (0xe5555555) >> (32 - 2 * FSL_FEATURE_FLEXRAM_INTERNAL_RAM_TOTAL_BANK_NUMBERS);

    // Switch from FlexRAM fuse config to the IOMUXC values.
    IOMUXC_GPR->GPR16 |= IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL(1);

    // Let the core know the TCM sizes changed.
    uint32_t current_gpr14 = IOMUXC_GPR->GPR14;
    current_gpr14 &= ~IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_MASK;
    current_gpr14 |= IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ(0x6);
    current_gpr14 &= ~IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_MASK;
    current_gpr14 |= IOMUXC_GPR_GPR14_CM7_CFGITCMSZ(0x6);
    IOMUXC_GPR->GPR14 = current_gpr14;

    /* Disable MPU */
    ARM_MPU_Disable();

    // Copy all of the code to run from ITCM.
    memcpy(&_ld_itcm_destination, &_ld_itcm_flash_copy, (size_t) &_ld_itcm_size);

    // Copy all of the data to run from DTCM.
    memcpy(&_ld_dtcm_data_destination, &_ld_dtcm_data_flash_copy, (size_t) &_ld_dtcm_data_size);

    // Clear DTCM bss.
    memset(&_ld_dtcm_bss_start, 0, (size_t) (&_ld_dtcm_bss_end - &_ld_dtcm_bss_start));

    // The first number in RBAR is the region number. When searching for a policy, the region with
    // the highest number wins. If none match, then the default policy set at enable applies.

    // This is an undocumented region and is likely more registers.
    MPU->RBAR = ARM_MPU_RBAR(8, 0xC0000000U);
    MPU->RASR = ARM_MPU_RASR(EXECUTION, ARM_MPU_AP_FULL, DEVICE, NOT_SHAREABLE, NOT_CACHEABLE, NOT_BUFFERABLE, NO_SUBREGIONS, ARM_MPU_REGION_SIZE_512MB);

    // This is the SEMC region where external RAM and 8+ flash would live. Disable for now, even though the EVKs have stuff here.
    MPU->RBAR = ARM_MPU_RBAR(9, 0x80000000U);
    MPU->RASR = ARM_MPU_RASR(NO_EXECUTION, ARM_MPU_AP_NONE, DEVICE, NOT_SHAREABLE, NOT_CACHEABLE, NOT_BUFFERABLE, NO_SUBREGIONS, ARM_MPU_REGION_SIZE_1GB);

    // FlexSPI2 is 0x70000000

    // This the first 1MB of flash is the bootloader and CircuitPython read-only data.
    MPU->RBAR = ARM_MPU_RBAR(10, 0x60000000U);
    MPU->RASR = ARM_MPU_RASR(EXECUTION, ARM_MPU_AP_FULL, NORMAL, NOT_SHAREABLE, CACHEABLE, BUFFERABLE, NO_SUBREGIONS, ARM_MPU_REGION_SIZE_1MB);

    // The remainder of flash is the fat filesystem which could have code on it too. Make sure that
    // we set the region to the minimal size so that bad data doesn't get speculatively fetched.
    // Thanks to Damien for the tip!
    uint32_t region_size = ARM_MPU_REGION_SIZE_32B;
    uint32_t filesystem_size = &_ld_filesystem_end - &_ld_filesystem_start;
    while (filesystem_size > (1u << (region_size + 1))) {
        region_size += 1;
    }
    // Mask out as much of the remainder as we can. For example on an 8MB flash, 7MB are for the
    // filesystem. The region_size here must be a power of 2 so it is 8MB. Using the subregion mask
    // we can ignore 1/8th size chunks. So, we ignore the last 1MB using the subregion.
    uint32_t remainder = (1u << (region_size + 1)) - filesystem_size;
    uint32_t subregion_size = (1u << (region_size + 1)) / 8;
    uint16_t subregion_mask = 0xff00 >> (remainder / subregion_size);

    MPU->RBAR = ARM_MPU_RBAR(11, 0x60100000U);
    MPU->RASR = ARM_MPU_RASR(EXECUTION, ARM_MPU_AP_FULL, NORMAL, NOT_SHAREABLE, CACHEABLE, BUFFERABLE, (uint8_t) subregion_mask, region_size);

    // This the ITCM. Set it to read-only because we've loaded everything already and it's easy to
    // accidentally write the wrong value to 0x00000000 (aka NULL).
    MPU->RBAR = ARM_MPU_RBAR(12, 0x00000000U);
    MPU->RASR = ARM_MPU_RASR(EXECUTION, ARM_MPU_AP_RO, NORMAL, NOT_SHAREABLE, CACHEABLE, BUFFERABLE, NO_SUBREGIONS, ARM_MPU_REGION_SIZE_32KB);

    // This the DTCM.
    MPU->RBAR = ARM_MPU_RBAR(13, 0x20000000U);
    MPU->RASR = ARM_MPU_RASR(EXECUTION, ARM_MPU_AP_FULL, NORMAL, NOT_SHAREABLE, CACHEABLE, BUFFERABLE, NO_SUBREGIONS, ARM_MPU_REGION_SIZE_32KB);

    // This is OCRAM.
    MPU->RBAR = ARM_MPU_RBAR(14, 0x20200000U);
    MPU->RASR = ARM_MPU_RASR(EXECUTION, ARM_MPU_AP_FULL, NORMAL, NOT_SHAREABLE, CACHEABLE, BUFFERABLE, NO_SUBREGIONS, ARM_MPU_REGION_SIZE_512KB);

    // We steal 64k from FlexRAM for ITCM and DTCM so disable those memory regions here.
    MPU->RBAR = ARM_MPU_RBAR(15, 0x20280000U);
    MPU->RASR = ARM_MPU_RASR(EXECUTION, ARM_MPU_AP_FULL, NORMAL, NOT_SHAREABLE, CACHEABLE, BUFFERABLE, 0x80, ARM_MPU_REGION_SIZE_512KB);

    /* Enable MPU */
    ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk);

    /* Enable I cache and D cache */
    SCB_EnableDCache();
    SCB_EnableICache();
}

safe_mode_t port_init(void) {
    clocks_init();

    // Configure millisecond timer initialization.
    tick_init();

#if CIRCUITPY_RTC
    rtc_init();
#endif

    // Reset everything into a known state before board_init.
    reset_port();

    // Init the board last so everything else is ready
    board_init();

    if (board_requests_safe_mode()) {
        return USER_SAFE_MODE;
    }

    return NO_SAFE_MODE;
}

void reset_port(void) {
    //reset_sercoms();

#if CIRCUITPY_AUDIOIO
    audio_dma_reset();
    audioout_reset();
#endif
#if CIRCUITPY_AUDIOBUSIO
    i2sout_reset();
    //pdmin_reset();
#endif

#if CIRCUITPY_TOUCHIO && CIRCUITPY_TOUCHIO_USE_NATIVE
    touchin_reset();
#endif

//    eic_reset();

#if CIRCUITPY_PULSEIO
    pulseout_reset();
    pwmout_reset();
#endif

#if CIRCUITPY_RTC
    rtc_reset();
#endif

#if CIRCUITPY_GAMEPAD
    gamepad_reset();
#endif
#if CIRCUITPY_GAMEPADSHIFT
    gamepadshift_reset();
#endif
#if CIRCUITPY_PEW
    pew_reset();
#endif

    //reset_event_system();

    reset_all_pins();
}

void reset_to_bootloader(void) {
    SNVS->LPGPR[0] = DBL_TAP_MAGIC;
    reset();
}

void reset_cpu(void) {
    reset();
}

extern uint32_t _ld_heap_start, _ld_heap_end, _ld_stack_top, _ld_stack_bottom;
uint32_t *port_stack_get_limit(void) {
    return &_ld_heap_start;
}

uint32_t *port_stack_get_top(void) {
    return &_ld_stack_top;
}

uint32_t *port_heap_get_bottom(void) {
    return &_ld_heap_start;
}

// Get heap top address
uint32_t *port_heap_get_top(void) {
    return &_ld_heap_end;
}

// Place the word to save just after our BSS section that gets blanked.
void port_set_saved_word(uint32_t value) {
    SNVS->LPGPR[1] = value;
}

uint32_t port_get_saved_word(void) {
    return SNVS->LPGPR[1];
}

/**
 * \brief Default interrupt handler for unused IRQs.
 */
__attribute__((used)) void MemManage_Handler(void)
{
    reset_into_safe_mode(MEM_MANAGE);
    while (true) {
        asm("nop;");
    }
}

/**
 * \brief Default interrupt handler for unused IRQs.
 */
__attribute__((used)) void BusFault_Handler(void)
{
    reset_into_safe_mode(MEM_MANAGE);
    while (true) {
        asm("nop;");
    }
}

/**
 * \brief Default interrupt handler for unused IRQs.
 */
__attribute__((used)) void UsageFault_Handler(void)
{
    reset_into_safe_mode(MEM_MANAGE);
    while (true) {
        asm("nop;");
    }
}

/**
 * \brief Default interrupt handler for unused IRQs.
 */
__attribute__((used)) void HardFault_Handler(void)
{
    reset_into_safe_mode(HARD_CRASH);
    while (true) {
        asm("nop;");
    }
}