2020-01-08 23:32:45 -05:00
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/*
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* Copyright 2017 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include "fsl_flexspi_nor_boot.h"
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#include "fsl_flexspi_nor_config.h"
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__attribute__((section(".boot_hdr.ivt")))
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/*************************************
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* IVT Data
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*************************************/
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const ivt image_vector_table = {
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IVT_HEADER, /* IVT Header */
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IMAGE_ENTRY_ADDRESS, /* Image Entry Function */
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IVT_RSVD, /* Reserved = 0 */
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(uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */
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(uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */
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(uint32_t)&image_vector_table, /* Pointer to IVT Self (absolute address */
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(uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */
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IVT_RSVD /* Reserved = 0 */
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};
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__attribute__((section(".boot_hdr.boot_data")))
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/*************************************
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* Boot Data
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*************************************/
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const BOOT_DATA_T boot_data = {
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FLASH_BASE, /* boot start location */
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FLASH_SIZE, /* size */
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PLUGIN_FLAG, /* Plugin flag*/
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0xFFFFFFFF /* empty - extra data word */
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};
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__attribute__((section(".boot_hdr.conf")))
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// Values copied from https://github.com/PaulStoffregen/cores/blob/ddb23fa5d97dac763bc06e11b9b41f026bd51f0a/teensy4/bootdata.c#L39
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const flexspi_nor_config_t qspiflash_config = {
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.memConfig =
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{
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.tag = FLEXSPI_CFG_BLK_TAG,
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.version = FLEXSPI_CFG_BLK_VERSION,
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2020-02-18 10:21:49 -05:00
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#ifdef BOARD_USING_SECONDARY_QSPI_PINMUX
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.readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromInternally,
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#else
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2020-05-30 05:44:13 -04:00
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.readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad,
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2020-02-18 10:21:49 -05:00
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#endif
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2020-01-08 23:32:45 -05:00
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.csHoldTime = 1u,
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.csSetupTime = 2u,
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// Enable DDR mode, Wordaddressable, Safe configuration, Differential clock
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.deviceType = kFlexSpiDeviceType_SerialNOR,
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.sflashPadType = kSerialFlash_4Pads,
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.serialClkFreq = kFlexSpiSerialClk_60MHz, // 03
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.sflashA1Size = FLASH_SIZE,
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.lookupTable =
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{
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// FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1)
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// (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) |
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// FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
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// Read LUTs
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FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18),
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FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04),
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0,
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0,
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0x24040405,
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0,
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0,
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0,
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0,
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0,
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0,
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0,
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0x00000406,
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0,
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0,
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0,
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0,
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0,
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0,
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0,
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0x08180420,
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0,
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0,
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0,
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0,
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0,
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0,
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0,
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0,
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0,
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0,
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0,
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0x081804D8,
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0,
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0,
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0,
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0x08180402,
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0x00002004,
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0,
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0,
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0,
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0,
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0,
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0,
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0x00000460,
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},
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},
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.pageSize = 256u,
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.sectorSize = 4u * 1024u,
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.ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz,
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.blockSize = 0x00010000,
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.isUniformBlockSize = false,
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};
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