2017-05-24 13:43:32 -04:00
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/*
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2017-08-27 15:02:50 -04:00
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* This file is part of the MicroPython project, http://micropython.org/
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2017-05-24 13:43:32 -04:00
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2017 Scott Shawcroft for Adafruit Industries
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include <stdint.h>
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#include <string.h>
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2018-01-02 21:25:41 -05:00
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#include <math.h>
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2017-05-24 13:43:32 -04:00
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#include "py/gc.h"
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#include "py/mperrno.h"
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#include "py/runtime.h"
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#include "common-hal/analogio/AnalogOut.h"
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#include "common-hal/audiobusio/PDMIn.h"
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#include "shared-bindings/analogio/AnalogOut.h"
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#include "shared-bindings/audiobusio/PDMIn.h"
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2021-10-15 09:39:13 -04:00
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#include "shared-bindings/microcontroller/__init__.h"
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2017-05-24 13:43:32 -04:00
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#include "shared-bindings/microcontroller/Pin.h"
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2018-07-31 19:53:54 -04:00
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#include "supervisor/shared/translate.h"
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2017-05-24 13:43:32 -04:00
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2018-04-26 15:51:37 -04:00
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#include "atmel_start_pins.h"
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#include "hal/include/hal_gpio.h"
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#include "hal/utils/include/utils.h"
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2018-06-15 19:16:21 -04:00
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#include "samd/clocks.h"
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#include "samd/events.h"
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#include "samd/i2s.h"
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#include "samd/pins.h"
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#include "samd/dma.h"
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2018-05-25 21:39:16 -04:00
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2018-04-26 15:51:37 -04:00
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#include "audio_dma.h"
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2017-05-24 13:43:32 -04:00
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2018-01-02 21:25:41 -05:00
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#define OVERSAMPLING 64
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#define SAMPLES_PER_BUFFER 32
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// MEMS microphones must be clocked at at least 1MHz.
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#define MIN_MIC_CLOCK 1000000
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2018-04-26 15:51:37 -04:00
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#ifdef SAMD21
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#define SERCTRL(name) I2S_SERCTRL_ ## name
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#endif
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#ifdef SAM_D5X_E5X
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#define SERCTRL(name) I2S_RXCTRL_ ## name
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#endif
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2021-10-15 09:39:13 -04:00
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// Set by interrupt handler when DMA block has finished transferring.
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static bool pdmin_dma_block_done;
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// Event channel used to trigger interrupt. Set to invalid value EVSYS_SYNCH_NUM when not in use.
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static uint8_t pdmin_event_channel;
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void pdmin_evsys_handler(void) {
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if (pdmin_event_channel < EVSYS_SYNCH_NUM && event_interrupt_active(pdmin_event_channel)) {
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pdmin_dma_block_done = true;
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}
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}
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void pdmin_reset(void) {
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pdmin_event_channel = EVSYS_SYNCH_NUM;
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2017-05-24 13:43:32 -04:00
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while (I2S->SYNCBUSY.reg & I2S_SYNCBUSY_ENABLE) {}
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I2S->INTENCLR.reg = I2S_INTENCLR_MASK;
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I2S->INTFLAG.reg = I2S_INTFLAG_MASK;
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I2S->CTRLA.reg &= ~I2S_SYNCBUSY_ENABLE;
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while (I2S->SYNCBUSY.reg & I2S_SYNCBUSY_ENABLE) {}
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I2S->CTRLA.reg = I2S_CTRLA_SWRST;
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}
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2020-02-29 15:37:32 -05:00
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// Caller validates that pins are free.
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void common_hal_audiobusio_pdmin_construct(audiobusio_pdmin_obj_t* self,
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const mcu_pin_obj_t* clock_pin,
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const mcu_pin_obj_t* data_pin,
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2018-04-26 15:51:37 -04:00
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uint32_t sample_rate,
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uint8_t bit_depth,
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bool mono,
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uint8_t oversample) {
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self->clock_pin = clock_pin; // PA10, PA20 -> SCK0, PB11 -> SCK1
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#ifdef SAMD21
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if (clock_pin == &pin_PA10
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#if defined(PIN_PA20) && !defined(IGNORE_PIN_PA20)
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|| clock_pin == &pin_PA20
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#endif
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) {
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self->clock_unit = 0;
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2020-07-26 21:27:32 -04:00
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#if defined(PIN_PB11) && !defined(IGNORE_PIN_PB11)
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} else if (clock_pin == &pin_PB11) {
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self->clock_unit = 1;
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#endif
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#endif
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#ifdef SAM_D5X_E5X
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if (clock_pin == &pin_PA10 || clock_pin == &pin_PB16) {
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self->clock_unit = 0;
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} else if (clock_pin == &pin_PB12
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#if defined(PIN_PB28) && !defined(IGNORE_PIN_PB28)
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|| data_pin == &pin_PB28) {
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#else
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) {
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#endif
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self->clock_unit = 1;
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#endif
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} else {
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mp_raise_ValueError_varg(translate("Invalid %q pin"), MP_QSTR_clock);
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}
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self->data_pin = data_pin; // PA07, PA19 -> SD0, PA08, PB16 -> SD1
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#ifdef SAMD21
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if (false
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#if defined(PIN_PA07) && !defined(IGNORE_PIN_PA07)
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|| data_pin == &pin_PA07
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#endif
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#if defined(PIN_PA19) && !defined(IGNORE_PIN_PA19)
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|| data_pin == &pin_PA19
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#endif
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) {
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self->serializer = 0;
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}
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else if (false
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#if defined(PIN_PA08) && !defined(IGNORE_PIN_PA08)
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|| data_pin == &pin_PA08
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#endif
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#if defined (PIN_PB16) && !defined(IGNORE_PIN_PB16)
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|| data_pin == &pin_PB16
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#endif
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) {
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self->serializer = 1;
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#endif
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#ifdef SAM_D5X_E5X
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if (data_pin == &pin_PB10 || data_pin == &pin_PA22) {
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self->serializer = 1;
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#endif
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} else {
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mp_raise_ValueError_varg(translate("Invalid %q pin"), MP_QSTR_data);
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}
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2018-01-02 21:25:41 -05:00
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if (!(bit_depth == 16 || bit_depth == 8) || !mono || oversample != OVERSAMPLING) {
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2018-07-31 19:53:54 -04:00
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mp_raise_NotImplementedError(translate("Only 8 or 16 bit mono with " MP_STRINGIFY(OVERSAMPLING) "x oversampling is supported."));
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}
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2018-04-26 15:51:37 -04:00
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turn_on_i2s();
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2017-05-24 13:43:32 -04:00
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2018-04-26 15:51:37 -04:00
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if (I2S->CTRLA.bit.ENABLE == 0) {
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I2S->CTRLA.bit.SWRST = 1;
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while (I2S->CTRLA.bit.SWRST == 1) {}
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} else {
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#ifdef SAMD21
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if ((I2S->CTRLA.vec.SEREN & (1 << self->serializer)) != 0) {
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2018-07-31 19:53:54 -04:00
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mp_raise_RuntimeError(translate("Serializer in use"));
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2018-04-26 15:51:37 -04:00
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}
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#endif
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2020-06-18 15:13:59 -04:00
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#ifdef SAM_D5X_E5X
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2018-04-26 15:51:37 -04:00
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if (I2S->CTRLA.bit.RXEN == 1) {
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2018-07-31 19:53:54 -04:00
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mp_raise_RuntimeError(translate("Serializer in use"));
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2018-04-26 15:51:37 -04:00
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}
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#endif
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}
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2020-06-18 15:13:59 -04:00
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#ifdef SAM_D5X_E5X
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2018-04-26 15:51:37 -04:00
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#define GPIO_I2S_FUNCTION GPIO_PIN_FUNCTION_J
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#endif
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#ifdef SAMD21
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#define GPIO_I2S_FUNCTION GPIO_PIN_FUNCTION_G
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#endif
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uint32_t clock_divisor = (uint32_t) roundf( 48000000.0f / sample_rate / oversample);
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float mic_clock_freq = 48000000.0f / clock_divisor;
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self->sample_rate = mic_clock_freq / oversample;
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if (mic_clock_freq < MIN_MIC_CLOCK || clock_divisor == 0) {
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2018-07-31 19:53:54 -04:00
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mp_raise_ValueError(translate("sampling rate out of range"));
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2018-04-26 15:51:37 -04:00
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}
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// Find a free GCLK to generate the MCLK signal.
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uint8_t gclk = find_free_gclk(clock_divisor);
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if (gclk > GCLK_GEN_NUM) {
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2018-07-31 19:53:54 -04:00
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mp_raise_RuntimeError(translate("Unable to find free GCLK"));
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2018-04-26 15:51:37 -04:00
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}
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self->gclk = gclk;
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2017-05-24 13:43:32 -04:00
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2018-04-26 15:51:37 -04:00
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enable_clock_generator(self->gclk, CLOCK_48MHZ, clock_divisor);
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connect_gclk_to_peripheral(self->gclk, I2S_GCLK_ID_0 + self->clock_unit);
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2017-05-24 13:43:32 -04:00
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2018-04-26 15:51:37 -04:00
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// Clock unit configuration
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uint32_t clkctrl = I2S_CLKCTRL_MCKSEL_GCLK |
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I2S_CLKCTRL_NBSLOTS(2) |
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I2S_CLKCTRL_FSWIDTH_SLOT |
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I2S_CLKCTRL_SLOTSIZE_16;
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// Serializer configuration
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#ifdef SAMD21
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uint32_t serctrl = (self->clock_unit << I2S_SERCTRL_CLKSEL_Pos) | SERCTRL(SERMODE_PDM2) | SERCTRL(DATASIZE_32);
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#endif
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2020-06-18 15:13:59 -04:00
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#ifdef SAM_D5X_E5X
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2018-04-26 15:51:37 -04:00
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uint32_t serctrl = (self->clock_unit << I2S_RXCTRL_CLKSEL_Pos) | SERCTRL(SERMODE_PDM2) | SERCTRL(DATASIZE_32);
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#endif
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2017-05-24 13:43:32 -04:00
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2018-04-26 15:51:37 -04:00
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// Configure the I2S peripheral
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i2s_set_enable(false);
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I2S->CLKCTRL[self->clock_unit].reg = clkctrl;
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#ifdef SAMD21
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I2S->SERCTRL[self->serializer].reg = serctrl;
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#endif
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2020-06-18 15:13:59 -04:00
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#ifdef SAM_D5X_E5X
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2018-04-26 15:51:37 -04:00
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I2S->RXCTRL.reg = serctrl;
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#endif
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i2s_set_enable(true);
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2017-05-24 13:43:32 -04:00
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2018-06-12 12:35:51 -04:00
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// Run the clock all the time. This eliminates startup delay for the microphone,
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// which can be 10-100ms. Turn serializer on as needed.
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2018-04-26 15:51:37 -04:00
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i2s_set_clock_unit_enable(self->clock_unit, true);
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claim_pin(clock_pin);
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claim_pin(data_pin);
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2018-07-31 17:01:01 -04:00
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gpio_set_pin_function(self->clock_pin->number, GPIO_I2S_FUNCTION);
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gpio_set_pin_function(self->data_pin->number, GPIO_I2S_FUNCTION);
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2018-01-02 21:25:41 -05:00
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2017-05-24 13:43:32 -04:00
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self->bytes_per_sample = oversample >> 3;
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self->bit_depth = bit_depth;
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}
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2017-10-02 20:49:40 -04:00
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bool common_hal_audiobusio_pdmin_deinited(audiobusio_pdmin_obj_t* self) {
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2020-02-28 23:32:24 -05:00
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return self->clock_pin == NULL;
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2017-10-02 20:49:40 -04:00
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}
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2017-05-24 13:43:32 -04:00
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void common_hal_audiobusio_pdmin_deinit(audiobusio_pdmin_obj_t* self) {
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2017-10-02 20:49:40 -04:00
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if (common_hal_audiobusio_pdmin_deinited(self)) {
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return;
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}
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2018-04-26 15:51:37 -04:00
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i2s_set_serializer_enable(self->serializer, false);
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i2s_set_clock_unit_enable(self->clock_unit, false);
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i2s_set_enable(false);
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disconnect_gclk_from_peripheral(self->gclk, I2S_GCLK_ID_0 + self->clock_unit);
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disable_clock_generator(self->gclk);
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2018-08-31 17:46:03 -04:00
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reset_pin_number(self->clock_pin->number);
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reset_pin_number(self->data_pin->number);
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2020-02-28 23:32:24 -05:00
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self->clock_pin = NULL;
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self->data_pin = NULL;
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2017-05-24 13:43:32 -04:00
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}
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uint8_t common_hal_audiobusio_pdmin_get_bit_depth(audiobusio_pdmin_obj_t* self) {
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return self->bit_depth;
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}
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2018-04-26 15:51:37 -04:00
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uint32_t common_hal_audiobusio_pdmin_get_sample_rate(audiobusio_pdmin_obj_t* self) {
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return self->sample_rate;
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2017-05-24 13:43:32 -04:00
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}
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static void setup_dma(audiobusio_pdmin_obj_t* self, uint32_t length,
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2018-04-26 15:51:37 -04:00
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DmacDescriptor* descriptor,
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DmacDescriptor* second_descriptor,
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uint32_t words_per_buffer, uint8_t words_per_sample,
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uint32_t* first_buffer, uint32_t* second_buffer) {
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descriptor->BTCTRL.reg = DMAC_BTCTRL_VALID |
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DMAC_BTCTRL_BLOCKACT_NOACT |
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DMAC_BTCTRL_EVOSEL_BLOCK |
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DMAC_BTCTRL_DSTINC |
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DMAC_BTCTRL_BEATSIZE_WORD;
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2017-05-24 13:43:32 -04:00
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// Block transfer count is the number of beats per block (aka descriptor).
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// In this case there are two bytes per beat so divide the length by two.
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uint16_t block_transfer_count = words_per_buffer;
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if (length * words_per_sample < words_per_buffer) {
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block_transfer_count = length * words_per_sample;
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}
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2018-04-26 15:51:37 -04:00
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descriptor->BTCNT.reg = block_transfer_count;
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descriptor->DSTADDR.reg = ((uint32_t) first_buffer + sizeof(uint32_t) * block_transfer_count);
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descriptor->DESCADDR.reg = 0;
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2017-05-24 13:43:32 -04:00
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if (length * words_per_sample > words_per_buffer) {
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2018-04-26 15:51:37 -04:00
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descriptor->DESCADDR.reg = ((uint32_t)second_descriptor);
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2017-05-24 13:43:32 -04:00
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}
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2018-04-26 15:51:37 -04:00
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#ifdef SAMD21
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descriptor->SRCADDR.reg = (uint32_t)&I2S->DATA[self->serializer];
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#endif
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2020-06-18 15:13:59 -04:00
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#ifdef SAM_D5X_E5X
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2018-04-26 15:51:37 -04:00
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descriptor->SRCADDR.reg = (uint32_t)&I2S->RXDATA;
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#endif
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2017-05-24 13:43:32 -04:00
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2018-01-02 21:25:41 -05:00
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// Do we need more values than will fit in the first buffer?
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// If so, set up a second buffer chained to be filled after the first buffer.
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2017-05-24 13:43:32 -04:00
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if (length * words_per_sample > words_per_buffer) {
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block_transfer_count = words_per_buffer;
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2018-04-26 15:51:37 -04:00
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second_descriptor->DESCADDR.reg = ((uint32_t)descriptor);
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2017-05-24 13:43:32 -04:00
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if (length * words_per_sample < 2 * words_per_buffer) {
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2018-01-02 21:25:41 -05:00
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// Length needed is more than one buffer but less than two.
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// Subtract off the size of the first buffer, and what remains is the count we need.
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block_transfer_count = length * words_per_sample - words_per_buffer;
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2018-04-26 15:51:37 -04:00
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second_descriptor->DESCADDR.reg = 0;
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2017-05-24 13:43:32 -04:00
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}
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2018-04-26 15:51:37 -04:00
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second_descriptor->DSTADDR.reg = ((uint32_t) second_buffer + sizeof(uint32_t) * block_transfer_count);
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2017-05-24 13:43:32 -04:00
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2018-04-26 15:51:37 -04:00
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second_descriptor->BTCNT.reg = block_transfer_count;
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#ifdef SAMD21
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second_descriptor->SRCADDR.reg = (uint32_t)&I2S->DATA[self->serializer];
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#endif
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2020-06-18 15:13:59 -04:00
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#ifdef SAM_D5X_E5X
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2018-04-26 15:51:37 -04:00
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second_descriptor->SRCADDR.reg = (uint32_t)&I2S->RXDATA;
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#endif
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second_descriptor->BTCTRL.reg = DMAC_BTCTRL_VALID |
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DMAC_BTCTRL_BLOCKACT_NOACT |
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DMAC_BTCTRL_EVOSEL_BLOCK |
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DMAC_BTCTRL_DSTINC |
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DMAC_BTCTRL_BEATSIZE_WORD;
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}
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2017-05-24 13:43:32 -04:00
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}
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2018-01-02 21:25:41 -05:00
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// a windowed sinc filter for 44 khz, 64 samples
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//
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// This filter is good enough to use for lower sample rates as
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// well. It does not increase the noise enough to be a problem.
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//
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// In the long run we could use a fast filter like this to do the
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// decimation and initial filtering in real time, filtering to a
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// higher sample rate than specified. Then after the audio is
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// recorded, a more expensive filter non-real-time filter could be
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// used to down-sample and low-pass.
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2020-11-13 21:33:02 -05:00
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const uint16_t sinc_filter [OVERSAMPLING] = {
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2018-01-02 21:25:41 -05:00
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0, 2, 9, 21, 39, 63, 94, 132,
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179, 236, 302, 379, 467, 565, 674, 792,
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920, 1055, 1196, 1341, 1487, 1633, 1776, 1913,
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2042, 2159, 2263, 2352, 2422, 2474, 2506, 2516,
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2506, 2474, 2422, 2352, 2263, 2159, 2042, 1913,
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1776, 1633, 1487, 1341, 1196, 1055, 920, 792,
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674, 565, 467, 379, 302, 236, 179, 132,
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94, 63, 39, 21, 9, 2, 0, 0
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2017-05-24 13:43:32 -04:00
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};
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2020-11-19 17:19:37 -05:00
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#ifdef SAMD21
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#define REPEAT_16_TIMES(X) do { for(uint8_t j=0; j<4; j++) { X X X X } } while (0)
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#else
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#define REPEAT_16_TIMES(X) do { X X X X X X X X X X X X X X X X } while(0)
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#endif
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2018-01-02 21:25:41 -05:00
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2017-05-24 13:43:32 -04:00
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static uint16_t filter_sample(uint32_t pdm_samples[4]) {
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2018-01-02 21:25:41 -05:00
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uint16_t running_sum = 0;
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const uint16_t *filter_ptr = sinc_filter;
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for (uint8_t i = 0; i < OVERSAMPLING/16; i++) {
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// The sample is 16-bits right channel in the upper two bytes and 16-bits left channel
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// in the lower two bytes.
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// We just ignore the upper bits
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uint32_t pdm_sample = pdm_samples[i];
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REPEAT_16_TIMES( {
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if (pdm_sample & 0x8000) {
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running_sum += *filter_ptr;
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}
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filter_ptr++;
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pdm_sample <<= 1;
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2017-05-24 13:43:32 -04:00
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}
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2020-11-19 17:19:37 -05:00
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);
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2017-05-24 13:43:32 -04:00
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}
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2018-01-02 21:25:41 -05:00
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return running_sum;
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2017-05-24 13:43:32 -04:00
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}
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2018-01-02 21:25:41 -05:00
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// output_buffer may be a byte buffer or a halfword buffer.
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// output_buffer_length is the number of slots, not the number of bytes.
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2017-05-24 13:43:32 -04:00
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uint32_t common_hal_audiobusio_pdmin_record_to_buffer(audiobusio_pdmin_obj_t* self,
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2018-01-02 21:25:41 -05:00
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uint16_t* output_buffer, uint32_t output_buffer_length) {
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2021-04-23 10:46:33 -04:00
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uint8_t dma_channel = dma_allocate_channel();
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2021-10-15 09:39:13 -04:00
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pdmin_event_channel = find_sync_event_channel_raise();
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pdmin_dma_block_done = false;
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2018-04-26 15:51:37 -04:00
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2018-01-02 21:25:41 -05:00
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// We allocate two buffers on the stack to use for double buffering.
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const uint8_t samples_per_buffer = SAMPLES_PER_BUFFER;
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2017-05-24 13:43:32 -04:00
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// For every word we record, we throw away 2 bytes of a phantom second channel.
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2018-04-26 15:51:37 -04:00
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uint8_t words_per_sample = self->bytes_per_sample / 2;
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uint32_t words_per_buffer = samples_per_buffer * words_per_sample;
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2017-05-24 13:43:32 -04:00
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uint32_t first_buffer[words_per_buffer];
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uint32_t second_buffer[words_per_buffer];
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2018-04-26 15:51:37 -04:00
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turn_on_event_system();
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2017-05-24 13:43:32 -04:00
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COMPILER_ALIGNED(16) DmacDescriptor second_descriptor;
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2018-04-26 15:51:37 -04:00
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setup_dma(self, output_buffer_length, dma_descriptor(dma_channel), &second_descriptor,
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words_per_buffer, words_per_sample, first_buffer, second_buffer);
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2017-05-24 13:43:32 -04:00
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2018-05-02 18:15:25 -04:00
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uint8_t trigger_source = I2S_DMAC_ID_RX_0;
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#ifdef SAMD21
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trigger_source += self->serializer;
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#endif
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dma_configure(dma_channel, trigger_source, true);
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2021-10-15 09:39:13 -04:00
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init_event_channel_interrupt(pdmin_event_channel, CORE_GCLK, EVSYS_ID_GEN_DMAC_CH_0 + dma_channel);
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2018-06-12 12:35:51 -04:00
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// Turn on serializer now to get it in sync with DMA.
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i2s_set_serializer_enable(self->serializer, true);
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2019-08-06 22:42:01 -04:00
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audio_dma_enable_channel(dma_channel);
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2017-05-24 13:43:32 -04:00
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// Record
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uint32_t buffers_processed = 0;
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2018-01-02 21:25:41 -05:00
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uint32_t values_output = 0;
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2017-05-24 13:43:32 -04:00
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2018-01-02 21:25:41 -05:00
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uint32_t remaining_samples_needed = output_buffer_length;
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while (values_output < output_buffer_length) {
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2021-10-15 09:39:13 -04:00
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while (!pdmin_dma_block_done) {
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2019-08-11 09:38:59 -04:00
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RUN_BACKGROUND_TASKS;
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2017-05-24 13:43:32 -04:00
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}
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2021-10-15 09:39:13 -04:00
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common_hal_mcu_disable_interrupts();
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pdmin_dma_block_done = false;
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common_hal_mcu_enable_interrupts();
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2018-01-02 21:25:41 -05:00
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// The mic is running all the time, so we don't need to wait the usual 10msec or 100msec
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// for it to start up.
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// Flip back and forth between processing the first and second buffers.
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uint32_t *buffer = first_buffer;
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2018-04-26 15:51:37 -04:00
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DmacDescriptor* descriptor = dma_descriptor(dma_channel);
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2017-05-24 13:43:32 -04:00
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if (buffers_processed % 2 == 1) {
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buffer = second_buffer;
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descriptor = &second_descriptor;
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}
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2021-10-15 09:39:13 -04:00
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2018-01-02 21:25:41 -05:00
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// Decimate and filter the buffer that was just filled.
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uint32_t samples_gathered = descriptor->BTCNT.reg / words_per_sample;
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// Don't run off the end of output buffer. Process only as many as needed.
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uint32_t samples_to_process = min(remaining_samples_needed, samples_gathered);
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for (uint32_t i = 0; i < samples_to_process; i++) {
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// Call filter_sample just one place so it can be inlined.
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uint16_t value = filter_sample(buffer + i * words_per_sample);
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2017-05-24 13:43:32 -04:00
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if (self->bit_depth == 8) {
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2018-01-02 21:25:41 -05:00
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// Truncate to 8 bits.
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((uint8_t*) output_buffer)[values_output] = value >> 8;
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} else {
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output_buffer[values_output] = value;
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2017-05-24 13:43:32 -04:00
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}
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2018-01-02 21:25:41 -05:00
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values_output++;
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2017-05-24 13:43:32 -04:00
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}
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2018-01-02 21:25:41 -05:00
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2017-05-24 13:43:32 -04:00
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buffers_processed++;
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2018-01-02 21:25:41 -05:00
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// Compute how many more samples we need, and if the last buffer is the last
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// set of samples needed, adjust the DMA count to only fetch as necessary.
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remaining_samples_needed = output_buffer_length - values_output;
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if (remaining_samples_needed <= samples_per_buffer*2 &&
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remaining_samples_needed > samples_per_buffer) {
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// Adjust the DMA settings for the current buffer, which will be processed
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// after the other buffer, which is now receiving samples via DMA.
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// We don't adjust the DMA in progress, but the one after that.
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// Timeline:
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// 1. current buffer (already processed)
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// 2. alternate buffer (DMA in progress)
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// 3. current buffer (last set of samples needed)
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// Set up to receive the last set of samples (don't include the alternate buffer, now in use).
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uint32_t samples_needed_for_last_buffer = remaining_samples_needed - samples_per_buffer;
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descriptor->BTCNT.reg = samples_needed_for_last_buffer * words_per_sample;
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descriptor->DSTADDR.reg = ((uint32_t) buffer)
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+ samples_needed_for_last_buffer * words_per_sample * sizeof(buffer[0]);
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// Break chain to alternate buffer.
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2017-05-24 13:43:32 -04:00
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descriptor->DESCADDR.reg = 0;
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}
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}
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2021-10-15 09:39:13 -04:00
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disable_event_channel(pdmin_event_channel);
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pdmin_event_channel = EVSYS_SYNCH_NUM; // Invalid event_channel.
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2021-04-23 10:46:33 -04:00
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dma_free_channel(dma_channel);
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2018-06-12 12:35:51 -04:00
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// Turn off serializer, but leave clock on, to avoid mic startup delay.
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i2s_set_serializer_enable(self->serializer, false);
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2017-05-24 13:43:32 -04:00
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2018-01-02 21:25:41 -05:00
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return values_output;
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2017-05-24 13:43:32 -04:00
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}
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void common_hal_audiobusio_pdmin_record_to_file(audiobusio_pdmin_obj_t* self, uint8_t* buffer, uint32_t length) {
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}
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