2014-05-03 18:27:38 -04:00
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/*
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2017-06-30 03:22:17 -04:00
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* This file is part of the MicroPython project, http://micropython.org/
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2014-05-03 18:27:38 -04:00
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2013, 2014 Damien P. George
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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2014-03-12 21:06:26 -04:00
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#include <stdio.h>
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#include <string.h>
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2014-08-21 17:48:23 -04:00
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#include <stdarg.h>
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2014-03-12 21:06:26 -04:00
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2015-01-01 16:06:20 -05:00
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#include "py/runtime.h"
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#include "py/stream.h"
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2016-05-10 18:22:54 -04:00
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#include "py/mperrno.h"
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2015-10-30 19:03:58 -04:00
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#include "py/mphal.h"
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2014-04-21 07:03:09 -04:00
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#include "uart.h"
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2015-10-31 13:44:20 -04:00
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#include "irq.h"
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2016-12-04 20:21:45 -05:00
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#include "genhdr/pins.h"
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2014-03-12 21:06:26 -04:00
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2014-04-29 17:55:34 -04:00
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/// \moduleref pyb
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/// \class UART - duplex serial communication bus
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///
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/// UART implements the standard UART/USART duplex serial communications protocol. At
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2014-10-11 12:57:10 -04:00
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/// the physical level it consists of 2 lines: RX and TX. The unit of communication
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/// is a character (not to be confused with a string character) which can be 8 or 9
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/// bits wide.
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2014-04-29 17:55:34 -04:00
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///
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2014-10-11 12:57:10 -04:00
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/// UART objects can be created and initialised using:
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2014-04-29 17:55:34 -04:00
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///
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/// from pyb import UART
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///
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/// uart = UART(1, 9600) # init with given baudrate
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2014-10-11 12:57:10 -04:00
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/// uart.init(9600, bits=8, parity=None, stop=1) # init with given parameters
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2014-04-29 17:55:34 -04:00
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///
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2014-10-11 12:57:10 -04:00
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/// Bits can be 8 or 9. Parity can be None, 0 (even) or 1 (odd). Stop can be 1 or 2.
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2014-04-29 17:55:34 -04:00
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///
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2014-10-11 12:57:10 -04:00
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/// A UART object acts like a stream object and reading and writing is done
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/// using the standard stream methods:
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///
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/// uart.read(10) # read 10 characters, returns a bytes object
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2016-11-13 16:24:22 -05:00
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/// uart.read() # read all available characters
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2014-10-11 12:57:10 -04:00
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/// uart.readline() # read a line
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/// uart.readinto(buf) # read and store into the given buffer
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/// uart.write('abc') # write the 3 characters
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///
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/// Individual characters can be read/written using:
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///
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/// uart.readchar() # read 1 character and returns it as an integer
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/// uart.writechar(42) # write 1 character
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///
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/// To check if there is anything to be read, use:
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2014-04-29 17:55:34 -04:00
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///
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/// uart.any() # returns True if any characters waiting
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2014-04-20 20:59:43 -04:00
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2014-10-11 12:57:10 -04:00
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#define CHAR_WIDTH_8BIT (0)
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#define CHAR_WIDTH_9BIT (1)
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2014-04-21 07:03:09 -04:00
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struct _pyb_uart_obj_t {
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2014-03-16 03:22:22 -04:00
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mp_obj_base_t base;
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2014-10-31 16:28:10 -04:00
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UART_HandleTypeDef uart; // this is 17 words big
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2014-10-11 12:57:10 -04:00
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IRQn_Type irqn;
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2014-10-31 16:28:10 -04:00
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pyb_uart_t uart_id : 8;
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bool is_enabled : 1;
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byte char_width; // 0 for 7,8 bit chars, 1 for 9 bit chars
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uint16_t char_mask; // 0x7f for 7 bit, 0xff for 8 bit, 0x1ff for 9 bit
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2014-10-11 12:57:10 -04:00
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uint16_t timeout; // timeout waiting for first char
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uint16_t timeout_char; // timeout waiting between chars
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uint16_t read_buf_len; // len in chars; buf can hold len-1 chars
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volatile uint16_t read_buf_head; // indexes first empty slot
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uint16_t read_buf_tail; // indexes first full slot (not full if equals head)
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byte *read_buf; // byte or uint16_t, depending on char size
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2014-03-16 03:22:22 -04:00
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};
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2014-03-12 21:06:26 -04:00
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2014-10-11 12:57:10 -04:00
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STATIC mp_obj_t pyb_uart_deinit(mp_obj_t self_in);
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2018-02-23 11:53:20 -05:00
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extern void NORETURN __fatal_error(const char *msg);
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2014-10-11 12:57:10 -04:00
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void uart_init0(void) {
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2018-02-23 11:53:20 -05:00
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#if defined(STM32H7)
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RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0};
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// Configure USART1/6 clock source
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RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART16;
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RCC_PeriphClkInit.Usart16ClockSelection = RCC_USART16CLKSOURCE_D2PCLK2;
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if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
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__fatal_error("HAL_RCCEx_PeriphCLKConfig");
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}
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// Configure USART2/3/4/5/7/8 clock source
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RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART234578;
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RCC_PeriphClkInit.Usart16ClockSelection = RCC_USART234578CLKSOURCE_D2PCLK1;
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if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
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__fatal_error("HAL_RCCEx_PeriphCLKConfig");
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}
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#endif
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2015-01-07 18:38:50 -05:00
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for (int i = 0; i < MP_ARRAY_SIZE(MP_STATE_PORT(pyb_uart_obj_all)); i++) {
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MP_STATE_PORT(pyb_uart_obj_all)[i] = NULL;
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2014-10-11 12:57:10 -04:00
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}
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}
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// unregister all interrupt sources
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void uart_deinit(void) {
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2015-01-07 18:38:50 -05:00
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for (int i = 0; i < MP_ARRAY_SIZE(MP_STATE_PORT(pyb_uart_obj_all)); i++) {
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pyb_uart_obj_t *uart_obj = MP_STATE_PORT(pyb_uart_obj_all)[i];
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2014-10-11 12:57:10 -04:00
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if (uart_obj != NULL) {
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pyb_uart_deinit(uart_obj);
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}
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}
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}
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2016-12-04 23:31:16 -05:00
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STATIC bool uart_exists(int uart_id) {
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if (uart_id > MP_ARRAY_SIZE(MP_STATE_PORT(pyb_uart_obj_all))) {
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// safeguard against pyb_uart_obj_all array being configured too small
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return false;
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}
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switch (uart_id) {
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#if defined(MICROPY_HW_UART1_TX) && defined(MICROPY_HW_UART1_RX)
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case PYB_UART_1: return true;
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#endif
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#if defined(MICROPY_HW_UART2_TX) && defined(MICROPY_HW_UART2_RX)
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case PYB_UART_2: return true;
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#endif
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#if defined(MICROPY_HW_UART3_TX) && defined(MICROPY_HW_UART3_RX)
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case PYB_UART_3: return true;
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#endif
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#if defined(MICROPY_HW_UART4_TX) && defined(MICROPY_HW_UART4_RX)
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case PYB_UART_4: return true;
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#endif
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#if defined(MICROPY_HW_UART5_TX) && defined(MICROPY_HW_UART5_RX)
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case PYB_UART_5: return true;
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#endif
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#if defined(MICROPY_HW_UART6_TX) && defined(MICROPY_HW_UART6_RX)
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case PYB_UART_6: return true;
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#endif
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#if defined(MICROPY_HW_UART7_TX) && defined(MICROPY_HW_UART7_RX)
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case PYB_UART_7: return true;
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#endif
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#if defined(MICROPY_HW_UART8_TX) && defined(MICROPY_HW_UART8_RX)
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case PYB_UART_8: return true;
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#endif
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default: return false;
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}
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}
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2014-04-20 20:14:14 -04:00
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// assumes Init parameters have been set up correctly
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2014-10-30 20:40:57 -04:00
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STATIC bool uart_init2(pyb_uart_obj_t *uart_obj) {
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2014-10-11 12:57:10 -04:00
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USART_TypeDef *UARTx;
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IRQn_Type irqn;
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2016-12-04 20:21:45 -05:00
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int uart_unit;
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2014-03-12 21:06:26 -04:00
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2016-12-04 20:21:45 -05:00
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const pin_obj_t *pins[4] = {0};
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2014-04-13 20:45:58 -04:00
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2016-12-04 20:21:45 -05:00
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switch (uart_obj->uart_id) {
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#if defined(MICROPY_HW_UART1_TX) && defined(MICROPY_HW_UART1_RX)
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2015-08-02 19:23:47 -04:00
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case PYB_UART_1:
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2016-12-04 20:21:45 -05:00
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uart_unit = 1;
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2015-08-02 19:23:47 -04:00
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UARTx = USART1;
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irqn = USART1_IRQn;
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2016-12-04 20:21:45 -05:00
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pins[0] = &MICROPY_HW_UART1_TX;
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pins[1] = &MICROPY_HW_UART1_RX;
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2018-02-12 23:37:35 -05:00
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__HAL_RCC_USART1_CLK_ENABLE();
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2015-08-02 19:23:47 -04:00
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break;
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#endif
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2016-12-04 20:21:45 -05:00
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#if defined(MICROPY_HW_UART2_TX) && defined(MICROPY_HW_UART2_RX)
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2014-04-21 07:03:09 -04:00
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case PYB_UART_2:
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2016-12-04 20:21:45 -05:00
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uart_unit = 2;
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2014-04-21 07:03:09 -04:00
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UARTx = USART2;
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2014-10-11 12:57:10 -04:00
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irqn = USART2_IRQn;
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2016-12-04 20:21:45 -05:00
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pins[0] = &MICROPY_HW_UART2_TX;
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pins[1] = &MICROPY_HW_UART2_RX;
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2015-05-02 12:31:39 -04:00
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#if defined(MICROPY_HW_UART2_RTS)
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2014-10-30 20:40:57 -04:00
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if (uart_obj->uart.Init.HwFlowCtl & UART_HWCONTROL_RTS) {
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2016-12-04 20:21:45 -05:00
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pins[2] = &MICROPY_HW_UART2_RTS;
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2014-10-30 20:40:57 -04:00
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}
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2015-05-02 12:31:39 -04:00
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#endif
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#if defined(MICROPY_HW_UART2_CTS)
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2014-10-30 20:40:57 -04:00
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if (uart_obj->uart.Init.HwFlowCtl & UART_HWCONTROL_CTS) {
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2016-12-04 20:21:45 -05:00
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pins[3] = &MICROPY_HW_UART2_CTS;
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2014-10-30 20:40:57 -04:00
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}
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2015-05-02 12:31:39 -04:00
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#endif
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2018-02-12 23:37:35 -05:00
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__HAL_RCC_USART2_CLK_ENABLE();
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2014-03-12 21:06:26 -04:00
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break;
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2015-05-02 12:31:39 -04:00
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#endif
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2014-04-13 20:45:58 -04:00
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2016-12-04 20:21:45 -05:00
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#if defined(MICROPY_HW_UART3_TX) && defined(MICROPY_HW_UART3_RX)
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2014-04-21 07:03:09 -04:00
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case PYB_UART_3:
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2016-12-04 20:21:45 -05:00
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uart_unit = 3;
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2014-04-21 07:03:09 -04:00
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UARTx = USART3;
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2014-10-11 12:57:10 -04:00
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irqn = USART3_IRQn;
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2016-12-04 20:21:45 -05:00
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pins[0] = &MICROPY_HW_UART3_TX;
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pins[1] = &MICROPY_HW_UART3_RX;
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2015-05-02 12:31:39 -04:00
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#if defined(MICROPY_HW_UART3_RTS)
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2014-10-30 20:40:57 -04:00
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if (uart_obj->uart.Init.HwFlowCtl & UART_HWCONTROL_RTS) {
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2016-12-04 20:21:45 -05:00
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pins[2] = &MICROPY_HW_UART3_RTS;
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2014-10-30 20:40:57 -04:00
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}
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2015-05-02 12:31:39 -04:00
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#endif
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#if defined(MICROPY_HW_UART3_CTS)
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2014-10-30 20:40:57 -04:00
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if (uart_obj->uart.Init.HwFlowCtl & UART_HWCONTROL_CTS) {
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2016-12-04 20:21:45 -05:00
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pins[3] = &MICROPY_HW_UART3_CTS;
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2014-10-30 20:40:57 -04:00
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}
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2015-05-02 12:31:39 -04:00
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#endif
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2018-02-12 23:37:35 -05:00
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__HAL_RCC_USART3_CLK_ENABLE();
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2014-03-12 21:06:26 -04:00
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break;
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2015-04-18 10:59:08 -04:00
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#endif
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2014-04-13 20:45:58 -04:00
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2016-12-04 20:21:45 -05:00
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#if defined(MICROPY_HW_UART4_TX) && defined(MICROPY_HW_UART4_RX)
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2014-04-21 07:03:09 -04:00
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case PYB_UART_4:
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2016-12-04 20:21:45 -05:00
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uart_unit = 4;
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2014-04-21 07:03:09 -04:00
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UARTx = UART4;
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2014-10-11 12:57:10 -04:00
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irqn = UART4_IRQn;
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2016-12-04 20:21:45 -05:00
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pins[0] = &MICROPY_HW_UART4_TX;
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pins[1] = &MICROPY_HW_UART4_RX;
|
2018-02-12 23:37:35 -05:00
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__HAL_RCC_UART4_CLK_ENABLE();
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2014-04-13 20:45:58 -04:00
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break;
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2015-04-18 10:59:08 -04:00
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#endif
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2014-04-13 20:45:58 -04:00
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2016-12-04 20:21:45 -05:00
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#if defined(MICROPY_HW_UART5_TX) && defined(MICROPY_HW_UART5_RX)
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2015-05-31 18:37:37 -04:00
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case PYB_UART_5:
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2016-12-04 20:21:45 -05:00
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uart_unit = 5;
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2015-05-31 18:37:37 -04:00
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UARTx = UART5;
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irqn = UART5_IRQn;
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2016-12-04 20:21:45 -05:00
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pins[0] = &MICROPY_HW_UART5_TX;
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pins[1] = &MICROPY_HW_UART5_RX;
|
2018-02-12 23:37:35 -05:00
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__HAL_RCC_UART5_CLK_ENABLE();
|
2015-05-31 18:37:37 -04:00
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break;
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#endif
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2016-12-04 20:21:45 -05:00
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#if defined(MICROPY_HW_UART6_TX) && defined(MICROPY_HW_UART6_RX)
|
2014-04-21 07:03:09 -04:00
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case PYB_UART_6:
|
2016-12-04 20:21:45 -05:00
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uart_unit = 6;
|
2014-04-21 07:03:09 -04:00
|
|
|
UARTx = USART6;
|
2014-10-11 12:57:10 -04:00
|
|
|
irqn = USART6_IRQn;
|
2016-12-04 20:21:45 -05:00
|
|
|
pins[0] = &MICROPY_HW_UART6_TX;
|
|
|
|
pins[1] = &MICROPY_HW_UART6_RX;
|
2017-12-23 03:01:23 -05:00
|
|
|
#if defined(MICROPY_HW_UART6_RTS)
|
|
|
|
if (uart_obj->uart.Init.HwFlowCtl & UART_HWCONTROL_RTS) {
|
|
|
|
pins[2] = &MICROPY_HW_UART6_RTS;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
#if defined(MICROPY_HW_UART6_CTS)
|
|
|
|
if (uart_obj->uart.Init.HwFlowCtl & UART_HWCONTROL_CTS) {
|
|
|
|
pins[3] = &MICROPY_HW_UART6_CTS;
|
|
|
|
}
|
|
|
|
#endif
|
2018-02-12 23:37:35 -05:00
|
|
|
__HAL_RCC_USART6_CLK_ENABLE();
|
2014-03-12 21:06:26 -04:00
|
|
|
break;
|
2015-05-02 12:31:39 -04:00
|
|
|
#endif
|
2014-04-13 20:45:58 -04:00
|
|
|
|
2016-12-04 23:14:22 -05:00
|
|
|
#if defined(MICROPY_HW_UART7_TX) && defined(MICROPY_HW_UART7_RX)
|
|
|
|
case PYB_UART_7:
|
|
|
|
uart_unit = 7;
|
|
|
|
UARTx = UART7;
|
|
|
|
irqn = UART7_IRQn;
|
|
|
|
pins[0] = &MICROPY_HW_UART7_TX;
|
|
|
|
pins[1] = &MICROPY_HW_UART7_RX;
|
2018-02-12 23:37:35 -05:00
|
|
|
__HAL_RCC_UART7_CLK_ENABLE();
|
2016-12-04 23:14:22 -05:00
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#if defined(MICROPY_HW_UART8_TX) && defined(MICROPY_HW_UART8_RX)
|
|
|
|
case PYB_UART_8:
|
|
|
|
uart_unit = 8;
|
|
|
|
UARTx = UART8;
|
|
|
|
irqn = UART8_IRQn;
|
|
|
|
pins[0] = &MICROPY_HW_UART8_TX;
|
|
|
|
pins[1] = &MICROPY_HW_UART8_RX;
|
2018-02-12 23:37:35 -05:00
|
|
|
__HAL_RCC_UART8_CLK_ENABLE();
|
2016-12-04 23:14:22 -05:00
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
|
2014-04-13 20:45:58 -04:00
|
|
|
default:
|
2015-05-02 12:31:39 -04:00
|
|
|
// UART does not exist or is not configured for this board
|
2014-04-13 20:45:58 -04:00
|
|
|
return false;
|
2014-03-12 21:06:26 -04:00
|
|
|
}
|
|
|
|
|
2016-12-04 20:21:45 -05:00
|
|
|
uint32_t mode = MP_HAL_PIN_MODE_ALT;
|
|
|
|
uint32_t pull = MP_HAL_PIN_PULL_UP;
|
2014-10-11 12:57:10 -04:00
|
|
|
|
2016-12-04 20:21:45 -05:00
|
|
|
for (uint i = 0; i < 4; i++) {
|
|
|
|
if (pins[i] != NULL) {
|
|
|
|
bool ret = mp_hal_pin_config_alt(pins[i], mode, pull, AF_FN_UART, uart_unit);
|
|
|
|
if (!ret) {
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
}
|
2015-08-02 19:20:08 -04:00
|
|
|
}
|
|
|
|
|
2016-12-04 20:21:45 -05:00
|
|
|
uart_obj->irqn = irqn;
|
|
|
|
uart_obj->uart.Instance = UARTx;
|
|
|
|
|
2014-04-21 07:03:09 -04:00
|
|
|
// init UARTx
|
|
|
|
HAL_UART_Init(&uart_obj->uart);
|
2014-04-20 20:14:14 -04:00
|
|
|
|
2014-04-21 07:03:09 -04:00
|
|
|
uart_obj->is_enabled = true;
|
2014-04-20 20:14:14 -04:00
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2014-10-11 12:57:10 -04:00
|
|
|
/* obsolete and unused
|
2014-04-21 07:03:09 -04:00
|
|
|
bool uart_init(pyb_uart_obj_t *uart_obj, uint32_t baudrate) {
|
|
|
|
UART_HandleTypeDef *uh = &uart_obj->uart;
|
2014-03-16 03:22:22 -04:00
|
|
|
memset(uh, 0, sizeof(*uh));
|
|
|
|
uh->Init.BaudRate = baudrate;
|
2014-04-20 20:14:14 -04:00
|
|
|
uh->Init.WordLength = UART_WORDLENGTH_8B;
|
|
|
|
uh->Init.StopBits = UART_STOPBITS_1;
|
|
|
|
uh->Init.Parity = UART_PARITY_NONE;
|
|
|
|
uh->Init.Mode = UART_MODE_TX_RX;
|
2014-03-16 03:22:22 -04:00
|
|
|
uh->Init.HwFlowCtl = UART_HWCONTROL_NONE;
|
|
|
|
uh->Init.OverSampling = UART_OVERSAMPLING_16;
|
2014-04-21 07:03:09 -04:00
|
|
|
return uart_init2(uart_obj);
|
2014-04-20 20:14:14 -04:00
|
|
|
}
|
2014-10-11 12:57:10 -04:00
|
|
|
*/
|
2014-04-13 20:45:58 -04:00
|
|
|
|
2015-11-27 10:31:59 -05:00
|
|
|
mp_uint_t uart_rx_any(pyb_uart_obj_t *self) {
|
|
|
|
int buffer_bytes = self->read_buf_head - self->read_buf_tail;
|
|
|
|
if (buffer_bytes < 0) {
|
|
|
|
return buffer_bytes + self->read_buf_len;
|
|
|
|
} else if (buffer_bytes > 0) {
|
|
|
|
return buffer_bytes;
|
|
|
|
} else {
|
|
|
|
return __HAL_UART_GET_FLAG(&self->uart, UART_FLAG_RXNE) != RESET;
|
|
|
|
}
|
2014-03-12 21:06:26 -04:00
|
|
|
}
|
|
|
|
|
2014-10-11 12:57:10 -04:00
|
|
|
// Waits at most timeout milliseconds for at least 1 char to become ready for
|
|
|
|
// reading (from buf or for direct reading).
|
|
|
|
// Returns true if something available, false if not.
|
|
|
|
STATIC bool uart_rx_wait(pyb_uart_obj_t *self, uint32_t timeout) {
|
|
|
|
uint32_t start = HAL_GetTick();
|
|
|
|
for (;;) {
|
|
|
|
if (self->read_buf_tail != self->read_buf_head || __HAL_UART_GET_FLAG(&self->uart, UART_FLAG_RXNE) != RESET) {
|
|
|
|
return true; // have at least 1 char ready for reading
|
|
|
|
}
|
|
|
|
if (HAL_GetTick() - start >= timeout) {
|
|
|
|
return false; // timeout
|
|
|
|
}
|
2017-02-05 23:10:03 -05:00
|
|
|
MICROPY_EVENT_POLL_HOOK
|
2014-10-11 12:57:10 -04:00
|
|
|
}
|
2014-03-12 21:06:26 -04:00
|
|
|
}
|
|
|
|
|
2014-10-11 12:57:10 -04:00
|
|
|
// assumes there is a character available
|
|
|
|
int uart_rx_char(pyb_uart_obj_t *self) {
|
|
|
|
if (self->read_buf_tail != self->read_buf_head) {
|
|
|
|
// buffering via IRQ
|
|
|
|
int data;
|
|
|
|
if (self->char_width == CHAR_WIDTH_9BIT) {
|
|
|
|
data = ((uint16_t*)self->read_buf)[self->read_buf_tail];
|
|
|
|
} else {
|
|
|
|
data = self->read_buf[self->read_buf_tail];
|
|
|
|
}
|
|
|
|
self->read_buf_tail = (self->read_buf_tail + 1) % self->read_buf_len;
|
2016-03-25 06:20:12 -04:00
|
|
|
if (__HAL_UART_GET_FLAG(&self->uart, UART_FLAG_RXNE) != RESET) {
|
|
|
|
// UART was stalled by flow ctrl: re-enable IRQ now we have room in buffer
|
|
|
|
__HAL_UART_ENABLE_IT(&self->uart, UART_IT_RXNE);
|
|
|
|
}
|
2014-10-11 12:57:10 -04:00
|
|
|
return data;
|
|
|
|
} else {
|
|
|
|
// no buffering
|
2018-03-16 19:42:50 -04:00
|
|
|
#if defined(STM32F7) || defined(STM32L4) || defined(STM32H7)
|
2015-07-28 14:13:33 -04:00
|
|
|
return self->uart.Instance->RDR & self->char_mask;
|
|
|
|
#else
|
2014-10-31 16:28:10 -04:00
|
|
|
return self->uart.Instance->DR & self->char_mask;
|
2015-07-28 14:13:33 -04:00
|
|
|
#endif
|
2014-03-12 21:06:26 -04:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2015-11-30 12:29:52 -05:00
|
|
|
// Waits at most timeout milliseconds for TX register to become empty.
|
|
|
|
// Returns true if can write, false if can't.
|
|
|
|
STATIC bool uart_tx_wait(pyb_uart_obj_t *self, uint32_t timeout) {
|
|
|
|
uint32_t start = HAL_GetTick();
|
|
|
|
for (;;) {
|
|
|
|
if (__HAL_UART_GET_FLAG(&self->uart, UART_FLAG_TXE)) {
|
|
|
|
return true; // tx register is empty
|
|
|
|
}
|
|
|
|
if (HAL_GetTick() - start >= timeout) {
|
|
|
|
return false; // timeout
|
|
|
|
}
|
2017-02-05 23:10:03 -05:00
|
|
|
MICROPY_EVENT_POLL_HOOK
|
2015-11-30 12:29:52 -05:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2016-12-22 23:16:26 -05:00
|
|
|
// Waits at most timeout milliseconds for UART flag to be set.
|
|
|
|
// Returns true if flag is/was set, false on timeout.
|
|
|
|
STATIC bool uart_wait_flag_set(pyb_uart_obj_t *self, uint32_t flag, uint32_t timeout) {
|
|
|
|
// Note: we don't use WFI to idle in this loop because UART tx doesn't generate
|
|
|
|
// an interrupt and the flag can be set quickly if the baudrate is large.
|
|
|
|
uint32_t start = HAL_GetTick();
|
|
|
|
for (;;) {
|
|
|
|
if (__HAL_UART_GET_FLAG(&self->uart, flag)) {
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
if (timeout == 0 || HAL_GetTick() - start >= timeout) {
|
|
|
|
return false; // timeout
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// src - a pointer to the data to send (16-bit aligned for 9-bit chars)
|
|
|
|
// num_chars - number of characters to send (9-bit chars count for 2 bytes from src)
|
|
|
|
// *errcode - returns 0 for success, MP_Exxx on error
|
|
|
|
// returns the number of characters sent (valid even if there was an error)
|
|
|
|
STATIC size_t uart_tx_data(pyb_uart_obj_t *self, const void *src_in, size_t num_chars, int *errcode) {
|
|
|
|
if (num_chars == 0) {
|
|
|
|
*errcode = 0;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
uint32_t timeout;
|
2016-03-25 06:20:12 -04:00
|
|
|
if (self->uart.Init.HwFlowCtl & UART_HWCONTROL_CTS) {
|
|
|
|
// CTS can hold off transmission for an arbitrarily long time. Apply
|
|
|
|
// the overall timeout rather than the character timeout.
|
2016-12-22 23:16:26 -05:00
|
|
|
timeout = self->timeout;
|
|
|
|
} else {
|
|
|
|
// The timeout specified here is for waiting for the TX data register to
|
|
|
|
// become empty (ie between chars), as well as for the final char to be
|
|
|
|
// completely transferred. The default value for timeout_char is long
|
|
|
|
// enough for 1 char, but we need to double it to wait for the last char
|
|
|
|
// to be transferred to the data register, and then to be transmitted.
|
|
|
|
timeout = 2 * self->timeout_char;
|
|
|
|
}
|
|
|
|
|
|
|
|
const uint8_t *src = (const uint8_t*)src_in;
|
|
|
|
size_t num_tx = 0;
|
|
|
|
USART_TypeDef *uart = self->uart.Instance;
|
|
|
|
|
|
|
|
while (num_tx < num_chars) {
|
|
|
|
if (!uart_wait_flag_set(self, UART_FLAG_TXE, timeout)) {
|
|
|
|
*errcode = MP_ETIMEDOUT;
|
|
|
|
return num_tx;
|
|
|
|
}
|
|
|
|
uint32_t data;
|
|
|
|
if (self->char_width == CHAR_WIDTH_9BIT) {
|
|
|
|
data = *((uint16_t*)src) & 0x1ff;
|
|
|
|
src += 2;
|
|
|
|
} else {
|
|
|
|
data = *src++;
|
|
|
|
}
|
2018-03-16 19:42:50 -04:00
|
|
|
#if defined(STM32F4)
|
2016-12-22 23:16:26 -05:00
|
|
|
uart->DR = data;
|
|
|
|
#else
|
|
|
|
uart->TDR = data;
|
|
|
|
#endif
|
|
|
|
++num_tx;
|
|
|
|
}
|
|
|
|
|
|
|
|
// wait for the UART frame to complete
|
|
|
|
if (!uart_wait_flag_set(self, UART_FLAG_TC, timeout)) {
|
|
|
|
*errcode = MP_ETIMEDOUT;
|
|
|
|
return num_tx;
|
|
|
|
}
|
|
|
|
|
|
|
|
*errcode = 0;
|
|
|
|
return num_tx;
|
2015-11-30 12:29:52 -05:00
|
|
|
}
|
|
|
|
|
2014-04-21 07:03:09 -04:00
|
|
|
void uart_tx_strn(pyb_uart_obj_t *uart_obj, const char *str, uint len) {
|
2016-12-22 23:16:26 -05:00
|
|
|
int errcode;
|
|
|
|
uart_tx_data(uart_obj, str, len, &errcode);
|
2014-03-12 21:06:26 -04:00
|
|
|
}
|
|
|
|
|
2014-10-11 12:57:10 -04:00
|
|
|
// this IRQ handler is set up to handle RXNE interrupts only
|
|
|
|
void uart_irq_handler(mp_uint_t uart_id) {
|
|
|
|
// get the uart object
|
2015-01-07 18:38:50 -05:00
|
|
|
pyb_uart_obj_t *self = MP_STATE_PORT(pyb_uart_obj_all)[uart_id - 1];
|
2014-10-11 12:57:10 -04:00
|
|
|
|
|
|
|
if (self == NULL) {
|
|
|
|
// UART object has not been set, so we can't do anything, not
|
|
|
|
// even disable the IRQ. This should never happen.
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (__HAL_UART_GET_FLAG(&self->uart, UART_FLAG_RXNE) != RESET) {
|
|
|
|
if (self->read_buf_len != 0) {
|
|
|
|
uint16_t next_head = (self->read_buf_head + 1) % self->read_buf_len;
|
|
|
|
if (next_head != self->read_buf_tail) {
|
2016-03-25 06:20:12 -04:00
|
|
|
// only read data if room in buf
|
2018-03-16 19:42:50 -04:00
|
|
|
#if defined(STM32F7) || defined(STM32L4) || defined(STM32H7)
|
2016-03-25 06:20:12 -04:00
|
|
|
int data = self->uart.Instance->RDR; // clears UART_FLAG_RXNE
|
|
|
|
#else
|
|
|
|
int data = self->uart.Instance->DR; // clears UART_FLAG_RXNE
|
|
|
|
#endif
|
|
|
|
data &= self->char_mask;
|
2014-10-11 12:57:10 -04:00
|
|
|
if (self->char_width == CHAR_WIDTH_9BIT) {
|
|
|
|
((uint16_t*)self->read_buf)[self->read_buf_head] = data;
|
|
|
|
} else {
|
|
|
|
self->read_buf[self->read_buf_head] = data;
|
|
|
|
}
|
|
|
|
self->read_buf_head = next_head;
|
2016-03-25 06:20:12 -04:00
|
|
|
} else { // No room: leave char in buf, disable interrupt
|
|
|
|
__HAL_UART_DISABLE_IT(&self->uart, UART_IT_RXNE);
|
2014-10-11 12:57:10 -04:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2014-03-12 21:06:26 -04:00
|
|
|
/******************************************************************************/
|
2017-06-30 03:22:17 -04:00
|
|
|
/* MicroPython bindings */
|
2014-03-12 21:06:26 -04:00
|
|
|
|
2015-04-09 18:56:15 -04:00
|
|
|
STATIC void pyb_uart_print(const mp_print_t *print, mp_obj_t self_in, mp_print_kind_t kind) {
|
2014-04-21 07:03:09 -04:00
|
|
|
pyb_uart_obj_t *self = self_in;
|
2014-04-20 20:14:14 -04:00
|
|
|
if (!self->is_enabled) {
|
2015-04-09 18:56:15 -04:00
|
|
|
mp_printf(print, "UART(%u)", self->uart_id);
|
2014-04-20 20:14:14 -04:00
|
|
|
} else {
|
2017-12-20 10:31:05 -05:00
|
|
|
mp_int_t bits;
|
|
|
|
switch (self->uart.Init.WordLength) {
|
|
|
|
#ifdef UART_WORDLENGTH_7B
|
|
|
|
case UART_WORDLENGTH_7B: bits = 7; break;
|
|
|
|
#endif
|
|
|
|
case UART_WORDLENGTH_8B: bits = 8; break;
|
|
|
|
case UART_WORDLENGTH_9B: default: bits = 9; break;
|
|
|
|
}
|
2014-10-31 16:28:10 -04:00
|
|
|
if (self->uart.Init.Parity != UART_PARITY_NONE) {
|
|
|
|
bits -= 1;
|
|
|
|
}
|
2015-04-09 18:56:15 -04:00
|
|
|
mp_printf(print, "UART(%u, baudrate=%u, bits=%u, parity=",
|
2014-10-31 16:28:10 -04:00
|
|
|
self->uart_id, self->uart.Init.BaudRate, bits);
|
2014-04-20 20:14:14 -04:00
|
|
|
if (self->uart.Init.Parity == UART_PARITY_NONE) {
|
2015-04-09 18:56:15 -04:00
|
|
|
mp_print_str(print, "None");
|
2014-04-20 20:14:14 -04:00
|
|
|
} else {
|
2015-04-09 18:56:15 -04:00
|
|
|
mp_printf(print, "%u", self->uart.Init.Parity == UART_PARITY_EVEN ? 0 : 1);
|
2014-04-20 20:14:14 -04:00
|
|
|
}
|
2016-03-25 06:20:12 -04:00
|
|
|
if (self->uart.Init.HwFlowCtl) {
|
|
|
|
mp_printf(print, ", flow=");
|
|
|
|
if (self->uart.Init.HwFlowCtl & UART_HWCONTROL_RTS) {
|
|
|
|
mp_printf(print, "RTS%s", self->uart.Init.HwFlowCtl & UART_HWCONTROL_CTS ? "|" : "");
|
|
|
|
}
|
|
|
|
if (self->uart.Init.HwFlowCtl & UART_HWCONTROL_CTS) {
|
|
|
|
mp_printf(print, "CTS");
|
|
|
|
}
|
|
|
|
}
|
2015-04-09 18:56:15 -04:00
|
|
|
mp_printf(print, ", stop=%u, timeout=%u, timeout_char=%u, read_buf_len=%u)",
|
2014-10-11 12:57:10 -04:00
|
|
|
self->uart.Init.StopBits == UART_STOPBITS_1 ? 1 : 2,
|
2015-11-27 13:30:46 -05:00
|
|
|
self->timeout, self->timeout_char,
|
|
|
|
self->read_buf_len == 0 ? 0 : self->read_buf_len - 1); // -1 to adjust for usable length of buffer
|
2014-04-20 20:14:14 -04:00
|
|
|
}
|
2014-03-25 19:40:54 -04:00
|
|
|
}
|
|
|
|
|
2016-03-25 06:20:12 -04:00
|
|
|
/// \method init(baudrate, bits=8, parity=None, stop=1, *, timeout=1000, timeout_char=0, flow=0, read_buf_len=64)
|
2014-04-29 17:55:34 -04:00
|
|
|
///
|
2014-10-02 12:27:13 -04:00
|
|
|
/// Initialise the UART bus with the given parameters:
|
2014-04-29 17:55:34 -04:00
|
|
|
///
|
|
|
|
/// - `baudrate` is the clock rate.
|
2014-10-31 16:28:10 -04:00
|
|
|
/// - `bits` is the number of bits per byte, 7, 8 or 9.
|
2014-04-29 17:55:34 -04:00
|
|
|
/// - `parity` is the parity, `None`, 0 (even) or 1 (odd).
|
2014-10-11 12:57:10 -04:00
|
|
|
/// - `stop` is the number of stop bits, 1 or 2.
|
|
|
|
/// - `timeout` is the timeout in milliseconds to wait for the first character.
|
|
|
|
/// - `timeout_char` is the timeout in milliseconds to wait between characters.
|
2016-03-25 06:20:12 -04:00
|
|
|
/// - `flow` is RTS | CTS where RTS == 256, CTS == 512
|
2014-10-11 12:57:10 -04:00
|
|
|
/// - `read_buf_len` is the character length of the read buffer (0 to disable).
|
2017-08-29 20:59:58 -04:00
|
|
|
STATIC mp_obj_t pyb_uart_init_helper(pyb_uart_obj_t *self, size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
|
2014-10-11 12:57:10 -04:00
|
|
|
static const mp_arg_t allowed_args[] = {
|
|
|
|
{ MP_QSTR_baudrate, MP_ARG_REQUIRED | MP_ARG_INT, {.u_int = 9600} },
|
|
|
|
{ MP_QSTR_bits, MP_ARG_INT, {.u_int = 8} },
|
|
|
|
{ MP_QSTR_parity, MP_ARG_OBJ, {.u_obj = mp_const_none} },
|
|
|
|
{ MP_QSTR_stop, MP_ARG_INT, {.u_int = 1} },
|
2014-10-30 20:40:57 -04:00
|
|
|
{ MP_QSTR_flow, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = UART_HWCONTROL_NONE} },
|
2014-10-11 12:57:10 -04:00
|
|
|
{ MP_QSTR_timeout, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 1000} },
|
|
|
|
{ MP_QSTR_timeout_char, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 0} },
|
|
|
|
{ MP_QSTR_read_buf_len, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 64} },
|
|
|
|
};
|
2014-04-20 20:14:14 -04:00
|
|
|
|
|
|
|
// parse args
|
2015-12-12 10:55:51 -05:00
|
|
|
struct {
|
|
|
|
mp_arg_val_t baudrate, bits, parity, stop, flow, timeout, timeout_char, read_buf_len;
|
|
|
|
} args;
|
|
|
|
mp_arg_parse_all(n_args, pos_args, kw_args,
|
|
|
|
MP_ARRAY_SIZE(allowed_args), allowed_args, (mp_arg_val_t*)&args);
|
2014-04-20 20:14:14 -04:00
|
|
|
|
2014-04-21 07:03:09 -04:00
|
|
|
// set the UART configuration values
|
2014-04-20 20:14:14 -04:00
|
|
|
memset(&self->uart, 0, sizeof(self->uart));
|
|
|
|
UART_InitTypeDef *init = &self->uart.Init;
|
2014-10-31 16:28:10 -04:00
|
|
|
|
|
|
|
// baudrate
|
2015-12-12 10:55:51 -05:00
|
|
|
init->BaudRate = args.baudrate.u_int;
|
2014-10-31 16:28:10 -04:00
|
|
|
|
|
|
|
// parity
|
2015-12-12 10:55:51 -05:00
|
|
|
mp_int_t bits = args.bits.u_int;
|
|
|
|
if (args.parity.u_obj == mp_const_none) {
|
2014-04-20 20:14:14 -04:00
|
|
|
init->Parity = UART_PARITY_NONE;
|
|
|
|
} else {
|
2015-12-12 10:55:51 -05:00
|
|
|
mp_int_t parity = mp_obj_get_int(args.parity.u_obj);
|
2014-04-20 20:14:14 -04:00
|
|
|
init->Parity = (parity & 1) ? UART_PARITY_ODD : UART_PARITY_EVEN;
|
2014-10-31 16:28:10 -04:00
|
|
|
bits += 1; // STs convention has bits including parity
|
2014-04-20 20:14:14 -04:00
|
|
|
}
|
2014-10-31 16:28:10 -04:00
|
|
|
|
|
|
|
// number of bits
|
|
|
|
if (bits == 8) {
|
|
|
|
init->WordLength = UART_WORDLENGTH_8B;
|
|
|
|
} else if (bits == 9) {
|
|
|
|
init->WordLength = UART_WORDLENGTH_9B;
|
2017-12-20 10:31:05 -05:00
|
|
|
#ifdef UART_WORDLENGTH_7B
|
|
|
|
} else if (bits == 7) {
|
|
|
|
init->WordLength = UART_WORDLENGTH_7B;
|
|
|
|
#endif
|
2014-10-31 16:28:10 -04:00
|
|
|
} else {
|
2017-06-14 21:54:41 -04:00
|
|
|
mp_raise_ValueError("unsupported combination of bits and parity");
|
2014-10-31 16:28:10 -04:00
|
|
|
}
|
|
|
|
|
|
|
|
// stop bits
|
2015-12-12 10:55:51 -05:00
|
|
|
switch (args.stop.u_int) {
|
2014-10-11 12:57:10 -04:00
|
|
|
case 1: init->StopBits = UART_STOPBITS_1; break;
|
|
|
|
default: init->StopBits = UART_STOPBITS_2; break;
|
|
|
|
}
|
2014-10-31 16:28:10 -04:00
|
|
|
|
|
|
|
// flow control
|
2015-12-12 10:55:51 -05:00
|
|
|
init->HwFlowCtl = args.flow.u_int;
|
2014-10-31 16:28:10 -04:00
|
|
|
|
|
|
|
// extra config (not yet configurable)
|
|
|
|
init->Mode = UART_MODE_TX_RX;
|
2014-04-20 20:14:14 -04:00
|
|
|
init->OverSampling = UART_OVERSAMPLING_16;
|
|
|
|
|
2014-04-21 07:03:09 -04:00
|
|
|
// init UART (if it fails, it's because the port doesn't exist)
|
|
|
|
if (!uart_init2(self)) {
|
2017-06-14 22:02:14 -04:00
|
|
|
nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, "UART(%d) doesn't exist", self->uart_id));
|
2014-10-11 12:57:10 -04:00
|
|
|
}
|
|
|
|
|
2015-11-30 12:29:52 -05:00
|
|
|
// set timeout
|
2015-12-12 10:55:51 -05:00
|
|
|
self->timeout = args.timeout.u_int;
|
2015-11-30 12:29:52 -05:00
|
|
|
|
|
|
|
// set timeout_char
|
|
|
|
// make sure it is at least as long as a whole character (13 bits to be safe)
|
2016-12-28 01:32:18 -05:00
|
|
|
// minimum value is 2ms because sys-tick has a resolution of only 1ms
|
2015-12-12 10:55:51 -05:00
|
|
|
self->timeout_char = args.timeout_char.u_int;
|
2016-12-28 01:32:18 -05:00
|
|
|
uint32_t min_timeout_char = 13000 / init->BaudRate + 2;
|
2015-11-30 12:29:52 -05:00
|
|
|
if (self->timeout_char < min_timeout_char) {
|
|
|
|
self->timeout_char = min_timeout_char;
|
|
|
|
}
|
2014-10-11 12:57:10 -04:00
|
|
|
|
|
|
|
// setup the read buffer
|
|
|
|
m_del(byte, self->read_buf, self->read_buf_len << self->char_width);
|
|
|
|
if (init->WordLength == UART_WORDLENGTH_9B && init->Parity == UART_PARITY_NONE) {
|
2014-10-31 16:28:10 -04:00
|
|
|
self->char_mask = 0x1ff;
|
2014-10-11 12:57:10 -04:00
|
|
|
self->char_width = CHAR_WIDTH_9BIT;
|
|
|
|
} else {
|
2014-10-31 16:28:10 -04:00
|
|
|
if (init->WordLength == UART_WORDLENGTH_9B || init->Parity == UART_PARITY_NONE) {
|
|
|
|
self->char_mask = 0xff;
|
|
|
|
} else {
|
|
|
|
self->char_mask = 0x7f;
|
|
|
|
}
|
2014-10-11 12:57:10 -04:00
|
|
|
self->char_width = CHAR_WIDTH_8BIT;
|
|
|
|
}
|
|
|
|
self->read_buf_head = 0;
|
|
|
|
self->read_buf_tail = 0;
|
2015-12-12 10:55:51 -05:00
|
|
|
if (args.read_buf_len.u_int <= 0) {
|
2014-10-11 12:57:10 -04:00
|
|
|
// no read buffer
|
|
|
|
self->read_buf_len = 0;
|
|
|
|
self->read_buf = NULL;
|
|
|
|
HAL_NVIC_DisableIRQ(self->irqn);
|
|
|
|
__HAL_UART_DISABLE_IT(&self->uart, UART_IT_RXNE);
|
|
|
|
} else {
|
|
|
|
// read buffer using interrupts
|
2015-12-12 10:55:51 -05:00
|
|
|
self->read_buf_len = args.read_buf_len.u_int + 1; // +1 to adjust for usable length of buffer
|
2015-11-27 13:30:46 -05:00
|
|
|
self->read_buf = m_new(byte, self->read_buf_len << self->char_width);
|
2014-10-11 12:57:10 -04:00
|
|
|
__HAL_UART_ENABLE_IT(&self->uart, UART_IT_RXNE);
|
2017-07-18 23:12:10 -04:00
|
|
|
HAL_NVIC_SetPriority(self->irqn, IRQ_PRI_UART, IRQ_SUBPRI_UART);
|
2014-10-11 12:57:10 -04:00
|
|
|
HAL_NVIC_EnableIRQ(self->irqn);
|
2014-03-25 19:40:54 -04:00
|
|
|
}
|
|
|
|
|
2015-02-21 19:26:49 -05:00
|
|
|
// compute actual baudrate that was configured
|
|
|
|
// (this formula assumes UART_OVERSAMPLING_16)
|
2016-12-04 23:14:22 -05:00
|
|
|
uint32_t actual_baudrate = 0;
|
2018-03-16 19:42:50 -04:00
|
|
|
#if defined(STM32F7) || defined(STM32H7)
|
2016-12-04 23:14:22 -05:00
|
|
|
UART_ClockSourceTypeDef clocksource = UART_CLOCKSOURCE_UNDEFINED;
|
|
|
|
UART_GETCLOCKSOURCE(&self->uart, clocksource);
|
|
|
|
switch (clocksource) {
|
2018-02-23 11:53:20 -05:00
|
|
|
#if defined(STM32H7)
|
|
|
|
case UART_CLOCKSOURCE_D2PCLK1: actual_baudrate = HAL_RCC_GetPCLK1Freq(); break;
|
|
|
|
case UART_CLOCKSOURCE_D3PCLK1: actual_baudrate = HAL_RCC_GetPCLK1Freq(); break;
|
|
|
|
case UART_CLOCKSOURCE_D2PCLK2: actual_baudrate = HAL_RCC_GetPCLK2Freq(); break;
|
|
|
|
#else
|
2016-12-04 23:14:22 -05:00
|
|
|
case UART_CLOCKSOURCE_PCLK1: actual_baudrate = HAL_RCC_GetPCLK1Freq(); break;
|
|
|
|
case UART_CLOCKSOURCE_PCLK2: actual_baudrate = HAL_RCC_GetPCLK2Freq(); break;
|
|
|
|
case UART_CLOCKSOURCE_SYSCLK: actual_baudrate = HAL_RCC_GetSysClockFreq(); break;
|
2018-02-23 11:53:20 -05:00
|
|
|
#endif
|
|
|
|
#if defined(STM32H7)
|
|
|
|
case UART_CLOCKSOURCE_CSI: actual_baudrate = CSI_VALUE; break;
|
|
|
|
#endif
|
|
|
|
case UART_CLOCKSOURCE_HSI: actual_baudrate = HSI_VALUE; break;
|
2016-12-04 23:14:22 -05:00
|
|
|
case UART_CLOCKSOURCE_LSE: actual_baudrate = LSE_VALUE; break;
|
2018-02-23 11:53:20 -05:00
|
|
|
#if defined(STM32H7)
|
|
|
|
case UART_CLOCKSOURCE_PLL2:
|
|
|
|
case UART_CLOCKSOURCE_PLL3:
|
|
|
|
#endif
|
2016-12-04 23:14:22 -05:00
|
|
|
case UART_CLOCKSOURCE_UNDEFINED: break;
|
|
|
|
}
|
|
|
|
#else
|
2016-04-17 06:59:33 -04:00
|
|
|
if (self->uart.Instance == USART1
|
|
|
|
#if defined(USART6)
|
|
|
|
|| self->uart.Instance == USART6
|
|
|
|
#endif
|
|
|
|
) {
|
2015-02-21 19:26:49 -05:00
|
|
|
actual_baudrate = HAL_RCC_GetPCLK2Freq();
|
|
|
|
} else {
|
|
|
|
actual_baudrate = HAL_RCC_GetPCLK1Freq();
|
|
|
|
}
|
2016-12-04 23:14:22 -05:00
|
|
|
#endif
|
2015-02-21 19:26:49 -05:00
|
|
|
actual_baudrate /= self->uart.Instance->BRR;
|
|
|
|
|
|
|
|
// check we could set the baudrate within 5%
|
|
|
|
uint32_t baudrate_diff;
|
|
|
|
if (actual_baudrate > init->BaudRate) {
|
|
|
|
baudrate_diff = actual_baudrate - init->BaudRate;
|
|
|
|
} else {
|
|
|
|
baudrate_diff = init->BaudRate - actual_baudrate;
|
|
|
|
}
|
|
|
|
init->BaudRate = actual_baudrate; // remember actual baudrate for printing
|
|
|
|
if (20 * baudrate_diff > init->BaudRate) {
|
|
|
|
nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, "set baudrate %d is not within 5%% of desired value", actual_baudrate));
|
|
|
|
}
|
|
|
|
|
2014-04-20 20:14:14 -04:00
|
|
|
return mp_const_none;
|
|
|
|
}
|
|
|
|
|
2014-04-29 17:55:34 -04:00
|
|
|
/// \classmethod \constructor(bus, ...)
|
|
|
|
///
|
|
|
|
/// Construct a UART object on the given bus. `bus` can be 1-6, or 'XA', 'XB', 'YA', or 'YB'.
|
|
|
|
/// With no additional parameters, the UART object is created but not
|
|
|
|
/// initialised (it has the settings from the last initialisation of
|
|
|
|
/// the bus, if any). If extra arguments are given, the bus is initialised.
|
|
|
|
/// See `init` for parameters of initialisation.
|
2014-05-04 09:28:11 -04:00
|
|
|
///
|
|
|
|
/// The physical pins of the UART busses are:
|
|
|
|
///
|
|
|
|
/// - `UART(4)` is on `XA`: `(TX, RX) = (X1, X2) = (PA0, PA1)`
|
|
|
|
/// - `UART(1)` is on `XB`: `(TX, RX) = (X9, X10) = (PB6, PB7)`
|
|
|
|
/// - `UART(6)` is on `YA`: `(TX, RX) = (Y1, Y2) = (PC6, PC7)`
|
|
|
|
/// - `UART(3)` is on `YB`: `(TX, RX) = (Y9, Y10) = (PB10, PB11)`
|
|
|
|
/// - `UART(2)` is on: `(TX, RX) = (X3, X4) = (PA2, PA3)`
|
2017-01-04 08:10:42 -05:00
|
|
|
STATIC mp_obj_t pyb_uart_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *args) {
|
2014-04-20 20:14:14 -04:00
|
|
|
// check arguments
|
|
|
|
mp_arg_check_num(n_args, n_kw, 1, MP_OBJ_FUN_ARGS_MAX, true);
|
|
|
|
|
2014-04-13 20:45:58 -04:00
|
|
|
// work out port
|
2014-10-11 12:57:10 -04:00
|
|
|
int uart_id = 0;
|
2014-04-13 20:45:58 -04:00
|
|
|
if (MP_OBJ_IS_STR(args[0])) {
|
|
|
|
const char *port = mp_obj_str_get_str(args[0]);
|
2014-04-15 06:52:47 -04:00
|
|
|
if (0) {
|
2015-05-27 11:51:04 -04:00
|
|
|
#ifdef MICROPY_HW_UART1_NAME
|
|
|
|
} else if (strcmp(port, MICROPY_HW_UART1_NAME) == 0) {
|
|
|
|
uart_id = PYB_UART_1;
|
|
|
|
#endif
|
|
|
|
#ifdef MICROPY_HW_UART2_NAME
|
|
|
|
} else if (strcmp(port, MICROPY_HW_UART2_NAME) == 0) {
|
|
|
|
uart_id = PYB_UART_2;
|
|
|
|
#endif
|
|
|
|
#ifdef MICROPY_HW_UART3_NAME
|
|
|
|
} else if (strcmp(port, MICROPY_HW_UART3_NAME) == 0) {
|
|
|
|
uart_id = PYB_UART_3;
|
|
|
|
#endif
|
|
|
|
#ifdef MICROPY_HW_UART4_NAME
|
|
|
|
} else if (strcmp(port, MICROPY_HW_UART4_NAME) == 0) {
|
|
|
|
uart_id = PYB_UART_4;
|
|
|
|
#endif
|
|
|
|
#ifdef MICROPY_HW_UART5_NAME
|
|
|
|
} else if (strcmp(port, MICROPY_HW_UART5_NAME) == 0) {
|
|
|
|
uart_id = PYB_UART_5;
|
|
|
|
#endif
|
|
|
|
#ifdef MICROPY_HW_UART6_NAME
|
|
|
|
} else if (strcmp(port, MICROPY_HW_UART6_NAME) == 0) {
|
|
|
|
uart_id = PYB_UART_6;
|
|
|
|
#endif
|
2014-04-13 20:45:58 -04:00
|
|
|
} else {
|
2017-06-14 22:02:14 -04:00
|
|
|
nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, "UART(%s) doesn't exist", port));
|
2014-04-13 20:45:58 -04:00
|
|
|
}
|
2014-04-15 06:52:47 -04:00
|
|
|
} else {
|
2014-10-11 12:57:10 -04:00
|
|
|
uart_id = mp_obj_get_int(args[0]);
|
2016-12-04 23:31:16 -05:00
|
|
|
if (!uart_exists(uart_id)) {
|
2017-06-14 22:02:14 -04:00
|
|
|
nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, "UART(%d) doesn't exist", uart_id));
|
2014-10-11 12:57:10 -04:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
pyb_uart_obj_t *self;
|
2015-01-07 18:38:50 -05:00
|
|
|
if (MP_STATE_PORT(pyb_uart_obj_all)[uart_id - 1] == NULL) {
|
2014-10-11 12:57:10 -04:00
|
|
|
// create new UART object
|
|
|
|
self = m_new0(pyb_uart_obj_t, 1);
|
|
|
|
self->base.type = &pyb_uart_type;
|
|
|
|
self->uart_id = uart_id;
|
2015-01-07 18:38:50 -05:00
|
|
|
MP_STATE_PORT(pyb_uart_obj_all)[uart_id - 1] = self;
|
2014-10-11 12:57:10 -04:00
|
|
|
} else {
|
|
|
|
// reference existing UART object
|
2015-01-07 18:38:50 -05:00
|
|
|
self = MP_STATE_PORT(pyb_uart_obj_all)[uart_id - 1];
|
2014-04-13 20:45:58 -04:00
|
|
|
}
|
|
|
|
|
2014-04-20 20:14:14 -04:00
|
|
|
if (n_args > 1 || n_kw > 0) {
|
|
|
|
// start the peripheral
|
|
|
|
mp_map_t kw_args;
|
|
|
|
mp_map_init_fixed_table(&kw_args, n_kw, args + n_args);
|
2014-10-11 12:57:10 -04:00
|
|
|
pyb_uart_init_helper(self, n_args - 1, args + 1, &kw_args);
|
2014-04-13 20:45:58 -04:00
|
|
|
}
|
|
|
|
|
2014-10-11 12:57:10 -04:00
|
|
|
return self;
|
2014-03-25 19:40:54 -04:00
|
|
|
}
|
|
|
|
|
2017-08-29 20:59:58 -04:00
|
|
|
STATIC mp_obj_t pyb_uart_init(size_t n_args, const mp_obj_t *args, mp_map_t *kw_args) {
|
2014-04-21 07:03:09 -04:00
|
|
|
return pyb_uart_init_helper(args[0], n_args - 1, args + 1, kw_args);
|
2014-04-20 20:14:14 -04:00
|
|
|
}
|
2014-04-21 07:03:09 -04:00
|
|
|
STATIC MP_DEFINE_CONST_FUN_OBJ_KW(pyb_uart_init_obj, 1, pyb_uart_init);
|
2014-04-20 20:14:14 -04:00
|
|
|
|
2014-04-29 17:55:34 -04:00
|
|
|
/// \method deinit()
|
|
|
|
/// Turn off the UART bus.
|
2014-04-21 07:03:09 -04:00
|
|
|
STATIC mp_obj_t pyb_uart_deinit(mp_obj_t self_in) {
|
|
|
|
pyb_uart_obj_t *self = self_in;
|
2014-10-11 12:57:10 -04:00
|
|
|
self->is_enabled = false;
|
|
|
|
UART_HandleTypeDef *uart = &self->uart;
|
|
|
|
HAL_UART_DeInit(uart);
|
|
|
|
if (uart->Instance == USART1) {
|
|
|
|
HAL_NVIC_DisableIRQ(USART1_IRQn);
|
2018-02-12 23:37:35 -05:00
|
|
|
__HAL_RCC_USART1_FORCE_RESET();
|
|
|
|
__HAL_RCC_USART1_RELEASE_RESET();
|
|
|
|
__HAL_RCC_USART1_CLK_DISABLE();
|
2014-10-11 12:57:10 -04:00
|
|
|
} else if (uart->Instance == USART2) {
|
|
|
|
HAL_NVIC_DisableIRQ(USART2_IRQn);
|
2018-02-12 23:37:35 -05:00
|
|
|
__HAL_RCC_USART2_FORCE_RESET();
|
|
|
|
__HAL_RCC_USART2_RELEASE_RESET();
|
|
|
|
__HAL_RCC_USART2_CLK_DISABLE();
|
2015-04-18 10:59:08 -04:00
|
|
|
#if defined(USART3)
|
2014-10-11 12:57:10 -04:00
|
|
|
} else if (uart->Instance == USART3) {
|
|
|
|
HAL_NVIC_DisableIRQ(USART3_IRQn);
|
2018-02-12 23:37:35 -05:00
|
|
|
__HAL_RCC_USART3_FORCE_RESET();
|
|
|
|
__HAL_RCC_USART3_RELEASE_RESET();
|
|
|
|
__HAL_RCC_USART3_CLK_DISABLE();
|
2015-04-18 10:59:08 -04:00
|
|
|
#endif
|
|
|
|
#if defined(UART4)
|
2014-10-11 12:57:10 -04:00
|
|
|
} else if (uart->Instance == UART4) {
|
|
|
|
HAL_NVIC_DisableIRQ(UART4_IRQn);
|
2018-02-12 23:37:35 -05:00
|
|
|
__HAL_RCC_UART4_FORCE_RESET();
|
|
|
|
__HAL_RCC_UART4_RELEASE_RESET();
|
|
|
|
__HAL_RCC_UART4_CLK_DISABLE();
|
2015-04-18 10:59:08 -04:00
|
|
|
#endif
|
2015-05-31 18:37:37 -04:00
|
|
|
#if defined(UART5)
|
|
|
|
} else if (uart->Instance == UART5) {
|
|
|
|
HAL_NVIC_DisableIRQ(UART5_IRQn);
|
2018-02-12 23:37:35 -05:00
|
|
|
__HAL_RCC_UART5_FORCE_RESET();
|
|
|
|
__HAL_RCC_UART5_RELEASE_RESET();
|
|
|
|
__HAL_RCC_UART5_CLK_DISABLE();
|
2015-05-31 18:37:37 -04:00
|
|
|
#endif
|
2016-04-17 06:59:33 -04:00
|
|
|
#if defined(UART6)
|
2014-10-11 12:57:10 -04:00
|
|
|
} else if (uart->Instance == USART6) {
|
|
|
|
HAL_NVIC_DisableIRQ(USART6_IRQn);
|
2018-02-12 23:37:35 -05:00
|
|
|
__HAL_RCC_USART6_FORCE_RESET();
|
|
|
|
__HAL_RCC_USART6_RELEASE_RESET();
|
|
|
|
__HAL_RCC_USART6_CLK_DISABLE();
|
2016-04-17 06:59:33 -04:00
|
|
|
#endif
|
2016-12-04 23:14:22 -05:00
|
|
|
#if defined(UART7)
|
|
|
|
} else if (uart->Instance == UART7) {
|
|
|
|
HAL_NVIC_DisableIRQ(UART7_IRQn);
|
2018-02-12 23:37:35 -05:00
|
|
|
__HAL_RCC_UART7_FORCE_RESET();
|
|
|
|
__HAL_RCC_UART7_RELEASE_RESET();
|
|
|
|
__HAL_RCC_UART7_CLK_DISABLE();
|
2016-12-04 23:14:22 -05:00
|
|
|
#endif
|
|
|
|
#if defined(UART8)
|
|
|
|
} else if (uart->Instance == UART8) {
|
|
|
|
HAL_NVIC_DisableIRQ(UART8_IRQn);
|
2018-02-12 23:37:35 -05:00
|
|
|
__HAL_RCC_UART8_FORCE_RESET();
|
|
|
|
__HAL_RCC_UART8_RELEASE_RESET();
|
|
|
|
__HAL_RCC_UART8_CLK_DISABLE();
|
2016-12-04 23:14:22 -05:00
|
|
|
#endif
|
2014-10-11 12:57:10 -04:00
|
|
|
}
|
2014-04-20 20:14:14 -04:00
|
|
|
return mp_const_none;
|
|
|
|
}
|
2014-04-21 07:03:09 -04:00
|
|
|
STATIC MP_DEFINE_CONST_FUN_OBJ_1(pyb_uart_deinit_obj, pyb_uart_deinit);
|
2014-04-20 20:14:14 -04:00
|
|
|
|
2014-04-29 17:55:34 -04:00
|
|
|
/// \method any()
|
|
|
|
/// Return `True` if any characters waiting, else `False`.
|
2014-04-21 07:03:09 -04:00
|
|
|
STATIC mp_obj_t pyb_uart_any(mp_obj_t self_in) {
|
|
|
|
pyb_uart_obj_t *self = self_in;
|
2015-11-27 10:31:59 -05:00
|
|
|
return MP_OBJ_NEW_SMALL_INT(uart_rx_any(self));
|
2014-03-12 21:06:26 -04:00
|
|
|
}
|
2014-04-21 07:03:09 -04:00
|
|
|
STATIC MP_DEFINE_CONST_FUN_OBJ_1(pyb_uart_any_obj, pyb_uart_any);
|
2014-03-12 21:06:26 -04:00
|
|
|
|
2014-10-11 12:57:10 -04:00
|
|
|
/// \method writechar(char)
|
|
|
|
/// Write a single character on the bus. `char` is an integer to write.
|
2014-04-29 17:55:34 -04:00
|
|
|
/// Return value: `None`.
|
2014-10-11 12:57:10 -04:00
|
|
|
STATIC mp_obj_t pyb_uart_writechar(mp_obj_t self_in, mp_obj_t char_in) {
|
|
|
|
pyb_uart_obj_t *self = self_in;
|
2014-04-20 20:14:14 -04:00
|
|
|
|
2014-10-11 12:57:10 -04:00
|
|
|
// get the character to write (might be 9 bits)
|
|
|
|
uint16_t data = mp_obj_get_int(char_in);
|
2014-04-20 20:14:14 -04:00
|
|
|
|
2015-11-30 12:29:52 -05:00
|
|
|
// write the character
|
2016-12-22 23:16:26 -05:00
|
|
|
int errcode;
|
2015-11-30 12:29:52 -05:00
|
|
|
if (uart_tx_wait(self, self->timeout)) {
|
2016-12-22 23:16:26 -05:00
|
|
|
uart_tx_data(self, &data, 1, &errcode);
|
2015-11-30 12:29:52 -05:00
|
|
|
} else {
|
2016-12-22 23:16:26 -05:00
|
|
|
errcode = MP_ETIMEDOUT;
|
2015-11-30 12:29:52 -05:00
|
|
|
}
|
2014-04-20 20:14:14 -04:00
|
|
|
|
2016-12-22 23:16:26 -05:00
|
|
|
if (errcode != 0) {
|
|
|
|
mp_raise_OSError(errcode);
|
2014-03-12 21:06:26 -04:00
|
|
|
}
|
2014-04-20 20:14:14 -04:00
|
|
|
|
2014-03-12 21:06:26 -04:00
|
|
|
return mp_const_none;
|
|
|
|
}
|
2014-10-11 12:57:10 -04:00
|
|
|
STATIC MP_DEFINE_CONST_FUN_OBJ_2(pyb_uart_writechar_obj, pyb_uart_writechar);
|
2014-04-20 20:14:14 -04:00
|
|
|
|
2014-10-11 12:57:10 -04:00
|
|
|
/// \method readchar()
|
|
|
|
/// Receive a single character on the bus.
|
|
|
|
/// Return value: The character read, as an integer. Returns -1 on timeout.
|
|
|
|
STATIC mp_obj_t pyb_uart_readchar(mp_obj_t self_in) {
|
|
|
|
pyb_uart_obj_t *self = self_in;
|
|
|
|
if (uart_rx_wait(self, self->timeout)) {
|
|
|
|
return MP_OBJ_NEW_SMALL_INT(uart_rx_char(self));
|
|
|
|
} else {
|
|
|
|
// return -1 on timeout
|
|
|
|
return MP_OBJ_NEW_SMALL_INT(-1);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
STATIC MP_DEFINE_CONST_FUN_OBJ_1(pyb_uart_readchar_obj, pyb_uart_readchar);
|
|
|
|
|
2015-02-13 14:04:24 -05:00
|
|
|
// uart.sendbreak()
|
|
|
|
STATIC mp_obj_t pyb_uart_sendbreak(mp_obj_t self_in) {
|
|
|
|
pyb_uart_obj_t *self = self_in;
|
2018-03-16 19:42:50 -04:00
|
|
|
#if defined(STM32F7) || defined(STM32L4) || defined(STM32H7)
|
2015-07-28 14:13:33 -04:00
|
|
|
self->uart.Instance->RQR = USART_RQR_SBKRQ; // write-only register
|
|
|
|
#else
|
2015-02-13 14:04:24 -05:00
|
|
|
self->uart.Instance->CR1 |= USART_CR1_SBK;
|
2015-07-28 14:13:33 -04:00
|
|
|
#endif
|
2015-02-13 14:04:24 -05:00
|
|
|
return mp_const_none;
|
|
|
|
}
|
|
|
|
STATIC MP_DEFINE_CONST_FUN_OBJ_1(pyb_uart_sendbreak_obj, pyb_uart_sendbreak);
|
|
|
|
|
2017-05-06 03:03:40 -04:00
|
|
|
STATIC const mp_rom_map_elem_t pyb_uart_locals_dict_table[] = {
|
2014-04-20 20:14:14 -04:00
|
|
|
// instance methods
|
2014-10-11 12:57:10 -04:00
|
|
|
|
2017-05-06 03:03:40 -04:00
|
|
|
{ MP_ROM_QSTR(MP_QSTR_init), MP_ROM_PTR(&pyb_uart_init_obj) },
|
|
|
|
{ MP_ROM_QSTR(MP_QSTR_deinit), MP_ROM_PTR(&pyb_uart_deinit_obj) },
|
|
|
|
{ MP_ROM_QSTR(MP_QSTR_any), MP_ROM_PTR(&pyb_uart_any_obj) },
|
2014-10-11 12:57:10 -04:00
|
|
|
|
|
|
|
/// \method read([nbytes])
|
2017-05-06 03:03:40 -04:00
|
|
|
{ MP_ROM_QSTR(MP_QSTR_read), MP_ROM_PTR(&mp_stream_read_obj) },
|
2014-10-11 12:57:10 -04:00
|
|
|
/// \method readline()
|
2017-05-06 03:03:40 -04:00
|
|
|
{ MP_ROM_QSTR(MP_QSTR_readline), MP_ROM_PTR(&mp_stream_unbuffered_readline_obj)},
|
2014-10-24 07:19:01 -04:00
|
|
|
/// \method readinto(buf[, nbytes])
|
2017-05-06 03:03:40 -04:00
|
|
|
{ MP_ROM_QSTR(MP_QSTR_readinto), MP_ROM_PTR(&mp_stream_readinto_obj) },
|
2014-10-11 12:57:10 -04:00
|
|
|
/// \method write(buf)
|
2017-05-06 03:03:40 -04:00
|
|
|
{ MP_ROM_QSTR(MP_QSTR_write), MP_ROM_PTR(&mp_stream_write_obj) },
|
2014-10-11 12:57:10 -04:00
|
|
|
|
2017-05-06 03:03:40 -04:00
|
|
|
{ MP_ROM_QSTR(MP_QSTR_writechar), MP_ROM_PTR(&pyb_uart_writechar_obj) },
|
|
|
|
{ MP_ROM_QSTR(MP_QSTR_readchar), MP_ROM_PTR(&pyb_uart_readchar_obj) },
|
|
|
|
{ MP_ROM_QSTR(MP_QSTR_sendbreak), MP_ROM_PTR(&pyb_uart_sendbreak_obj) },
|
2014-10-30 20:40:57 -04:00
|
|
|
|
|
|
|
// class constants
|
2017-05-06 03:03:40 -04:00
|
|
|
{ MP_ROM_QSTR(MP_QSTR_RTS), MP_ROM_INT(UART_HWCONTROL_RTS) },
|
|
|
|
{ MP_ROM_QSTR(MP_QSTR_CTS), MP_ROM_INT(UART_HWCONTROL_CTS) },
|
2014-03-12 21:06:26 -04:00
|
|
|
};
|
|
|
|
|
2014-04-21 07:03:09 -04:00
|
|
|
STATIC MP_DEFINE_CONST_DICT(pyb_uart_locals_dict, pyb_uart_locals_dict_table);
|
2014-03-26 17:47:19 -04:00
|
|
|
|
2014-10-11 12:57:10 -04:00
|
|
|
STATIC mp_uint_t pyb_uart_read(mp_obj_t self_in, void *buf_in, mp_uint_t size, int *errcode) {
|
|
|
|
pyb_uart_obj_t *self = self_in;
|
|
|
|
byte *buf = buf_in;
|
|
|
|
|
|
|
|
// check that size is a multiple of character width
|
|
|
|
if (size & self->char_width) {
|
2016-05-10 18:22:54 -04:00
|
|
|
*errcode = MP_EIO;
|
2014-10-11 12:57:10 -04:00
|
|
|
return MP_STREAM_ERROR;
|
|
|
|
}
|
|
|
|
|
|
|
|
// convert byte size to char size
|
|
|
|
size >>= self->char_width;
|
|
|
|
|
|
|
|
// make sure we want at least 1 char
|
|
|
|
if (size == 0) {
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
// wait for first char to become available
|
|
|
|
if (!uart_rx_wait(self, self->timeout)) {
|
2015-10-19 17:27:07 -04:00
|
|
|
// return EAGAIN error to indicate non-blocking (then read() method returns None)
|
2016-05-10 18:22:54 -04:00
|
|
|
*errcode = MP_EAGAIN;
|
2015-10-19 17:27:07 -04:00
|
|
|
return MP_STREAM_ERROR;
|
2014-10-11 12:57:10 -04:00
|
|
|
}
|
|
|
|
|
|
|
|
// read the data
|
|
|
|
byte *orig_buf = buf;
|
|
|
|
for (;;) {
|
|
|
|
int data = uart_rx_char(self);
|
|
|
|
if (self->char_width == CHAR_WIDTH_9BIT) {
|
|
|
|
*(uint16_t*)buf = data;
|
|
|
|
buf += 2;
|
|
|
|
} else {
|
|
|
|
*buf++ = data;
|
|
|
|
}
|
|
|
|
if (--size == 0 || !uart_rx_wait(self, self->timeout_char)) {
|
|
|
|
// return number of bytes read
|
|
|
|
return buf - orig_buf;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
STATIC mp_uint_t pyb_uart_write(mp_obj_t self_in, const void *buf_in, mp_uint_t size, int *errcode) {
|
|
|
|
pyb_uart_obj_t *self = self_in;
|
|
|
|
const byte *buf = buf_in;
|
|
|
|
|
|
|
|
// check that size is a multiple of character width
|
|
|
|
if (size & self->char_width) {
|
2016-05-10 18:22:54 -04:00
|
|
|
*errcode = MP_EIO;
|
2014-10-11 12:57:10 -04:00
|
|
|
return MP_STREAM_ERROR;
|
|
|
|
}
|
|
|
|
|
2016-03-25 06:20:12 -04:00
|
|
|
// wait to be able to write the first character. EAGAIN causes write to return None
|
2015-11-30 12:29:52 -05:00
|
|
|
if (!uart_tx_wait(self, self->timeout)) {
|
2016-05-10 18:22:54 -04:00
|
|
|
*errcode = MP_EAGAIN;
|
2015-11-30 12:29:52 -05:00
|
|
|
return MP_STREAM_ERROR;
|
|
|
|
}
|
|
|
|
|
2014-10-11 12:57:10 -04:00
|
|
|
// write the data
|
2016-12-22 23:16:26 -05:00
|
|
|
size_t num_tx = uart_tx_data(self, buf, size >> self->char_width, errcode);
|
|
|
|
|
|
|
|
if (*errcode == 0 || *errcode == MP_ETIMEDOUT) {
|
|
|
|
// return number of bytes written, even if there was a timeout
|
|
|
|
return num_tx << self->char_width;
|
2014-10-11 12:57:10 -04:00
|
|
|
} else {
|
|
|
|
return MP_STREAM_ERROR;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2014-11-16 17:16:14 -05:00
|
|
|
STATIC mp_uint_t pyb_uart_ioctl(mp_obj_t self_in, mp_uint_t request, mp_uint_t arg, int *errcode) {
|
2014-08-21 17:48:23 -04:00
|
|
|
pyb_uart_obj_t *self = self_in;
|
|
|
|
mp_uint_t ret;
|
2016-12-02 00:37:29 -05:00
|
|
|
if (request == MP_STREAM_POLL) {
|
2014-11-16 17:16:14 -05:00
|
|
|
mp_uint_t flags = arg;
|
2014-08-21 17:48:23 -04:00
|
|
|
ret = 0;
|
2016-12-02 00:37:29 -05:00
|
|
|
if ((flags & MP_STREAM_POLL_RD) && uart_rx_any(self)) {
|
|
|
|
ret |= MP_STREAM_POLL_RD;
|
2014-08-21 17:48:23 -04:00
|
|
|
}
|
2016-12-02 00:37:29 -05:00
|
|
|
if ((flags & MP_STREAM_POLL_WR) && __HAL_UART_GET_FLAG(&self->uart, UART_FLAG_TXE)) {
|
|
|
|
ret |= MP_STREAM_POLL_WR;
|
2014-08-21 17:48:23 -04:00
|
|
|
}
|
|
|
|
} else {
|
2016-05-10 18:22:54 -04:00
|
|
|
*errcode = MP_EINVAL;
|
2014-10-02 12:27:13 -04:00
|
|
|
ret = MP_STREAM_ERROR;
|
2014-08-21 17:48:23 -04:00
|
|
|
}
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
STATIC const mp_stream_p_t uart_stream_p = {
|
2014-10-11 12:57:10 -04:00
|
|
|
.read = pyb_uart_read,
|
|
|
|
.write = pyb_uart_write,
|
|
|
|
.ioctl = pyb_uart_ioctl,
|
2014-08-21 17:48:23 -04:00
|
|
|
.is_text = false,
|
|
|
|
};
|
|
|
|
|
2014-04-21 07:03:09 -04:00
|
|
|
const mp_obj_type_t pyb_uart_type = {
|
2014-03-12 21:06:26 -04:00
|
|
|
{ &mp_type_type },
|
2014-04-21 07:03:09 -04:00
|
|
|
.name = MP_QSTR_UART,
|
|
|
|
.print = pyb_uart_print,
|
|
|
|
.make_new = pyb_uart_make_new,
|
2016-01-09 18:14:54 -05:00
|
|
|
.getiter = mp_identity_getiter,
|
2014-10-11 12:57:10 -04:00
|
|
|
.iternext = mp_stream_unbuffered_iter,
|
2016-06-18 11:19:24 -04:00
|
|
|
.protocol = &uart_stream_p,
|
2017-05-06 03:03:40 -04:00
|
|
|
.locals_dict = (mp_obj_dict_t*)&pyb_uart_locals_dict,
|
2014-03-12 21:06:26 -04:00
|
|
|
};
|