ff208d7677
This class focuses on the timing sensitive parts of the protocol. Everything else will be done by Python code. This also establishes that its OK to back a nativeio class with a bitbang implementation when no hardware acceleration exists. When it does, then bitbangio should be used to explicitly bitbang a protocol.
184 lines
6.1 KiB
C
184 lines
6.1 KiB
C
/*
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* This file is part of the Micro Python project, http://micropython.org/
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2013, 2014 Damien P. George
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include <stdint.h>
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#include <string.h>
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#include "py/nlr.h"
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#include "py/runtime.h"
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#include "py/mphal.h"
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#include "shared-bindings/nativeio/DigitalInOut.h"
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#include "asf/sam0/drivers/port/port.h"
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#include "asf/sam0/drivers/system/pinmux/pinmux.h"
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digitalinout_result_t common_hal_nativeio_digitalinout_construct(
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nativeio_digitalinout_obj_t* self, const mcu_pin_obj_t* pin) {
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self->pin = pin;
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struct port_config pin_conf;
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port_get_config_defaults(&pin_conf);
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pin_conf.direction = PORT_PIN_DIR_INPUT;
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pin_conf.input_pull = PORT_PIN_PULL_NONE;
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port_pin_set_config(self->pin->pin, &pin_conf);
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return DIGITALINOUT_OK;
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}
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void common_hal_nativeio_digitalinout_deinit(nativeio_digitalinout_obj_t* self) {
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struct port_config pin_conf;
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port_get_config_defaults(&pin_conf);
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pin_conf.powersave = true;
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port_pin_set_config(self->pin->pin, &pin_conf);
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}
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void common_hal_nativeio_digitalinout_switch_to_input(
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nativeio_digitalinout_obj_t* self, enum digitalinout_pull_t pull) {
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self->output = false;
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common_hal_nativeio_digitalinout_set_pull(self, pull);
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}
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void common_hal_nativeio_digitalinout_switch_to_output(
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nativeio_digitalinout_obj_t* self, bool value,
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enum digitalinout_drive_mode_t drive_mode) {
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struct port_config pin_conf;
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port_get_config_defaults(&pin_conf);
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pin_conf.direction = PORT_PIN_DIR_INPUT;
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pin_conf.input_pull = PORT_PIN_PULL_NONE;
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port_pin_set_config(self->pin->pin, &pin_conf);
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self->output = true;
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self->open_drain = drive_mode == DRIVE_MODE_OPEN_DRAIN;
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common_hal_nativeio_digitalinout_set_value(self, value);
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}
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enum digitalinout_direction_t common_hal_nativeio_digitalinout_get_direction(
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nativeio_digitalinout_obj_t* self) {
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return self->output? DIRECTION_OUT : DIRECTION_IN;
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}
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void common_hal_nativeio_digitalinout_set_value(
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nativeio_digitalinout_obj_t* self, bool value) {
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uint32_t pin = self->pin->pin;
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PortGroup *const port_base = port_get_group_from_gpio_pin(pin);
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uint32_t pin_mask = (1UL << (pin % 32));
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/* Set the pin to high or low atomically based on the requested level */
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if (value) {
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if (self->open_drain) {
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port_base->DIRCLR.reg = pin_mask;
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} else {
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port_base->DIRSET.reg = pin_mask;
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port_base->OUTSET.reg = pin_mask;
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}
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} else {
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port_base->DIRSET.reg = pin_mask;
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port_base->OUTCLR.reg = pin_mask;
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}
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}
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bool common_hal_nativeio_digitalinout_get_value(
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nativeio_digitalinout_obj_t* self) {
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uint32_t pin = self->pin->pin;
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PortGroup *const port_base = port_get_group_from_gpio_pin(pin);
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uint32_t pin_mask = (1UL << (pin % 32));
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if (!self->output) {
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return (port_base->IN.reg & pin_mask);
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} else {
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if (self->open_drain && (port_base->DIR.reg & pin_mask) == 0) {
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return true;
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} else {
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return (port_base->OUT.reg & pin_mask);
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}
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}
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}
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void common_hal_nativeio_digitalinout_set_drive_mode(
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nativeio_digitalinout_obj_t* self,
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enum digitalinout_drive_mode_t drive_mode) {
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bool value = common_hal_nativeio_digitalinout_get_value(self);
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self->open_drain = drive_mode == DRIVE_MODE_OPEN_DRAIN;
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// True is implemented differently between modes so reset the value to make
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// sure its correct for the new mode.
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if (value) {
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common_hal_nativeio_digitalinout_set_value(self, value);
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}
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}
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enum digitalinout_drive_mode_t common_hal_nativeio_digitalinout_get_drive_mode(
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nativeio_digitalinout_obj_t* self) {
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if (self->open_drain) {
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return DRIVE_MODE_OPEN_DRAIN;
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} else {
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return DRIVE_MODE_PUSH_PULL;
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}
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}
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void common_hal_nativeio_digitalinout_set_pull(
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nativeio_digitalinout_obj_t* self, enum digitalinout_pull_t pull) {
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enum port_pin_pull asf_pull = PORT_PIN_PULL_NONE;
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switch (pull) {
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case PULL_UP:
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asf_pull = PORT_PIN_PULL_UP;
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break;
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case PULL_DOWN:
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asf_pull = PORT_PIN_PULL_DOWN;
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break;
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case PULL_NONE:
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default:
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break;
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}
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struct port_config pin_conf;
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port_get_config_defaults(&pin_conf);
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pin_conf.direction = PORT_PIN_DIR_INPUT;
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pin_conf.input_pull = asf_pull;
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port_pin_set_config(self->pin->pin, &pin_conf);
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}
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enum digitalinout_pull_t common_hal_nativeio_digitalinout_get_pull(
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nativeio_digitalinout_obj_t* self) {
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uint32_t pin = self->pin->pin;
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PortGroup *const port_base = port_get_group_from_gpio_pin(pin);
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uint32_t pin_mask = (1UL << (pin % 32));
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if (self->output) {
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mp_raise_AttributeError("Cannot get pull while in output mode");
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return PULL_NONE;
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} else {
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if (port_base->PINCFG[pin % 32].bit.PULLEN == 0) {
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return PULL_NONE;
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} if ((port_base->OUT.reg & pin_mask) > 0) {
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return PULL_UP;
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} else {
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return PULL_DOWN;
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}
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}
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}
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