fc9d66fac6
Methods implemented are: - rtc.init(date) - rtc.datetime([new_date]) - rtc.calibration(value) The presence of this class can be controlled by MICROPY_PY_MACHINE_RTC. If the RTC module is used, the time module uses the RTC as well. For boards without a 32kHz crystal, using RTC makes no sense, since it will then use the ULP32K oscillator, which is not precise at all. Therefore, it will by default only be enabled for boards using a crystal, but can be enabled in the respective mpconfigboard.h.
361 lines
14 KiB
C
361 lines
14 KiB
C
/*
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* This file is part of the MicroPython project, http://micropython.org/
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*
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* This file provides functions for configuring the clocks.
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2022 Robert Hammelrath
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include <stdint.h>
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#include "py/runtime.h"
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#include "py/mphal.h"
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#include "samd_soc.h"
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static uint32_t cpu_freq = CPU_FREQ;
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static uint32_t peripheral_freq = DFLL48M_FREQ;
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static uint32_t dfll48m_calibration;
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int sercom_gclk_id[] = {
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SERCOM0_GCLK_ID_CORE, SERCOM1_GCLK_ID_CORE,
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SERCOM2_GCLK_ID_CORE, SERCOM3_GCLK_ID_CORE,
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SERCOM4_GCLK_ID_CORE, SERCOM5_GCLK_ID_CORE,
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#if defined(SERCOM7_GCLK_ID_CORE)
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SERCOM6_GCLK_ID_CORE, SERCOM7_GCLK_ID_CORE,
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#endif
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};
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uint32_t get_cpu_freq(void) {
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return cpu_freq;
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}
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uint32_t get_peripheral_freq(void) {
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return peripheral_freq;
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}
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void set_cpu_freq(uint32_t cpu_freq_arg) {
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// Setup GCLK0 for 48MHz as default state to keep the MCU running during config change.
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GCLK->GENCTRL[0].reg = GCLK_GENCTRL_RUNSTDBY | GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC_DFLL;
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while (GCLK->SYNCBUSY.bit.GENCTRL0) {
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}
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// Setup DPLL0 for 120 MHz
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// first: disable DPLL0 in case it is running
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OSCCTRL->Dpll[0].DPLLCTRLA.bit.ENABLE = 0;
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while (OSCCTRL->Dpll[0].DPLLSYNCBUSY.bit.ENABLE == 1) {
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}
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if (cpu_freq_arg > DFLL48M_FREQ) {
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cpu_freq = cpu_freq_arg;
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peripheral_freq = DFLL48M_FREQ;
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// Now configure the registers
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OSCCTRL->Dpll[0].DPLLCTRLB.reg = OSCCTRL_DPLLCTRLB_DIV(1) | OSCCTRL_DPLLCTRLB_LBYPASS |
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OSCCTRL_DPLLCTRLB_REFCLK(0) | OSCCTRL_DPLLCTRLB_WUF | OSCCTRL_DPLLCTRLB_FILTER(0x01);
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uint32_t div = cpu_freq / DPLLx_REF_FREQ;
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uint32_t frac = (cpu_freq - div * DPLLx_REF_FREQ) / (DPLLx_REF_FREQ / 32);
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OSCCTRL->Dpll[0].DPLLRATIO.reg = (frac << 16) + div - 1;
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// enable it again
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OSCCTRL->Dpll[0].DPLLCTRLA.reg = OSCCTRL_DPLLCTRLA_ENABLE | OSCCTRL_DPLLCTRLA_RUNSTDBY;
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// Per errata 2.13.1
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while (!(OSCCTRL->Dpll[0].DPLLSTATUS.bit.CLKRDY == 1)) {
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}
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// Setup GCLK0 for DPLL0 output (48 or 48-200MHz)
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GCLK->GENCTRL[0].reg = GCLK_GENCTRL_RUNSTDBY | GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC_DPLL0;
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while (GCLK->SYNCBUSY.bit.GENCTRL0) {
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}
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// Set GCLK 2 back to 48 MHz
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GCLK->GENCTRL[2].reg = GCLK_GENCTRL_DIV(1) | GCLK_GENCTRL_RUNSTDBY | GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC_DFLL;
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while (GCLK->SYNCBUSY.bit.GENCTRL2) {
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}
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} else {
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int div = DFLL48M_FREQ / cpu_freq_arg;
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// Setup GCLK1 for the low freq
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GCLK->GENCTRL[2].reg = GCLK_GENCTRL_DIV(div) | GCLK_GENCTRL_RUNSTDBY | GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC_DFLL;
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while (GCLK->SYNCBUSY.bit.GENCTRL2) {
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}
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GCLK->GENCTRL[0].reg = GCLK_GENCTRL_DIV(div) | GCLK_GENCTRL_RUNSTDBY | GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC_DFLL;
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while (GCLK->SYNCBUSY.bit.GENCTRL0) {
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}
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peripheral_freq = DFLL48M_FREQ / div;
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cpu_freq = DFLL48M_FREQ / div;
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}
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if (cpu_freq >= 8000000) {
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// Setup GCLK5 for DFLL48M output (48 MHz)
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GCLK->GENCTRL[5].reg = GCLK_GENCTRL_DIV(1) | GCLK_GENCTRL_RUNSTDBY | GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC_DFLL;
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while (GCLK->SYNCBUSY.bit.GENCTRL5) {
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}
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} else {
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// Setup GCLK5 off if CPU Clk < 8 MHz
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GCLK->GENCTRL[5].reg = 0;
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while (GCLK->SYNCBUSY.bit.GENCTRL5) {
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}
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}
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SysTick_Config(cpu_freq / 1000);
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}
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void check_usb_recovery_mode(void) {
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#if !MICROPY_HW_XOSC32K
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mp_hal_delay_ms(500);
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// Check USB status. If not connected, switch DFLL48M back to open loop
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if (USB->DEVICE.DeviceEndpoint[0].EPCFG.reg == 0) {
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// as per Errata 2.8.3
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OSCCTRL->DFLLMUL.reg = 0;
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while (OSCCTRL->DFLLSYNC.bit.DFLLMUL == 1) {
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}
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// Set the mode to open loop mode
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OSCCTRL->DFLLCTRLB.reg = 0;
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while (OSCCTRL->DFLLSYNC.bit.DFLLCTRLB == 1) {
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}
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OSCCTRL->DFLLCTRLA.reg = OSCCTRL_DFLLCTRLA_RUNSTDBY | OSCCTRL_DFLLCTRLA_ENABLE;
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while (OSCCTRL->DFLLSYNC.bit.ENABLE == 1) {
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}
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OSCCTRL->DFLLVAL.reg = dfll48m_calibration; // Reload DFLLVAL register
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while (OSCCTRL->DFLLSYNC.bit.DFLLVAL == 1) {
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}
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// Set the mode to open loop mode
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OSCCTRL->DFLLCTRLB.reg = 0;
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while (OSCCTRL->DFLLSYNC.bit.DFLLCTRLB == 1) {
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}
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}
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#endif // MICROPY_HW_XOSC32K
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}
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// Purpose of the #defines for the clock configuration.
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//
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// The CPU clock is generated by DPLL0, which takes 32768 Hz as reference frequency,
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// supplied through GCLK1.
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//
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// DFLL48M is used for the peripheral clock, e.g. for PWM, UART, SPI, I2C.
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// DFLL48M is either free running, or controlled by the 32kHz crystal, or
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// Synchronized with the USB clock.
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//
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// GCLK1 takes it's input either from the 32kHz crystal, the internal low power
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// RC oscillator or from DFLL48M.
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//
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// #define MICROPY_HW_XOSC32K (0 | 1)
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//
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// If MICROPY_HW_XOSC32K = 1, the 32kHz crystal is used for the DFLL48M oscillator
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// and for GCLK1, feeding the CPU, unless MICROPY_HW_MCU_OSC32KULP is set.
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// In that case GCLK1 (and the CPU clock) is driven by the 32K Low power oscillator.
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// The reason for offering this option is a design flaw of the Adafruit
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// Feather boards, where the RGB Led and Debug signals interfere with the
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// crystal, causing the CPU to fail if it is driven by the crystal. The
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// peripheral devices are affected as well, but continue it's operation.
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//
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// If MICROPY_HW_XOSC32K = 0, the 32kHz signal for GCLK1 (and the CPU) is
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// created by dividing the 48MHz clock of DFLL48M.
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//
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// If MICROPY_HW_DFLL_USB_SYNC = 0, the DFLL48M oscillator is free running using
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// the pre-configured trim values. In that mode, the peripheral clock is
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// not exactly 48Mhz and has a substantional temperature drift.
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//
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// If MICROPY_HW_DFLL_USB_SYNC = 1, the DFLL48 is synchronized with the 1 kHz USB sync
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// signal. If after boot there is no USB sync withing 500ms, the configuratuion falls
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// back to a free running 48Mhz oscillator.
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//
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// In all modes, the 48MHz signal has a substantial jitter, largest when
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// MICROPY_HW_DFLL_USB_SYNC is active. That is caused by the repective
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// reference frequencies of 32kHz or 1 kHz being low. That affects most
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// PWM. Std Dev at 1kHz 0.156Hz (w. Crystal) up to 0.4 Hz (with USB sync).
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//
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// If none of the mentioned defines is set, the device uses the internal oscillators.
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void init_clocks(uint32_t cpu_freq) {
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dfll48m_calibration = 0; // please the compiler
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// SAMD51 clock settings
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// GCLK0: 48MHz from DFLL48M or 48 - 200 MHz from DPLL0 (SAMD51)
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// GCLK1: 32768 Hz from 32KULP or DFLL48M
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// GCLK2: 8-48MHz from DFLL48M for Peripheral devices
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// GCLK3: 8Mhz for the us-counter (TC0/TC1)
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// GCLK4: 32kHz from crystal, if present
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// GCLK5: 48MHz from DFLL48M for USB
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// DPLL0: 48 - 200 MHz
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// Steps to set up clocks:
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// Reset Clocks
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// Switch GCLK0 to DFLL 48MHz
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// Setup 32768 Hz source and DFLL48M in closed loop mode, if a crystal is present.
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// Setup GCLK1 to the DPLL0 Reference freq. of 32768 Hz
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// Setup GCLK1 to drive peripheral channel 1
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// Setup DPLL0 to 120MHz
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// Setup GCLK0 to 120MHz
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// Setup GCLK2 to 48MHz for Peripherals
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// Setup GCLK3 to 8MHz for TC0/TC1
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// Setup GCLK4 to 32kHz crystal, if present
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// Setup GCLK5 to 48 MHz
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// Setup GCLK0 for 48MHz as default state to keep the MCU running during config change.
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GCLK->GENCTRL[0].reg = GCLK_GENCTRL_RUNSTDBY | GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC_DFLL;
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while (GCLK->SYNCBUSY.bit.GENCTRL0) {
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}
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#if MICROPY_HW_XOSC32K
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// OSCILLATOR CONTROL
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// Enable the clock for RTC
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OSC32KCTRL->RTCCTRL.reg = OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K;
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// Setup XOSC32K
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OSC32KCTRL->INTFLAG.reg = OSC32KCTRL_INTFLAG_XOSC32KRDY | OSC32KCTRL_INTFLAG_XOSC32KFAIL;
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OSC32KCTRL->CFDCTRL.bit.CFDEN = 1; // Fall back to internal Osc on crystal fail
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OSC32KCTRL->XOSC32K.reg =
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OSC32KCTRL_XOSC32K_CGM_HS |
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OSC32KCTRL_XOSC32K_XTALEN |
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OSC32KCTRL_XOSC32K_EN32K |
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OSC32KCTRL_XOSC32K_EN1K |
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OSC32KCTRL_XOSC32K_RUNSTDBY |
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OSC32KCTRL_XOSC32K_STARTUP(4) |
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OSC32KCTRL_XOSC32K_ENABLE;
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// make sure osc32kcrtl is ready
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while (OSC32KCTRL->STATUS.bit.XOSC32KRDY == 0) {
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}
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#if MICROPY_HW_MCU_OSC32KULP
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// Setup GCLK1 for 32kHz ULP
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GCLK->GENCTRL[1].reg = GCLK_GENCTRL_RUNSTDBY | GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC_OSCULP32K;
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#else
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// Setup GCLK1 for 32kHz crystal
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GCLK->GENCTRL[1].reg = GCLK_GENCTRL_RUNSTDBY | GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC_XOSC32K;
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#endif
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while (GCLK->SYNCBUSY.bit.GENCTRL1) {
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}
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// Setup GCLK4 for 32kHz crystal
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GCLK->GENCTRL[4].reg = GCLK_GENCTRL_RUNSTDBY | GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC_XOSC32K;
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while (GCLK->SYNCBUSY.bit.GENCTRL4) {
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}
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// Set-up the DFLL48M in closed loop mode with input from the 32kHz crystal
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// Step 1: Peripheral channel 0 is driven by GCLK4 and it feeds DFLL48M
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GCLK->PCHCTRL[0].reg = GCLK_PCHCTRL_GEN_GCLK4 | GCLK_PCHCTRL_CHEN;
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while (GCLK->PCHCTRL[0].bit.CHEN == 0) {
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}
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// Step 2: Set the multiplication values. The offset of 16384 to the freq is for rounding.
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OSCCTRL->DFLLMUL.reg = OSCCTRL_DFLLMUL_MUL((DFLL48M_FREQ + DPLLx_REF_FREQ / 2) / DPLLx_REF_FREQ) |
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OSCCTRL_DFLLMUL_FSTEP(1) | OSCCTRL_DFLLMUL_CSTEP(1);
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while (OSCCTRL->DFLLSYNC.bit.DFLLMUL == 1) {
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}
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// Step 3: Set the mode to closed loop
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OSCCTRL->DFLLCTRLB.reg = OSCCTRL_DFLLCTRLB_BPLCKC | OSCCTRL_DFLLCTRLB_STABLE | OSCCTRL_DFLLCTRLB_MODE;
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while (OSCCTRL->DFLLSYNC.bit.DFLLCTRLB == 1) {
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}
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// Wait for lock fine
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while (OSCCTRL->STATUS.bit.DFLLLCKF == 0) {
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}
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// Step 4: Start the DFLL.
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OSCCTRL->DFLLCTRLA.reg = OSCCTRL_DFLLCTRLA_RUNSTDBY | OSCCTRL_DFLLCTRLA_ENABLE;
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while (OSCCTRL->DFLLSYNC.bit.ENABLE == 1) {
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}
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#else // MICROPY_HW_XOSC32K
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// Enable the clock for RTC
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OSC32KCTRL->RTCCTRL.reg = OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K;
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// Derive GCLK1 from DFLL48M at DPLL0_REF_FREQ as defined in mpconfigboard.h (e.g. 32768 Hz)
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GCLK->GENCTRL[1].reg = ((DFLL48M_FREQ + DPLLx_REF_FREQ / 2) / DPLLx_REF_FREQ) << GCLK_GENCTRL_DIV_Pos
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| GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC_DFLL;
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while (GCLK->SYNCBUSY.bit.GENCTRL1) {
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}
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OSCCTRL->DFLLCTRLA.bit.RUNSTDBY = 1;
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OSCCTRL->DFLLCTRLA.bit.ONDEMAND = 0;
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OSCCTRL->DFLLCTRLA.bit.ENABLE = 1;
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while (OSCCTRL->DFLLSYNC.bit.ENABLE == 1) {
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}
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#if MICROPY_HW_DFLL_USB_SYNC
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// Configure the DFLL48M for USB clock recovery.
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// Will have to switch back if no USB
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dfll48m_calibration = OSCCTRL->DFLLVAL.reg;
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// Set the Multiplication factor.
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OSCCTRL->DFLLMUL.reg = OSCCTRL_DFLLMUL_MUL(48000) |
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OSCCTRL_DFLLMUL_FSTEP(1) | OSCCTRL_DFLLMUL_CSTEP(1);
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while (OSCCTRL->DFLLSYNC.bit.DFLLMUL == 1) {
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}
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// Set the mode to closed loop USB Recovery
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OSCCTRL->DFLLCTRLB.reg = OSCCTRL_DFLLCTRLB_USBCRM | OSCCTRL_DFLLCTRLB_CCDIS | OSCCTRL_DFLLCTRLB_MODE;
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while (OSCCTRL->DFLLSYNC.bit.DFLLCTRLB == 1) {
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}
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#endif
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#endif // MICROPY_HW_XOSC32K
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// Peripheral channel 1 is driven by GCLK1 and it feeds DPLL0
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GCLK->PCHCTRL[1].reg = GCLK_PCHCTRL_GEN_GCLK1 | GCLK_PCHCTRL_CHEN;
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while (GCLK->PCHCTRL[1].bit.CHEN == 0) {
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}
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set_cpu_freq(cpu_freq);
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peripheral_freq = DFLL48M_FREQ; // To be changed if CPU_FREQ < 48M
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// Setup GCLK2 for DFLL48M output (48 MHz), may be scaled down later by calls to set_cpu_freq
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GCLK->GENCTRL[2].reg = GCLK_GENCTRL_DIV(1) | GCLK_GENCTRL_RUNSTDBY | GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC_DFLL;
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while (GCLK->SYNCBUSY.bit.GENCTRL2) {
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}
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// Setup GCLK3 for 8MHz, Used for TC0/1 counter
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GCLK->GENCTRL[3].reg = GCLK_GENCTRL_DIV(6) | GCLK_GENCTRL_RUNSTDBY | GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC_DFLL;
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while (GCLK->SYNCBUSY.bit.GENCTRL3) {
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}
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}
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void enable_sercom_clock(int id) {
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GCLK->PCHCTRL[sercom_gclk_id[id]].reg = GCLK_PCHCTRL_CHEN | GCLK_PCHCTRL_GEN_GCLK2;
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// no easy way to set the clocks, except enabling all of them
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switch (id) {
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case 0:
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MCLK->APBAMASK.bit.SERCOM0_ = 1;
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break;
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case 1:
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MCLK->APBAMASK.bit.SERCOM1_ = 1;
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break;
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case 2:
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MCLK->APBBMASK.bit.SERCOM2_ = 1;
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break;
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case 3:
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MCLK->APBBMASK.bit.SERCOM3_ = 1;
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break;
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case 4:
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MCLK->APBDMASK.bit.SERCOM4_ = 1;
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break;
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case 5:
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MCLK->APBDMASK.bit.SERCOM5_ = 1;
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break;
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#ifdef SERCOM7_GCLK_ID_CORE
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case 6:
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MCLK->APBDMASK.bit.SERCOM6_ = 1;
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break;
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case 7:
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MCLK->APBDMASK.bit.SERCOM7_ = 1;
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break;
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#endif
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}
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}
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