circuitpython/ports
Damien George f63b4f85aa py/parse: Work around xtensa esp-2020r3 compiler bug.
This commit works around a bug in xtensa-esp32-elf-gcc version esp-2020r3.

The bug is in generation of loop constructs.  The below code is generated
by the xtensa-esp32 compiler.  The first extract is the buggy machine code
and the second extract is the corrected machine code.  The test
`basics/logic_constfolding.py` fails with the first code and succeeds with
the second.

Disassembly of section .text.push_result_rule:

00000000 <push_result_rule>:
  ...
  d6:   209770       or      a9, a7, a7
  d9:   178976       loop    a9, f4 <push_result_rule+0xf4>
                     d9: R_XTENSA_SLOT0_OP   .text.push_result_rule+0xf4
  dc:   030190       rsr.lend        a9
  df:   130090       wsr.lbeg        a9
  e2:   a8c992       addi    a9, a9, -88
  e5:   06d992       addmi   a9, a9, 0x600
  e8:   130190       wsr.lend        a9
  eb:   002000       isync
  ee:   030290       rsr.lcount      a9
  f1:   01c992       addi    a9, a9, 1
  f4:   1494e7       bne     a4, a14, 10c <push_result_rule+0x10c>
                     f4: R_XTENSA_SLOT0_OP   .text.push_result_rule+0x10c

Disassembly of section .text.push_result_rule:

00000000 <push_result_rule>:
  ...
  d6:   209770       or      a9, a7, a7
  d9:   178976       loop    a9, f4 <push_result_rule+0xf4>
                     d9: R_XTENSA_SLOT0_OP   .text.push_result_rule+0xf4
  dc:   030190       rsr.lend        a9
  df:   130090       wsr.lbeg        a9
  e2:   000091       l32r    a9, fffc00e4 <push_result_rule+0xfffc00e4>
                     e2: R_XTENSA_SLOT0_OP   .literal.push_result_rule+0x18
  e5:   0020f0       nop
  e8:   130190       wsr.lend        a9
  eb:   002000       isync
  ee:   030290       rsr.lcount      a9
  f1:   01c992       addi    a9, a9, 1
  f4:   1494e7       bne     a4, a14, 10c <push_result_rule+0x10c>
                     f4: R_XTENSA_SLOT0_OP   .text.push_result_rule+0x10c

Work done in collaboration with @jimmo.

Signed-off-by: Damien George <damien@micropython.org>
2022-06-09 13:56:30 +10:00
..
bare-arm bare-arm/mpconfigport.h: Disable remaining optional features. 2021-11-01 14:23:06 +11:00
cc3200 all: Remove third argument to MP_REGISTER_MODULE. 2022-06-02 16:31:37 +10:00
esp32 py/parse: Work around xtensa esp-2020r3 compiler bug. 2022-06-09 13:56:30 +10:00
esp8266 all: Remove third argument to MP_REGISTER_MODULE. 2022-06-02 16:31:37 +10:00
javascript all: Remove third argument to MP_REGISTER_MODULE. 2022-06-02 16:31:37 +10:00
mimxrt mimxrt/machine_uart: Fix an inconsistency for UART.init() arg handling. 2022-06-07 18:21:46 +10:00
minimal ports: Use default VFS config for import_stat and builtin_open. 2022-05-25 13:04:45 +10:00
nrf nrf/mpconfigport: Fix MICROPY_VFS IO build support. 2022-06-03 12:39:43 +10:00
pic16bit pic16bit: Use 1 byte for qstr hash len and include header to fix build. 2022-06-07 16:55:18 +10:00
powerpc py/builtin: Clean up and simplify import_stat and builtin_open config. 2022-05-25 13:04:45 +10:00
qemu-arm all: Remove third argument to MP_REGISTER_MODULE. 2022-06-02 16:31:37 +10:00
renesas-ra renesas-ra/machine_pin: Remove code for unsupported Pin features. 2022-06-03 10:57:48 +10:00
rp2 extmod/extmod.cmake: Require components to be explicitly enabled. 2022-06-08 13:03:34 +10:00
samd all: Remove third argument to MP_REGISTER_MODULE. 2022-06-02 16:31:37 +10:00
stm32 stm32/boards/LEGO_HUB_NO6: Add comment to readme about powering off. 2022-06-09 13:24:08 +10:00
teensy all: Remove third argument to MP_REGISTER_MODULE. 2022-06-02 16:31:37 +10:00
unix unix/variants: Enable seeding random module on import in dev, coverage. 2022-06-07 23:41:49 +10:00
windows unix,windows: Factor out code that generates random bytes to a new func. 2022-06-07 23:41:30 +10:00
zephyr all: Remove third argument to MP_REGISTER_MODULE. 2022-06-02 16:31:37 +10:00