78f6c2232c
This is mostly for convenience, so that user code doesn't need to add additional checks. Also, bring the bitbangio into compatibility with busio wrt. empty buffers.
259 lines
10 KiB
C
259 lines
10 KiB
C
/*
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* This file is part of the MicroPython project, http://micropython.org/
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2016 Scott Shawcroft
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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// This file contains all of the Python API definitions for the
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// bitbangio.SPI class.
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#include <string.h>
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#include "shared-bindings/bitbangio/SPI.h"
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#include "shared-bindings/microcontroller/Pin.h"
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#include "shared-bindings/util.h"
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#include "lib/utils/context_manager_helpers.h"
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#include "py/mperrno.h"
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#include "py/runtime.h"
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//| .. currentmodule:: bitbangio
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//|
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//| :class:`SPI` -- a 3-4 wire serial protocol
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//| -----------------------------------------------
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//|
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//| SPI is a serial protocol that has exclusive pins for data in and out of the
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//| master. It is typically faster than :py:class:`~bitbangio.I2C` because a
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//| separate pin is used to control the active slave rather than a transmitted
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//| address. This class only manages three of the four SPI lines: `!clock`,
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//| `!MOSI`, `!MISO`. Its up to the client to manage the appropriate slave
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//| select line. (This is common because multiple slaves can share the `!clock`,
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//| `!MOSI` and `!MISO` lines and therefore the hardware.)
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//|
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//| .. class:: SPI(clock, MOSI=None, MISO=None)
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//|
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//| Construct an SPI object on the given pins.
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//|
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//| :param ~microcontroller.Pin clock: the pin to use for the clock.
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//| :param ~microcontroller.Pin MOSI: the Master Out Slave In pin.
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//| :param ~microcontroller.Pin MISO: the Master In Slave Out pin.
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//|
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// TODO(tannewt): Support LSB SPI.
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STATIC mp_obj_t bitbangio_spi_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *pos_args) {
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mp_arg_check_num(n_args, n_kw, 0, MP_OBJ_FUN_ARGS_MAX, true);
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bitbangio_spi_obj_t *self = m_new_obj(bitbangio_spi_obj_t);
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self->base.type = &bitbangio_spi_type;
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mp_map_t kw_args;
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mp_map_init_fixed_table(&kw_args, n_kw, pos_args + n_args);
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enum { ARG_clock, ARG_MOSI, ARG_MISO, ARG_baudrate, ARG_polarity, ARG_phase, ARG_bits, ARG_firstbit };
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static const mp_arg_t allowed_args[] = {
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{ MP_QSTR_clock, MP_ARG_REQUIRED | MP_ARG_OBJ },
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{ MP_QSTR_MOSI, MP_ARG_OBJ, {.u_obj = mp_const_none} },
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{ MP_QSTR_MISO, MP_ARG_OBJ, {.u_obj = mp_const_none} },
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};
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mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)];
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mp_arg_parse_all(n_args, pos_args, &kw_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args);
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assert_pin(args[ARG_clock].u_obj, false);
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assert_pin(args[ARG_MOSI].u_obj, true);
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assert_pin(args[ARG_MISO].u_obj, true);
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const mcu_pin_obj_t* clock = MP_OBJ_TO_PTR(args[ARG_clock].u_obj);
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const mcu_pin_obj_t* mosi = MP_OBJ_TO_PTR(args[ARG_MOSI].u_obj);
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const mcu_pin_obj_t* miso = MP_OBJ_TO_PTR(args[ARG_MISO].u_obj);
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shared_module_bitbangio_spi_construct(self, clock, mosi, miso);
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return (mp_obj_t)self;
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}
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//| .. method:: SPI.deinit()
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//|
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//| Turn off the SPI bus.
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//|
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STATIC mp_obj_t bitbangio_spi_obj_deinit(mp_obj_t self_in) {
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bitbangio_spi_obj_t *self = MP_OBJ_TO_PTR(self_in);
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shared_module_bitbangio_spi_deinit(self);
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return mp_const_none;
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}
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MP_DEFINE_CONST_FUN_OBJ_1(bitbangio_spi_deinit_obj, bitbangio_spi_obj_deinit);
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//| .. method:: SPI.__enter__()
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//|
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//| No-op used by Context Managers.
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//|
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// Provided by context manager helper.
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//| .. method:: SPI.__exit__()
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//|
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//| Automatically deinitializes the hardware when exiting a context. See
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//| :ref:`lifetime-and-contextmanagers` for more info.
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//|
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STATIC mp_obj_t bitbangio_spi_obj___exit__(size_t n_args, const mp_obj_t *args) {
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(void)n_args;
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shared_module_bitbangio_spi_deinit(args[0]);
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return mp_const_none;
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}
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STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(bitbangio_spi_obj___exit___obj, 4, 4, bitbangio_spi_obj___exit__);
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static void check_lock(bitbangio_spi_obj_t *self) {
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if (!shared_module_bitbangio_spi_has_lock(self)) {
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mp_raise_RuntimeError("Function requires lock");
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}
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}
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//| .. method:: SPI.configure(\*, baudrate=100000, polarity=0, phase=0, bits=8)
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//|
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//| Configures the SPI bus. Only valid when locked.
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//|
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//| :param int baudrate: the clock rate in Hertz
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//| :param int polarity: the base state of the clock line (0 or 1)
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//| :param int phase: the edge of the clock that data is captured. First (0)
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//| or second (1). Rising or falling depends on clock polarity.
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//| :param int bits: the number of bits per word
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//|
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STATIC mp_obj_t bitbangio_spi_configure(size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
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enum { ARG_baudrate, ARG_polarity, ARG_phase, ARG_bits };
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static const mp_arg_t allowed_args[] = {
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{ MP_QSTR_baudrate, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 100000} },
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{ MP_QSTR_polarity, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 0} },
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{ MP_QSTR_phase, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 0} },
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{ MP_QSTR_bits, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 8} },
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};
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bitbangio_spi_obj_t *self = MP_OBJ_TO_PTR(pos_args[0]);
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raise_error_if_deinited(shared_module_bitbangio_spi_deinited(self));
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check_lock(self);
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mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)];
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mp_arg_parse_all(n_args - 1, pos_args + 1, kw_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args);
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uint8_t polarity = args[ARG_polarity].u_int;
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if (polarity != 0 && polarity != 1) {
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mp_raise_ValueError("Invalid polarity");
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}
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uint8_t phase = args[ARG_phase].u_int;
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if (phase != 0 && phase != 1) {
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mp_raise_ValueError("Invalid phase");
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}
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uint8_t bits = args[ARG_bits].u_int;
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if (bits != 8 && bits != 9) {
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mp_raise_ValueError("Invalid number of bits");
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}
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shared_module_bitbangio_spi_configure(self, args[ARG_baudrate].u_int, polarity, phase, bits);
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return mp_const_none;
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}
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MP_DEFINE_CONST_FUN_OBJ_KW(bitbangio_spi_configure_obj, 1, bitbangio_spi_configure);
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//| .. method:: SPI.try_lock()
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//|
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//| Attempts to grab the SPI lock. Returns True on success.
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//|
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//| :return: True when lock has been grabbed
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//| :rtype: bool
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//|
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STATIC mp_obj_t bitbangio_spi_obj_try_lock(mp_obj_t self_in) {
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bitbangio_spi_obj_t *self = MP_OBJ_TO_PTR(self_in);
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raise_error_if_deinited(shared_module_bitbangio_spi_deinited(self));
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return mp_obj_new_bool(shared_module_bitbangio_spi_try_lock(self));
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}
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MP_DEFINE_CONST_FUN_OBJ_1(bitbangio_spi_try_lock_obj, bitbangio_spi_obj_try_lock);
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//| .. method:: SPI.unlock()
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//|
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//| Releases the SPI lock.
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//|
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STATIC mp_obj_t bitbangio_spi_obj_unlock(mp_obj_t self_in) {
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bitbangio_spi_obj_t *self = MP_OBJ_TO_PTR(self_in);
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raise_error_if_deinited(shared_module_bitbangio_spi_deinited(self));
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shared_module_bitbangio_spi_unlock(self);
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return mp_const_none;
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}
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MP_DEFINE_CONST_FUN_OBJ_1(bitbangio_spi_unlock_obj, bitbangio_spi_obj_unlock);
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//| .. method:: SPI.write(buf)
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//|
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//| Write the data contained in ``buf``. Requires the SPI being locked.
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//| If the buffer is empty, nothing happens.
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//|
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// TODO(tannewt): Add support for start and end kwargs.
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STATIC mp_obj_t bitbangio_spi_write(mp_obj_t self_in, mp_obj_t wr_buf) {
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bitbangio_spi_obj_t *self = MP_OBJ_TO_PTR(self_in);
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raise_error_if_deinited(shared_module_bitbangio_spi_deinited(self));
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mp_buffer_info_t src;
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mp_get_buffer_raise(wr_buf, &src, MP_BUFFER_READ);
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if (src.len == 0) {
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return mp_const_none;
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}
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check_lock(self);
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bool ok = shared_module_bitbangio_spi_write(self, src.buf, src.len);
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if (!ok) {
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mp_raise_OSError(MP_EIO);
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}
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return mp_const_none;
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}
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MP_DEFINE_CONST_FUN_OBJ_2(bitbangio_spi_write_obj, bitbangio_spi_write);
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//| .. method:: SPI.readinto(buf)
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//|
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//| Read into the buffer specified by ``buf`` while writing zeroes.
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//| Requires the SPI being locked.
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//| If the number of bytes to read is 0, nothing happens.
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//|
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// TODO(tannewt): Add support for start and end kwargs.
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STATIC mp_obj_t bitbangio_spi_readinto(size_t n_args, const mp_obj_t *args) {
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bitbangio_spi_obj_t *self = MP_OBJ_TO_PTR(args[0]);
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raise_error_if_deinited(shared_module_bitbangio_spi_deinited(self));
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mp_buffer_info_t bufinfo;
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mp_get_buffer_raise(args[1], &bufinfo, MP_BUFFER_WRITE);
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if (bufinfo.len == 0) {
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return mp_const_none;
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}
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check_lock(args[0]);
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bool ok = shared_module_bitbangio_spi_read(self, bufinfo.buf, bufinfo.len);
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if (!ok) {
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mp_raise_OSError(MP_EIO);
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}
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return mp_const_none;
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}
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MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(bitbangio_spi_readinto_obj, 2, 2, bitbangio_spi_readinto);
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STATIC const mp_rom_map_elem_t bitbangio_spi_locals_dict_table[] = {
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{ MP_ROM_QSTR(MP_QSTR_deinit), MP_ROM_PTR(&bitbangio_spi_deinit_obj) },
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{ MP_ROM_QSTR(MP_QSTR___enter__), MP_ROM_PTR(&default___enter___obj) },
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{ MP_ROM_QSTR(MP_QSTR___exit__), MP_ROM_PTR(&bitbangio_spi_obj___exit___obj) },
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{ MP_ROM_QSTR(MP_QSTR_configure), MP_ROM_PTR(&bitbangio_spi_configure_obj) },
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{ MP_ROM_QSTR(MP_QSTR_try_lock), MP_ROM_PTR(&bitbangio_spi_try_lock_obj) },
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{ MP_ROM_QSTR(MP_QSTR_unlock), MP_ROM_PTR(&bitbangio_spi_unlock_obj) },
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{ MP_ROM_QSTR(MP_QSTR_readinto), MP_ROM_PTR(&bitbangio_spi_readinto_obj) },
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{ MP_ROM_QSTR(MP_QSTR_write), MP_ROM_PTR(&bitbangio_spi_write_obj) },
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};
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STATIC MP_DEFINE_CONST_DICT(bitbangio_spi_locals_dict, bitbangio_spi_locals_dict_table);
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const mp_obj_type_t bitbangio_spi_type = {
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{ &mp_type_type },
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.name = MP_QSTR_SPI,
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.make_new = bitbangio_spi_make_new,
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.locals_dict = (mp_obj_dict_t*)&bitbangio_spi_locals_dict,
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};
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