9d91111b1b
This started while adding USB MIDI support (and descriptor support is in this change.) When seeing that I'd have to implement the MIDI class logic twice, once for atmel-samd and once for nrf, I decided to refactor the USB stack so its shared across ports. This has led to a number of changes that remove items from the ports folder and move them into supervisor. Furthermore, we had external SPI flash support for nrf pending so I factored out the connection between the usb stack and the flash API as well. This PR also includes the QSPI support for nRF.
233 lines
7.8 KiB
C
233 lines
7.8 KiB
C
/*
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* This file is part of the MicroPython project, http://micropython.org/
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2016, 2017 Scott Shawcroft for Adafruit Industries
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "supervisor/spi_flash_api.h"
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#include <stdint.h>
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#include <string.h>
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#include "mpconfigboard.h" // for EXTERNAL_FLASH_QSPI_DUAL
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#include "supervisor/shared/external_flash/common_commands.h"
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#include "supervisor/shared/external_flash/qspi_flash.h"
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#include "samd/cache.h"
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#include "samd/dma.h"
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#include "atmel_start_pins.h"
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#include "hal_gpio.h"
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bool spi_flash_command(uint8_t command) {
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QSPI->INSTRCTRL.bit.INSTR = command;
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QSPI->INSTRFRAME.reg = QSPI_INSTRFRAME_WIDTH_SINGLE_BIT_SPI |
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QSPI_INSTRFRAME_ADDRLEN_24BITS |
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QSPI_INSTRFRAME_TFRTYPE_READ |
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QSPI_INSTRFRAME_INSTREN;
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QSPI->CTRLA.reg = QSPI_CTRLA_ENABLE | QSPI_CTRLA_LASTXFER;
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while( !QSPI->INTFLAG.bit.INSTREND );
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QSPI->INTFLAG.reg = QSPI_INTFLAG_INSTREND;
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return true;
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}
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bool spi_flash_read_command(uint8_t command, uint8_t* response, uint32_t length) {
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samd_peripherals_disable_and_clear_cache();
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QSPI->INSTRCTRL.bit.INSTR = command;
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QSPI->INSTRFRAME.reg = QSPI_INSTRFRAME_WIDTH_SINGLE_BIT_SPI |
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QSPI_INSTRFRAME_ADDRLEN_24BITS |
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QSPI_INSTRFRAME_TFRTYPE_READ |
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QSPI_INSTRFRAME_INSTREN |
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QSPI_INSTRFRAME_DATAEN;
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// Dummy read of INSTRFRAME needed to synchronize.
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// See Instruction Transmission Flow Diagram, figure 37.9, page 995
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// and Example 4, page 998, section 37.6.8.5.
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(volatile uint32_t) QSPI->INSTRFRAME.reg;
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memcpy(response, (uint8_t *) QSPI_AHB, length);
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QSPI->CTRLA.reg = QSPI_CTRLA_ENABLE | QSPI_CTRLA_LASTXFER;
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while( !QSPI->INTFLAG.bit.INSTREND );
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QSPI->INTFLAG.reg = QSPI_INTFLAG_INSTREND;
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samd_peripherals_enable_cache();
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return true;
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}
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bool spi_flash_write_command(uint8_t command, uint8_t* data, uint32_t length) {
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samd_peripherals_disable_and_clear_cache();
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QSPI->INSTRCTRL.bit.INSTR = command;
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QSPI->INSTRFRAME.reg = QSPI_INSTRFRAME_WIDTH_SINGLE_BIT_SPI |
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QSPI_INSTRFRAME_ADDRLEN_24BITS |
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QSPI_INSTRFRAME_TFRTYPE_WRITE |
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QSPI_INSTRFRAME_INSTREN |
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(data != NULL ? QSPI_INSTRFRAME_DATAEN : 0);
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// Dummy read of INSTRFRAME needed to synchronize.
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// See Instruction Transmission Flow Diagram, figure 37.9, page 995
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// and Example 4, page 998, section 37.6.8.5.
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(volatile uint32_t) QSPI->INSTRFRAME.reg;
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if (data != NULL) {
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memcpy((uint8_t *) QSPI_AHB, data, length);
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}
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QSPI->CTRLA.reg = QSPI_CTRLA_ENABLE | QSPI_CTRLA_LASTXFER;
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while( !QSPI->INTFLAG.bit.INSTREND );
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QSPI->INTFLAG.reg = QSPI_INTFLAG_INSTREND;
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samd_peripherals_enable_cache();
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return true;
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}
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bool spi_flash_sector_command(uint8_t command, uint32_t address) {
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QSPI->INSTRCTRL.bit.INSTR = command;
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QSPI->INSTRADDR.bit.ADDR = address;
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QSPI->INSTRFRAME.reg = QSPI_INSTRFRAME_WIDTH_SINGLE_BIT_SPI |
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QSPI_INSTRFRAME_ADDRLEN_24BITS |
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QSPI_INSTRFRAME_TFRTYPE_WRITE |
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QSPI_INSTRFRAME_INSTREN |
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QSPI_INSTRFRAME_ADDREN;
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QSPI->CTRLA.reg = QSPI_CTRLA_ENABLE | QSPI_CTRLA_LASTXFER;
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while( !QSPI->INTFLAG.bit.INSTREND );
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QSPI->INTFLAG.reg = QSPI_INTFLAG_INSTREND;
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return true;
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}
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bool spi_flash_write_data(uint32_t address, uint8_t* data, uint32_t length) {
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samd_peripherals_disable_and_clear_cache();
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QSPI->INSTRCTRL.bit.INSTR = CMD_PAGE_PROGRAM;
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uint32_t mode = QSPI_INSTRFRAME_WIDTH_SINGLE_BIT_SPI;
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QSPI->INSTRFRAME.reg = mode |
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QSPI_INSTRFRAME_ADDRLEN_24BITS |
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QSPI_INSTRFRAME_TFRTYPE_WRITEMEMORY |
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QSPI_INSTRFRAME_INSTREN |
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QSPI_INSTRFRAME_ADDREN |
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QSPI_INSTRFRAME_DATAEN;
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memcpy(((uint8_t *) QSPI_AHB) + address, data, length);
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// TODO(tannewt): Fix DMA and enable it.
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// qspi_dma_write(address, data, length);
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QSPI->CTRLA.reg = QSPI_CTRLA_ENABLE | QSPI_CTRLA_LASTXFER;
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while( !QSPI->INTFLAG.bit.INSTREND );
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QSPI->INTFLAG.reg = QSPI_INTFLAG_INSTREND;
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samd_peripherals_enable_cache();
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return true;
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}
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bool spi_flash_read_data(uint32_t address, uint8_t* data, uint32_t length) {
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samd_peripherals_disable_and_clear_cache();
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#ifdef EXTERNAL_FLASH_QSPI_DUAL
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QSPI->INSTRCTRL.bit.INSTR = CMD_DUAL_READ;
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uint32_t mode = QSPI_INSTRFRAME_WIDTH_DUAL_OUTPUT;
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#else
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QSPI->INSTRCTRL.bit.INSTR = CMD_QUAD_READ;
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uint32_t mode = QSPI_INSTRFRAME_WIDTH_QUAD_OUTPUT;
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#endif
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QSPI->INSTRFRAME.reg = mode |
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QSPI_INSTRFRAME_ADDRLEN_24BITS |
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QSPI_INSTRFRAME_TFRTYPE_READMEMORY |
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QSPI_INSTRFRAME_INSTREN |
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QSPI_INSTRFRAME_ADDREN |
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QSPI_INSTRFRAME_DATAEN |
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QSPI_INSTRFRAME_DUMMYLEN(8);
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memcpy(data, ((uint8_t *) QSPI_AHB) + address, length);
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// TODO(tannewt): Fix DMA and enable it.
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// qspi_dma_read(address, data, length);
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QSPI->CTRLA.reg = QSPI_CTRLA_ENABLE | QSPI_CTRLA_LASTXFER;
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while( !QSPI->INTFLAG.bit.INSTREND );
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QSPI->INTFLAG.reg = QSPI_INTFLAG_INSTREND;
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samd_peripherals_enable_cache();
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return true;
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}
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void spi_flash_init(void) {
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MCLK->APBCMASK.bit.QSPI_ = true;
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MCLK->AHBMASK.bit.QSPI_ = true;
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MCLK->AHBMASK.bit.QSPI_2X_ = false; // Only true if we are doing DDR.
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QSPI->CTRLA.reg = QSPI_CTRLA_SWRST;
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// We don't need to wait because we're running as fast as the CPU.
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// Slow, good for debugging with Saleae
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// QSPI->BAUD.bit.BAUD = 32;
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// Super fast, may be unreliable when Saleae is connected to high speed lines.
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QSPI->BAUD.bit.BAUD = 2;
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QSPI->CTRLB.reg = QSPI_CTRLB_MODE_MEMORY | // Serial memory mode (map to QSPI_AHB)
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QSPI_CTRLB_DATALEN_8BITS |
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QSPI_CTRLB_CSMODE_LASTXFER;
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QSPI->CTRLA.reg = QSPI_CTRLA_ENABLE;
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// The QSPI is only connected to one set of pins in the SAMD51 so we can hard code it.
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uint32_t pins[6] = {PIN_PA08, PIN_PA09, PIN_PA10, PIN_PA11, PIN_PB10, PIN_PB11};
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for (uint8_t i = 0; i < 6; i++) {
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gpio_set_pin_direction(pins[i], GPIO_DIRECTION_IN);
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gpio_set_pin_pull_mode(pins[i], GPIO_PULL_OFF);
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gpio_set_pin_function(pins[i], GPIO_PIN_FUNCTION_H);
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}
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}
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void spi_flash_init_device(const external_flash_device* device) {
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check_quad_enable(device);
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// TODO(tannewt): Adjust the speed for the found device.
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}
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