231 lines
6.1 KiB
C
231 lines
6.1 KiB
C
/**
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* \file
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*
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* \brief SAM DMA cyclic redundancy check (CRC) Driver
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*
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* Copyright (C) 2014-2015 Atmel Corporation. All rights reserved.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. The name of Atmel may not be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* 4. This software may only be redistributed and used in connection with an
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* Atmel microcontroller product.
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*
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* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* \asf_license_stop
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*
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*/
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/*
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* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
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*/
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#ifndef DMA_CRC_H_INCLUDED
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#define DMA_CRC_H_INCLUDED
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#include <compiler.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** DMA channel n offset. */
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#define DMA_CRC_CHANNEL_N_OFFSET 0x20
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/** CRC Polynomial Type. */
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enum crc_polynomial_type {
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/** CRC16 (CRC-CCITT). */
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CRC_TYPE_16,
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/** CRC32 (IEEE 802.3). */
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CRC_TYPE_32,
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};
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/** CRC Beat Type. */
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enum crc_beat_size {
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/** Byte bus access. */
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CRC_BEAT_SIZE_BYTE,
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/** Half-word bus access. */
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CRC_BEAT_SIZE_HWORD,
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/** Word bus access. */
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CRC_BEAT_SIZE_WORD,
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};
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/** Configurations for CRC calculation. */
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struct dma_crc_config {
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/** CRC polynomial type. */
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enum crc_polynomial_type type;
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/** CRC beat size. */
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enum crc_beat_size size;
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};
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/**
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* \brief Get DMA CRC default configurations.
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*
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* The default configuration is as follows:
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* \li Polynomial type is set to CRC-16(CRC-CCITT)
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* \li CRC Beat size: BYTE
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*
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* \param[in] config default configurations
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*/
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static inline void dma_crc_get_config_defaults(struct dma_crc_config *config)
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{
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Assert(config);
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config->type = CRC_TYPE_16;
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config->size = CRC_BEAT_SIZE_BYTE;
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}
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/**
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* \brief Enable DMA CRC module with an DMA channel.
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*
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* This function enables a CRC calculation with an allocated DMA channel. This channel ID
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* can be gotten from a successful \ref dma_allocate.
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*
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* \param[in] channel_id DMA channel expected with CRC calculation
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* \param[in] config CRC calculation configurations
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*
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* \return Status of the DMC CRC.
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* \retval STATUS_OK Get the DMA CRC module
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* \retval STATUS_BUSY DMA CRC module is already taken and not ready yet
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*/
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static inline enum status_code dma_crc_channel_enable(uint32_t channel_id,
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struct dma_crc_config *config)
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{
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if (DMAC->CRCSTATUS.reg & DMAC_CRCSTATUS_CRCBUSY) {
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return STATUS_BUSY;
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}
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DMAC->CRCCTRL.reg = DMAC_CRCCTRL_CRCBEATSIZE(config->size) |
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DMAC_CRCCTRL_CRCPOLY(config->type) |
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DMAC_CRCCTRL_CRCSRC(channel_id+DMA_CRC_CHANNEL_N_OFFSET);
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DMAC->CTRL.reg |= DMAC_CTRL_CRCENABLE;
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return STATUS_OK;
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}
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/**
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* \brief Disable DMA CRC module.
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*
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*/
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static inline void dma_crc_disable(void)
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{
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DMAC->CTRL.reg &= ~DMAC_CTRL_CRCENABLE;
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DMAC->CRCCTRL.reg = 0;
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}
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/**
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* \brief Get DMA CRC checksum value.
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*
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* \return Calculated CRC checksum.
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*/
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static inline uint32_t dma_crc_get_checksum(void)
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{
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if (DMAC->CRCCTRL.bit.CRCSRC == DMAC_CRCCTRL_CRCSRC_IO_Val) {
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DMAC->CRCSTATUS.reg = DMAC_CRCSTATUS_CRCBUSY;
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}
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return DMAC->CRCCHKSUM.reg;
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}
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/**
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* \brief Enable DMA CRC module with I/O.
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*
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* This function enables a CRC calculation with I/O mode.
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*
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* \param[in] config CRC calculation configurations.
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*
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* \return Status of the DMC CRC.
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* \retval STATUS_OK Get the DMA CRC module
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* \retval STATUS_BUSY DMA CRC module is already taken and not ready yet
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*/
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static inline enum status_code dma_crc_io_enable(
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struct dma_crc_config *config)
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{
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if (DMAC->CRCSTATUS.reg & DMAC_CRCSTATUS_CRCBUSY) {
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return STATUS_BUSY;
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}
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if (DMAC->CTRL.reg & DMAC_CTRL_CRCENABLE) {
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return STATUS_BUSY;
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}
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DMAC->CRCCTRL.reg = DMAC_CRCCTRL_CRCBEATSIZE(config->size) |
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DMAC_CRCCTRL_CRCPOLY(config->type) |
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DMAC_CRCCTRL_CRCSRC_IO;
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if (config->type == CRC_TYPE_32) {
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DMAC->CRCCHKSUM.reg = 0xFFFFFFFF;
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}
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DMAC->CTRL.reg |= DMAC_CTRL_CRCENABLE;
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return STATUS_OK;
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}
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/**
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* \brief Calculate CRC with I/O.
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*
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* This function calculate the CRC of the input data buffer.
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*
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* \param[in] buffer CRC Pointer to calculation buffer
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* \param[in] total_beat_size Total beat size to be calculated
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*
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* \return Calculated CRC checksum value.
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*/
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static inline void dma_crc_io_calculation(void *buffer,
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uint32_t total_beat_size)
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{
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uint32_t counter = total_beat_size;
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uint8_t *buffer_8;
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uint16_t *buffer_16;
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uint32_t *buffer_32;
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for (counter=0; counter<total_beat_size; counter++) {
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if (DMAC->CRCCTRL.bit.CRCBEATSIZE == CRC_BEAT_SIZE_BYTE) {
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buffer_8 = buffer;
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DMAC->CRCDATAIN.reg = buffer_8[counter];
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} else if (DMAC->CRCCTRL.bit.CRCBEATSIZE == CRC_BEAT_SIZE_HWORD) {
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buffer_16 = buffer;
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DMAC->CRCDATAIN.reg = buffer_16[counter];
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} else if (DMAC->CRCCTRL.bit.CRCBEATSIZE == CRC_BEAT_SIZE_WORD) {
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buffer_32 = buffer;
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DMAC->CRCDATAIN.reg = buffer_32[counter];
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}
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/* Wait several cycle to make sure CRC complete */
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nop();
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nop();
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nop();
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nop();
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}
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}
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#ifdef __cplusplus
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}
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#endif
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#endif /* DMA_CRC_H_INCLUDED */
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