def719e7a7
There were several different spellings of MicroPython present in comments,
when there should be only one.
Aligning to upstream commit 55f33240f3.
123 lines
5.0 KiB
C
123 lines
5.0 KiB
C
/*
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* This file is part of the MicroPython project, http://micropython.org/
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2017 Glenn Ruben Bakke
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "mphalport.h"
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#include "hal_qspie.h"
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#ifdef HAL_QSPIE_MODULE_ENABLED
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#define QSPI_IRQ_NUM QSPI_IRQn
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#define QSPI_BASE ((NRF_QSPI_Type *)NRF_QSPI_BASE)
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// frequency, 32 MHz / (SCKFREQ + 1)
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static const uint32_t hal_qspi_frequency_lookup[] = {
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(15 << QSPI_IFCONFIG1_SCKFREQ_Pos), // 2 Mbps
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(7 << QSPI_IFCONFIG1_SCKFREQ_Pos), // 4 Mbps
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(3 << QSPI_IFCONFIG1_SCKFREQ_Pos), // 8 Mbps
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(1 << QSPI_IFCONFIG1_SCKFREQ_Pos), // 16 Mbps
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(0 << QSPI_IFCONFIG1_SCKFREQ_Pos), // 32 Mbps
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};
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void hal_qspi_master_init(NRF_QSPI_Type * p_instance, hal_qspi_init_t const * p_qspi_init)
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{
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// configure SCK
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p_instance->PSEL.SCK = (p_qspi_init->clk_pin << QSPI_PSEL_SCK_PIN_Pos)
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| (p_qspi_init->clk_pin_port << QSPI_PSEL_SCK_PORT_Pos)
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| (QSPI_PSEL_SCK_CONNECT_Connected << QSPI_PSEL_SCK_CONNECT_Pos);
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// configure CS
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if (p_qspi_init->use_csn) {
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p_instance->PSEL.CSN = (p_qspi_init->clk_pin << QSPI_PSEL_CSN_PIN_Pos)
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| (p_qspi_init->clk_pin_port << QSPI_PSEL_CSN_PORT_Pos)
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| (QSPI_PSEL_CSN_CONNECT_Connected << QSPI_PSEL_CSN_CONNECT_Pos);
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} else {
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p_instance->PSEL.CSN = (QSPI_PSEL_CSN_CONNECT_Disconnected << QSPI_PSEL_CSN_CONNECT_Pos);
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}
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// configure MOSI/IO0, valid for all configurations
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p_instance->PSEL.IO0 = (p_qspi_init->d0_mosi_pin << QSPI_PSEL_IO0_PIN_Pos)
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| (p_qspi_init->d0_mosi_pin_port << QSPI_PSEL_IO0_PORT_Pos)
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| (QSPI_PSEL_IO0_CONNECT_Connected << QSPI_PSEL_IO0_CONNECT_Pos);
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if (p_qspi_init->data_line != HAL_QSPI_DATA_LINE_SINGLE) {
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// configure MISO/IO1
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p_instance->PSEL.IO1 = (p_qspi_init->d1_miso_pin << QSPI_PSEL_IO1_PIN_Pos)
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| (p_qspi_init->d1_miso_pin_port << QSPI_PSEL_IO1_PORT_Pos)
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| (QSPI_PSEL_IO1_CONNECT_Connected << QSPI_PSEL_IO1_CONNECT_Pos);
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if (p_qspi_init->data_line == HAL_QSPI_DATA_LINE_QUAD) {
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// configure IO2
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p_instance->PSEL.IO2 = (p_qspi_init->d2_pin << QSPI_PSEL_IO2_PIN_Pos)
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| (p_qspi_init->d2_pin_port << QSPI_PSEL_IO2_PORT_Pos)
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| (QSPI_PSEL_IO2_CONNECT_Connected << QSPI_PSEL_IO2_CONNECT_Pos);
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// configure IO3
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p_instance->PSEL.IO3 = (p_qspi_init->d3_pin << QSPI_PSEL_IO3_PIN_Pos)
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| (p_qspi_init->d3_pin_port << QSPI_PSEL_IO3_PORT_Pos)
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| (QSPI_PSEL_IO3_CONNECT_Connected << QSPI_PSEL_IO3_CONNECT_Pos);
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}
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}
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uint32_t mode;
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switch (p_qspi_init->mode) {
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case HAL_SPI_MODE_CPOL0_CPHA0:
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mode = (QSPI_IFCONFIG1_SPIMODE_MODE0 << QSPI_IFCONFIG1_SPIMODE_Pos);
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break;
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case HAL_SPI_MODE_CPOL1_CPHA1:
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mode = (QSPI_IFCONFIG1_SPIMODE_MODE3 << QSPI_IFCONFIG1_SPIMODE_Pos);
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break;
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default:
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mode = 0;
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break;
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}
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// interface config1
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p_instance->IFCONFIG1 = hal_qspi_frequency_lookup[p_qspi_init->freq]
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| mode
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| (1 << QSPI_IFCONFIG1_SCKDELAY_Pos); // number of 16 MHz periods (62.5 ns)
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p_instance->ENABLE = 1;
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}
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void hal_qspi_master_tx_rx(NRF_QSPI_Type * p_instance,
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uint16_t transfer_size,
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const uint8_t * tx_data,
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uint8_t * rx_data)
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{
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p_instance->READ.DST = (uint32_t)rx_data;
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p_instance->READ.CNT = transfer_size;
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p_instance->READ.SRC = (uint32_t)tx_data;
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p_instance->READ.CNT = transfer_size;
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p_instance->TASKS_ACTIVATE = 1;
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while (p_instance->EVENTS_READY == 0) {
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;
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}
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p_instance->TASKS_ACTIVATE = 0;
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}
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#endif // HAL_QSPIE_MODULE_ENABLED
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