dd38d90724
This compiles and links, but hasn't been tested on a board yet and even if it was run, it doesn't currently do anything.
875 lines
46 KiB
C
875 lines
46 KiB
C
/**
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******************************************************************************
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* @file stm32f4xx_hal_rcc_ex.h
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* @author MCD Application Team
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* @version V1.0.0
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* @date 18-February-2014
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* @brief Header file of RCC HAL Extension module.
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of STMicroelectronics nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __STM32F4xx_HAL_RCC_EX_H
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#define __STM32F4xx_HAL_RCC_EX_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f4xx_hal_def.h"
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/** @addtogroup STM32F4xx_HAL_Driver
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* @{
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*/
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/** @addtogroup RCCEx
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* @{
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*/
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/* Exported types ------------------------------------------------------------*/
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#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
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/**
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* @brief PLLI2S Clock structure definition
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*/
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typedef struct
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{
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uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock
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This parameter must be a number between Min_Data = 192 and Max_Data = 432
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This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
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uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock
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This parameter must be a number between Min_Data = 2 and Max_Data = 7
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This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
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uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI1 clock.
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This parameter must be a number between Min_Data = 2 and Max_Data = 15
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This parameter will be used only when PLLI2S is selected as Clock Source SAI */
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}RCC_PLLI2SInitTypeDef;
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/**
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* @brief PLLSAI Clock structure definition
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*/
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typedef struct
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{
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uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
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This parameter must be a number between Min_Data = 192 and Max_Data = 432
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This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
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uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI1 clock.
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This parameter must be a number between Min_Data = 2 and Max_Data = 15
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This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
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uint32_t PLLSAIR; /*!< specifies the division factor for LTDC clock
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This parameter must be a number between Min_Data = 2 and Max_Data = 7
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This parameter will be used only when PLLSAI is selected as Clock Source LTDC */
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}RCC_PLLSAIInitTypeDef;
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/**
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* @brief RCC extended clocks structure definition
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*/
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typedef struct
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{
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uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
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This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
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RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters
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This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
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RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters
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This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */
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uint32_t PLLI2SDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock
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This parameter must be a number between Min_Data = 1 and Max_Data = 32
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This parameter will be used only when PLLI2S is selected as Clock Source SAI */
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uint32_t PLLSAIDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
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This parameter must be a number between Min_Data = 1 and Max_Data = 32
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This parameter will be used only when PLLSAI is selected as Clock Source SAI */
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uint32_t PLLSAIDivR; /*!< Specifies the PLLSAI division factor for LTDC clock.
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This parameter must be one value of @ref RCCEx_PLLSAI_DIVR */
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uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
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This parameter can be a value of @ref RCC_RTC_Clock_Source */
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uint8_t TIMPresSelection; /*!< Specifies TIM Clock Prescalers Selection
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This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
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}RCC_PeriphCLKInitTypeDef;
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#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
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#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) || defined(STM32F401xC) || defined(STM32F401xE)
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/**
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* @brief PLLI2S Clock structure definition
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*/
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typedef struct
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{
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uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock
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This parameter must be a number between Min_Data = 192 and Max_Data = 432
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This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
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uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock
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This parameter must be a number between Min_Data = 2 and Max_Data = 7
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This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
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}RCC_PLLI2SInitTypeDef;
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/**
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* @brief RCC extended clocks structure definition
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*/
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typedef struct
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{
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uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
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This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
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RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters
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This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
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uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
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This parameter can be a value of @ref RCC_RTC_Clock_Source */
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}RCC_PeriphCLKInitTypeDef;
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#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE */
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/* Exported constants --------------------------------------------------------*/
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/** @defgroup RCCEx_Exported_Constants
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* @{
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*/
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/** @defgroup RCCEx_Periph_Clock_Selection
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* @{
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*/
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#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
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#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001)
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#define RCC_PERIPHCLK_SAI_PLLI2S ((uint32_t)0x00000002)
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#define RCC_PERIPHCLK_SAI_PLLSAI ((uint32_t)0x00000004)
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#define RCC_PERIPHCLK_LTDC ((uint32_t)0x00000008)
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#define RCC_PERIPHCLK_TIM ((uint32_t)0x00000010)
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#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020)
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#define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x0000002F))
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#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
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#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) || defined(STM32F401xC) || defined(STM32F401xE)
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#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001)
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#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000002)
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#define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x00000003))
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#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE */
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/**
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* @}
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*/
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/** @defgroup RCCEx_BitAddress_AliasRegion
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* @brief RCC registers bit address in the alias region
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* @{
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*/
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/* --- CR Register ---*/
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#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
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/* Alias word address of PLLSAION bit */
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#define PLLSAION_BitNumber 0x1C
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#define CR_PLLSAION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (PLLSAION_BitNumber * 4))
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/* --- DCKCFGR Register ---*/
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/* Alias word address of TIMPRE bit */
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#define RCC_DCKCFGR_OFFSET (RCC_OFFSET + 0x8C)
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#define TIMPRE_BitNumber 0x18
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#define DCKCFGR_TIMPRE_BB (PERIPH_BB_BASE + (RCC_DCKCFGR_OFFSET * 32) + (TIMPRE_BitNumber * 4))
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/**
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* @}
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*/
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/** @defgroup RCCEx_PLLI2S_Clock_Source
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* @{
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*/
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#define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
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/**
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* @}
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*/
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/** @defgroup RCCEx_PLLSAI_Clock_Source
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* @{
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*/
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#define IS_RCC_PLLSAIN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
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#define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
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#define IS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
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/**
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* @}
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*/
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/** @defgroup RCCEx_PLLSAI_DIVQ
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* @{
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*/
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#define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
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/**
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* @}
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*/
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/** @defgroup RCCEx_PLLI2S_DIVQ
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* @{
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*/
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#define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
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/**
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* @}
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*/
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/** @defgroup RCCEx_PLLSAI_DIVR
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* @{
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*/
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#define RCC_PLLSAIDIVR_2 ((uint32_t)0x00000000)
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#define RCC_PLLSAIDIVR_4 ((uint32_t)0x00010000)
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#define RCC_PLLSAIDIVR_8 ((uint32_t)0x00020000)
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#define RCC_PLLSAIDIVR_16 ((uint32_t)0x00030000)
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#define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDIVR_2) ||\
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((VALUE) == RCC_PLLSAIDIVR_4) ||\
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((VALUE) == RCC_PLLSAIDIVR_8) ||\
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((VALUE) == RCC_PLLSAIDIVR_16))
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/**
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* @}
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*/
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/** @defgroup RCCEx_SAI_BlockA_Clock_Source
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* @{
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*/
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#define RCC_SAIACLKSOURCE_PLLSAI ((uint32_t)0x00000000)
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#define RCC_SAIACLKSOURCE_PLLI2S ((uint32_t)0x00100000)
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#define RCC_SAIACLKSOURCE_EXT ((uint32_t)0x00200000)
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/**
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* @}
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*/
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/** @defgroup RCCEx_SAI_BlockB_Clock_Source
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* @{
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*/
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#define RCC_SAIBCLKSOURCE_PLLSAI ((uint32_t)0x00000000)
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#define RCC_SAIBCLKSOURCE_PLLI2S ((uint32_t)0x00400000)
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#define RCC_SAIBCLKSOURCE_EXT ((uint32_t)0x00800000)
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/**
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* @}
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*/
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/** @defgroup RCCEx_TIM_PRescaler_Selection
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* @{
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*/
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#define RCC_TIMPRES_DESACTIVATED ((uint8_t)0x00)
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#define RCC_TIMPRES_ACTIVATED ((uint8_t)0x01)
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/**
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* @}
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*/
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#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
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/**
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* @}
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*/
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/**
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* @}
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*/
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/* Exported macro ------------------------------------------------------------*/
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/** @brief Enables or disables the AHB1 peripheral clock.
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* @note After reset, the peripheral clock (used for registers read/write access)
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* is disabled and the application software has to enable this clock before
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* using it.
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*/
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#if !defined(STM32F401xC) && !defined(STM32F401xE)
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#define __GPIOI_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOIEN))
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#define __GPIOF_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOFEN))
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#define __GPIOG_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOGEN))
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#define __ETHMAC_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACEN))
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#define __ETHMACTX_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACTXEN))
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#define __ETHMACRX_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACRXEN))
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#define __ETHMACPTP_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACPTPEN))
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#define __USB_OTG_HS_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_OTGHSEN))
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#define __USB_OTG_HS_ULPI_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_OTGHSULPIEN))
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#define __GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
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#define __GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
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#define __GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
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#define __ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
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#define __ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
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#define __ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
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#define __ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))
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#define __USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
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#define __USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
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#endif /* !(STM32F401xC && STM32F401xE) */
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#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
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#define __GPIOJ_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOJEN))
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#define __GPIOK_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOKEN))
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#define __DMA2D_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_DMA2DEN))
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#define __GPIOJ_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOJEN))
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#define __GPIOK_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOKEN))
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#define __DMA2D_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2DEN))
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#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */
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#if !defined(STM32F401xC) && !defined(STM32F401xE)
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/**
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* @brief Enable ETHERNET clock.
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*/
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#define __ETH_CLK_ENABLE() do { \
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__ETHMAC_CLK_ENABLE(); \
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__ETHMACTX_CLK_ENABLE(); \
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__ETHMACRX_CLK_ENABLE(); \
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} while(0)
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/**
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* @brief Disable ETHERNET clock.
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*/
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#define __ETH_CLK_DISABLE() do { \
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__ETHMACTX_CLK_DISABLE(); \
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__ETHMACRX_CLK_DISABLE(); \
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__ETHMAC_CLK_DISABLE(); \
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} while(0)
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#endif /* !(STM32F401xC && STM32F401xE) */
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/** @brief Enable or disable the AHB2 peripheral clock.
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* @note After reset, the peripheral clock (used for registers read/write access)
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* is disabled and the application software has to enable this clock before
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* using it.
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*/
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#if !defined(STM32F401xC) && !defined(STM32F401xE)
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#define __DCMI_CLK_ENABLE() (RCC->AHB2ENR |= (RCC_AHB2ENR_DCMIEN))
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#define __DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
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#endif /* !(STM32F401xC && STM32F401xE) */
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#if defined(STM32F415xx) || defined(STM32F417xx) || defined(STM32F437xx)|| defined(STM32F439xx)
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#define __CRYP_CLK_ENABLE() (RCC->AHB2ENR |= (RCC_AHB2ENR_CRYPEN))
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#define __HASH_CLK_ENABLE() (RCC->AHB2ENR |= (RCC_AHB2ENR_HASHEN))
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#define __CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
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#define __HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
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#endif /* STM32F415xx || STM32F417xx || STM32F437xx || STM32F439xx */
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/** @brief Enables or disables the AHB3 peripheral clock.
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* @note After reset, the peripheral clock (used for registers read/write access)
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* is disabled and the application software has to enable this clock before
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* using it.
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*/
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#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
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#define __FSMC_CLK_ENABLE() (RCC->AHB3ENR |= (RCC_AHB3ENR_FSMCEN))
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#define __FSMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FSMCEN))
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#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
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#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
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#define __FMC_CLK_ENABLE() (RCC->AHB3ENR |= (RCC_AHB3ENR_FMCEN))
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#define __FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))
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#endif /* STM32F415xx || STM32F417xx || STM32F437xx || STM32F439xx */
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/** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
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* @note After reset, the peripheral clock (used for registers read/write access)
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* is disabled and the application software has to enable this clock before
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* using it.
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*/
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#if !defined(STM32F401xC) && !defined(STM32F401xE)
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#define __TIM6_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM6EN))
|
|
#define __TIM7_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM7EN))
|
|
#define __TIM12_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM12EN))
|
|
#define __TIM13_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM13EN))
|
|
#define __TIM14_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM14EN))
|
|
#define __WWDG_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_WWDGEN))
|
|
#define __USART3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART3EN))
|
|
#define __UART4_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_UART4EN))
|
|
#define __UART5_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_UART5EN))
|
|
#define __CAN1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_CAN1EN))
|
|
#define __CAN2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_CAN2EN))
|
|
#define __DAC_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_DACEN))
|
|
|
|
#define __TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
|
|
#define __TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
|
|
#define __TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
|
|
#define __TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
|
|
#define __TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
|
|
#define __WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
|
|
#define __USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
|
|
#define __UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
|
|
#define __UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
|
|
#define __CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
|
|
#define __CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
|
|
#define __DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
|
|
#endif /* !(STM32F401xC && STM32F401xE) */
|
|
|
|
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
|
|
#define __UART7_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_UART7EN))
|
|
#define __UART8_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_UART8EN))
|
|
|
|
#define __UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN))
|
|
#define __UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN))
|
|
#endif /* STM32F415xx || STM32F417xx || STM32F437xx || STM32F439xx */
|
|
|
|
/** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
|
|
* @note After reset, the peripheral clock (used for registers read/write access)
|
|
* is disabled and the application software has to enable this clock before
|
|
* using it.
|
|
*/
|
|
#if !defined(STM32F401xC) && !defined(STM32F401xE)
|
|
#define __TIM8_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM8EN))
|
|
#define __ADC2_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_ADC2EN))
|
|
#define __ADC3_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_ADC3EN))
|
|
|
|
#define __TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
|
|
#define __ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
|
|
#define __ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
|
|
#endif /* !(STM32F401xC && STM32F401xE) */
|
|
|
|
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
|
|
#define __SPI5_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SPI5EN))
|
|
#define __SPI6_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SPI6EN))
|
|
#define __SAI1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SAI1EN))
|
|
#define __LTDC_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_LTDCEN))
|
|
|
|
#define __SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
|
|
#define __SPI6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN))
|
|
#define __SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))
|
|
#define __LTDC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_LTDCEN))
|
|
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
|
|
|
|
/** @brief Force or release AHB1 peripheral reset.
|
|
*/
|
|
#if !defined(STM32F401xC) && !defined(STM32F401xE)
|
|
#define __GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST))
|
|
#define __GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST))
|
|
#define __GPIOI_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST))
|
|
#define __ETHMAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST))
|
|
#define __OTGHS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST))
|
|
|
|
#define __GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
|
|
#define __GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
|
|
#define __GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
|
|
#define __ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
|
|
#define __OTGHS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
|
|
#endif /* !STM32F401xC && STM32F401xE */
|
|
|
|
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
|
|
#define __GPIOJ_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOJRST))
|
|
#define __GPIOK_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOKRST))
|
|
#define __DMA2D_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2DRST))
|
|
|
|
#define __GPIOJ_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOJRST))
|
|
#define __GPIOK_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOKRST))
|
|
#define __DMA2D_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2DRST))
|
|
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
|
|
|
|
/** @brief Force or release AHB2 peripheral reset.
|
|
*/
|
|
#if !defined(STM32F401xC) && !defined(STM32F401xE)
|
|
#define __DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))
|
|
#define __DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
|
|
#endif /* !STM32F401xC && STM32F401xE */
|
|
|
|
#if defined(STM32F415xx) || defined(STM32F417xx) || defined(STM32F437xx)|| defined(STM32F439xx)
|
|
#define __CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST))
|
|
#define __HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST))
|
|
|
|
#define __CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))
|
|
#define __HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))
|
|
|
|
#endif /* STM32F415xx || STM32F417xx || STM32F437xx || STM32F439xx */
|
|
|
|
/** @brief Force or release AHB3 peripheral reset
|
|
*/
|
|
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
|
|
#define __FSMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FSMCRST))
|
|
#define __FSMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FSMCRST))
|
|
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
|
|
|
|
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
|
|
#define __FMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST))
|
|
#define __FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST))
|
|
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
|
|
|
|
/** @brief Force or release APB1 peripheral reset.
|
|
*/
|
|
#if !defined(STM32F401xC) && !defined(STM32F401xE)
|
|
#define __TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
|
|
#define __TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
|
|
#define __TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
|
|
#define __TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
|
|
#define __TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
|
|
#define __USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
|
|
#define __UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
|
|
#define __UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
|
|
#define __CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))
|
|
#define __CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))
|
|
#define __DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
|
|
|
|
#define __TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
|
|
#define __TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
|
|
#define __TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
|
|
#define __TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
|
|
#define __TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
|
|
#define __USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
|
|
#define __UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
|
|
#define __UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
|
|
#define __CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
|
|
#define __CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
|
|
#define __DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
|
|
#endif /* !STM32F401xC && STM32F401xE */
|
|
|
|
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
|
|
#define __UART7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART7RST))
|
|
#define __UART8_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART8RST))
|
|
|
|
#define __UART7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST))
|
|
#define __UART8_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST))
|
|
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
|
|
|
|
/** @brief Force or release APB2 peripheral reset.
|
|
*/
|
|
#if !defined(STM32F401xC) && !defined(STM32F401xE)
|
|
#define __TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
|
|
#define __TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
|
|
#endif /* !STM32F401xC && STM32F401xE */
|
|
|
|
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
|
|
#define __SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST))
|
|
#define __SPI6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI6RST))
|
|
#define __SAI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST))
|
|
#define __LTDC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_LTDCRST))
|
|
|
|
#define __SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
|
|
#define __SPI6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST))
|
|
#define __SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))
|
|
#define __LTDC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_LTDCRST))
|
|
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
|
|
|
|
|
|
/** @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
|
|
* @note Peripheral clock gating in SLEEP mode can be used to further reduce
|
|
* power consumption.
|
|
* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
|
|
* @note By default, all peripheral clocks are enabled during SLEEP mode.
|
|
*/
|
|
#if !defined(STM32F401xC) && !defined(STM32F401xE)
|
|
#define __GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN))
|
|
#define __GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN))
|
|
#define __GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN))
|
|
#define __SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN))
|
|
#define __ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN))
|
|
#define __ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN))
|
|
#define __ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN))
|
|
#define __ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN))
|
|
#define __OTGHS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN))
|
|
#define __OTGHSULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN))
|
|
|
|
#define __GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
|
|
#define __GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
|
|
#define __GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))
|
|
#define __SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
|
|
#define __ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))
|
|
#define __ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
|
|
#define __ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
|
|
#define __ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
|
|
#define __OTGHS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
|
|
#define __OTGHSULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
|
|
#endif /* !STM32F401xC && STM32F401xE */
|
|
|
|
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
|
|
#define __GPIOJ_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOJLPEN))
|
|
#define __GPIOK_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOKLPEN))
|
|
#define __SRAM3_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM3LPEN))
|
|
#define __DMA2D_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2DLPEN))
|
|
|
|
#define __GPIOJ_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOJLPEN))
|
|
#define __GPIOK_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOKLPEN))
|
|
#define __DMA2D_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2DLPEN))
|
|
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
|
|
|
|
/** @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
|
|
* @note Peripheral clock gating in SLEEP mode can be used to further reduce
|
|
* power consumption.
|
|
* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
|
|
* @note By default, all peripheral clocks are enabled during SLEEP mode.
|
|
*/
|
|
#if !defined(STM32F401xC) && !defined(STM32F401xE)
|
|
#define __DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
|
|
#define __DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
|
|
#endif /* !STM32F401xC && STM32F401xE */
|
|
|
|
#if defined(STM32F415xx) || defined(STM32F417xx) || defined(STM32F437xx)|| defined(STM32F439xx)
|
|
#define __CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))
|
|
#define __HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))
|
|
|
|
#define __CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))
|
|
#define __HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))
|
|
|
|
#endif /* STM32F415xx || STM32F417xx || STM32F437xx || STM32F439xx */
|
|
|
|
/** @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
|
|
* @note Peripheral clock gating in SLEEP mode can be used to further reduce
|
|
* power consumption.
|
|
* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
|
|
* @note By default, all peripheral clocks are enabled during SLEEP mode.
|
|
*/
|
|
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
|
|
#define __FSMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FSMCLPEN))
|
|
#define __FSMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FSMCLPEN))
|
|
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
|
|
|
|
#if defined(STM32F415xx) || defined(STM32F417xx) || defined(STM32F437xx)|| defined(STM32F439xx)
|
|
#define __FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN))
|
|
#define __FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN))
|
|
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
|
|
|
|
/** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
|
|
* @note Peripheral clock gating in SLEEP mode can be used to further reduce
|
|
* power consumption.
|
|
* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
|
|
* @note By default, all peripheral clocks are enabled during SLEEP mode.
|
|
*/
|
|
#if !defined(STM32F401xC) && !defined(STM32F401xE)
|
|
#define __TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))
|
|
#define __TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN))
|
|
#define __TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN))
|
|
#define __TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN))
|
|
#define __TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN))
|
|
#define __USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN))
|
|
#define __UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN))
|
|
#define __UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN))
|
|
#define __CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN))
|
|
#define __CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN))
|
|
#define __DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))
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|
|
|
#define __TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
|
|
#define __TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
|
|
#define __TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
|
|
#define __TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
|
|
#define __TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
|
|
#define __USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
|
|
#define __UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
|
|
#define __UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
|
|
#define __CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
|
|
#define __CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
|
|
#define __DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
|
|
#endif /* !STM32F401xC && STM32F401xE */
|
|
|
|
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
|
|
#define __UART7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART7LPEN))
|
|
#define __UART8_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART8LPEN))
|
|
|
|
#define __UART7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN))
|
|
#define __UART8_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN))
|
|
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
|
|
|
|
/** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
|
|
* @note Peripheral clock gating in SLEEP mode can be used to further reduce
|
|
* power consumption.
|
|
* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
|
|
* @note By default, all peripheral clocks are enabled during SLEEP mode.
|
|
*/
|
|
#if !defined(STM32F401xC) && !defined(STM32F401xE)
|
|
#define __TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN))
|
|
#define __ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN))
|
|
#define __ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN))
|
|
|
|
#define __TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
|
|
#define __ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
|
|
#define __ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
|
|
#endif /* !STM32F401xC && STM32F401xE */
|
|
|
|
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
|
|
#define __SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN))
|
|
#define __SPI6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI6LPEN))
|
|
#define __SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN))
|
|
#define __LTDC_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_LTDCLPEN))
|
|
|
|
#define __SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
|
|
#define __SPI6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN))
|
|
#define __SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))
|
|
#define __LTDC_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_LTDCLPEN))
|
|
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
|
|
|
|
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
|
|
|
|
/** @brief Macro to configure the Timers clocks prescalers
|
|
* @note This feature is only available with STM32F429x/439x Devices.
|
|
* @param __PRESC__ : specifies the Timers clocks prescalers selection
|
|
* This parameter can be one of the following values:
|
|
* @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is
|
|
* equal to HPRE if PPREx is corresponding to division by 1 or 2,
|
|
* else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to
|
|
* division by 4 or more.
|
|
* @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is
|
|
* equal to HPRE if PPREx is corresponding to division by 1, 2 or 4,
|
|
* else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding
|
|
* to division by 8 or more.
|
|
*/
|
|
#define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) (*(__IO uint32_t *) DCKCFGR_TIMPRE_BB = (__PRESC__))
|
|
|
|
/** @brief Macros to Enable or Disable the PLLISAI.
|
|
* @note The PLLSAI is only available with STM32F429x/439x Devices.
|
|
* @note The PLLSAI is disabled by hardware when entering STOP and STANDBY modes.
|
|
*/
|
|
#define __HAL_RCC_PLLSAI_ENABLE() (*(__IO uint32_t *) CR_PLLSAION_BB = ENABLE)
|
|
#define __HAL_RCC_PLLSAI_DISABLE() (*(__IO uint32_t *) CR_PLLSAION_BB = DISABLE)
|
|
|
|
/** @brief Macro to configure the PLLSAI clock multiplication and division factors.
|
|
* @note The PLLSAI is only available with STM32F429x/439x Devices.
|
|
* @note This function must be used only when the PLLSAI is disabled.
|
|
* @note PLLSAI clock source is common with the main PLL (configured in
|
|
* RCC_PLLConfig function )
|
|
* @param __PLLSAIN__: specifies the multiplication factor for PLLSAI VCO output clock.
|
|
* This parameter must be a number between Min_Data = 192 and Max_Data = 432.
|
|
* @note You have to set the PLLSAIN parameter correctly to ensure that the VCO
|
|
* output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
|
|
* @param __PLLSAIQ__: specifies the division factor for SAI1 clock
|
|
* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
|
|
* @param __PLLSAIR__: specifies the division factor for LTDC clock
|
|
* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
|
|
*/
|
|
#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIQ__, __PLLSAIR__) (RCC->PLLSAICFGR = ((__PLLSAIN__) << 6) | ((__PLLSAIQ__) << 24) | ((__PLLSAIR__) << 28))
|
|
|
|
/** @brief Macro used by the SAI HAL driver to configure the PLLI2S clock multiplication and division factors.
|
|
* @note This macro must be used only when the PLLI2S is disabled.
|
|
* @note PLLI2S clock source is common with the main PLL (configured in
|
|
* HAL_RCC_ClockConfig() API)
|
|
* @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock.
|
|
* This parameter must be a number between Min_Data = 192 and Max_Data = 432.
|
|
* @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
|
|
* output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
|
|
* @param __PLLI2SQ__: specifies the division factor for SAI1 clock.
|
|
* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
|
|
* @note the PLLI2SQ parameter is only available with STM32F429x/439x Devices
|
|
* and can be configured using the __HAL_RCC_PLLI2S_PLLSAICLK_CONFIG() macro
|
|
* @param __PLLI2SR__: specifies the division factor for I2S clock
|
|
* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
|
|
* @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
|
|
* on the I2S clock frequency.
|
|
*/
|
|
#define __HAL_RCC_PLLI2S_SAICLK_CONFIG(__PLLI2SN__, __PLLI2SQ__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SN__) << 6) | ((__PLLI2SQ__) << 24) | ((__PLLI2SR__) << 28))
|
|
|
|
/** @brief Macro to configure the SAI clock Divider coming from PLLI2S.
|
|
* @note The SAI peripheral is only available with STM32F429x/439x Devices.
|
|
* @note This function must be called before enabling the PLLI2S.
|
|
* @param __PLLI2SDivQ__: specifies the PLLI2S division factor for SAI1 clock .
|
|
* This parameter must be a number between 1 and 32.
|
|
* SAI1 clock frequency = f(PLLI2SQ) / __PLLI2SDivQ__
|
|
*/
|
|
#define __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(__PLLI2SDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVQ, (__PLLI2SDivQ__)-1))
|
|
|
|
/** @brief Macro to configure the SAI clock Divider coming from PLLSAI.
|
|
* @note The SAI peripheral is only available with STM32F429x/439x Devices.
|
|
* @note This function must be called before enabling the PLLSAI.
|
|
* @param __PLLSAIDivQ__: specifies the PLLSAI division factor for SAI1 clock .
|
|
* This parameter must be a number between Min_Data = 1 and Max_Data = 32.
|
|
* SAI1 clock frequency = f(PLLSAIQ) / __PLLSAIDivQ__
|
|
*/
|
|
#define __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(__PLLSAIDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ, ((__PLLSAIDivQ__)-1)<<8))
|
|
|
|
/** @brief Macro to configure the LTDC clock Divider coming from PLLSAI.
|
|
*
|
|
* @note The LTDC peripheral is only available with STM32F429x/439x Devices.
|
|
* @note This function must be called before enabling the PLLSAI.
|
|
* @param __PLLSAIDivR__: specifies the PLLSAI division factor for LTDC clock .
|
|
* This parameter must be a number between Min_Data = 2 and Max_Data = 16.
|
|
* LTDC clock frequency = f(PLLSAIR) / __PLLSAIDivR__
|
|
*/
|
|
#define __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(__PLLSAIDivR__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVR, (__PLLSAIDivR__)))
|
|
|
|
/** @brief Macro to configure SAI1BlockA clock source selection.
|
|
* @note The SAI peripheral is only available with STM32F429x/439x Devices.
|
|
* @note This function must be called before enabling PLLSAI, PLLI2S and
|
|
* the SAI clock.
|
|
* @param __SOURCE__: specifies the SAI Block A clock source.
|
|
* This parameter can be one of the following values:
|
|
* @arg RCC_SAIACLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
|
|
* as SAI1 Block A clock.
|
|
* @arg RCC_SAIACLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
|
|
* as SAI1 Block A clock.
|
|
* @arg RCC_SAIACLKSOURCE_Ext: External clock mapped on the I2S_CKIN pin
|
|
* used as SAI1 Block A clock.
|
|
*/
|
|
#define __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1ASRC, (__SOURCE__)))
|
|
|
|
/** @brief Macro to configure SAI1BlockB clock source selection.
|
|
* @note The SAI peripheral is only available with STM32F429x/439x Devices.
|
|
* @note This function must be called before enabling PLLSAI, PLLI2S and
|
|
* the SAI clock.
|
|
* @param __SOURCE__: specifies the SAI Block B clock source.
|
|
* This parameter can be one of the following values:
|
|
* @arg RCC_SAIBCLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
|
|
* as SAI1 Block B clock.
|
|
* @arg RCC_SAIBCLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
|
|
* as SAI1 Block B clock.
|
|
* @arg RCC_SAIBCLKSOURCE_Ext: External clock mapped on the I2S_CKIN pin
|
|
* used as SAI1 Block B clock.
|
|
*/
|
|
#define __HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC, (__SOURCE__)))
|
|
|
|
/** @brief Enable PLLSAI_RDY interrupt.
|
|
*/
|
|
#define __HAL_RCC_PLLSAI_ENABLE_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYIE))
|
|
|
|
/** @brief Disable PLLSAI_RDY interrupt.
|
|
*/
|
|
#define __HAL_RCC_PLLSAI_DISABLE_IT() (RCC->CIR &= ~(RCC_CIR_PLLSAIRDYIE))
|
|
|
|
/** @brief Clear the PLLSAI RDY interrupt pending bits.
|
|
*/
|
|
#define __HAL_RCC_PLLSAI_CLEAR_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYF))
|
|
|
|
/** @brief Check the PLLSAI RDY interrupt has occurred or not.
|
|
* @retval The new state (TRUE or FALSE).
|
|
*/
|
|
#define __HAL_RCC_PLLSAI_GET_IT() ((RCC->CIR & (RCC_CIR_PLLSAIRDYIE)) == (RCC_CIR_PLLSAIRDYIE))
|
|
|
|
/** @brief Check PLLSAI RDY flag is set or not.
|
|
* @retval The new state (TRUE or FALSE).
|
|
*/
|
|
#define __HAL_RCC_PLLSAI_GET_FLAG() ((RCC->CR & (RCC_CR_PLLSAIRDY)) == (RCC_CR_PLLSAIRDY))
|
|
|
|
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
|
|
|
|
/* Exported functions --------------------------------------------------------*/
|
|
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
|
|
void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif /* __STM32F4xx_HAL_RCC_EX_H */
|
|
|
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|