541 lines
17 KiB
C
541 lines
17 KiB
C
/*
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* This file is part of the MicroPython project, http://micropython.org/
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2017 Scott Shawcroft for Adafruit Industries
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* Copyright (c) 2019 Lucian Copeland for Adafruit Industries
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include <stdint.h>
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#include <sys/time.h>
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#include "supervisor/board.h"
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#include "supervisor/port.h"
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#include "supervisor/filesystem.h"
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#include "supervisor/shared/reload.h"
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#include "py/runtime.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/task.h"
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#include "bindings/espidf/__init__.h"
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#include "bindings/espulp/__init__.h"
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#include "common-hal/microcontroller/Pin.h"
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#include "common-hal/analogio/AnalogOut.h"
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#include "common-hal/busio/I2C.h"
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#include "common-hal/busio/SPI.h"
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#include "common-hal/busio/UART.h"
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#include "common-hal/dualbank/__init__.h"
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#include "common-hal/ps2io/Ps2.h"
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#include "common-hal/pulseio/PulseIn.h"
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#include "common-hal/pwmio/PWMOut.h"
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#include "common-hal/watchdog/WatchDogTimer.h"
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#include "common-hal/socketpool/Socket.h"
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#include "common-hal/wifi/__init__.h"
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#include "supervisor/background_callback.h"
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#include "supervisor/memory.h"
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#include "supervisor/shared/tick.h"
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#include "shared-bindings/microcontroller/__init__.h"
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#include "shared-bindings/microcontroller/RunMode.h"
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#include "shared-bindings/rtc/__init__.h"
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#include "shared-bindings/socketpool/__init__.h"
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#include "shared-module/os/__init__.h"
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#include "peripherals/rmt.h"
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#include "peripherals/timer.h"
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#if CIRCUITPY_COUNTIO || CIRCUITPY_ROTARYIO || CIRCUITPY_FREQUENCYIO
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#include "peripherals/pcnt.h"
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#endif
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#if CIRCUITPY_TOUCHIO_USE_NATIVE
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#include "peripherals/touch.h"
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#endif
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#if CIRCUITPY_AUDIOBUSIO
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#include "common-hal/audiobusio/__init__.h"
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#endif
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#if CIRCUITPY_BLEIO
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#include "shared-bindings/_bleio/__init__.h"
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#endif
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#if CIRCUITPY_ESPCAMERA
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#include "esp_camera.h"
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#endif
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#ifndef CONFIG_IDF_TARGET_ESP32
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#include "soc/cache_memory.h"
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#endif
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#include "soc/efuse_reg.h"
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#include "soc/rtc_cntl_reg.h"
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#include "esp_debug_helpers.h"
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#include "bootloader_flash_config.h"
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#include "esp_efuse.h"
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#include "esp_ipc.h"
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#include "esp_rom_efuse.h"
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#ifdef CONFIG_IDF_TARGET_ESP32
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#include "esp32/rom/efuse.h"
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#endif
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#include "esp_log.h"
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#define TAG "port"
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uint32_t *heap;
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uint32_t heap_size;
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STATIC esp_timer_handle_t _tick_timer;
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STATIC esp_timer_handle_t _sleep_timer;
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TaskHandle_t circuitpython_task = NULL;
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extern void esp_restart(void) NORETURN;
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STATIC void tick_on_cp_core(void *arg) {
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supervisor_tick();
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// CircuitPython's VM is run in a separate FreeRTOS task from timer callbacks. So, we have to
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// notify the main task every time in case it's waiting for us.
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xTaskNotifyGive(circuitpython_task);
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}
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// This function may happen on the PRO core when CP is on the APP core. So, make
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// sure we run on the CP core.
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STATIC void tick_timer_cb(void *arg) {
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#if defined(CONFIG_FREERTOS_UNICORE) && CONFIG_FREERTOS_UNICORE
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tick_on_cp_core(arg);
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#else
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// This only blocks until the start of the function. That's ok since the PRO
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// core shouldn't care what we do.
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esp_ipc_call(CONFIG_ESP_MAIN_TASK_AFFINITY, tick_on_cp_core, NULL);
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#endif
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}
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void sleep_timer_cb(void *arg);
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// The ESP-IDF determines these pins at runtime so we do too. This code is based on:
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// https://github.com/espressif/esp-idf/blob/6d85d53ceec30c818a92c2fff8f5437d21c4720f/components/esp_hw_support/port/esp32/spiram_psram.c#L810
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// IO-pins for PSRAM.
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// WARNING: PSRAM shares all but the CS and CLK pins with the flash, so these defines
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// hardcode the flash pins as well, making this code incompatible with either a setup
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// that has the flash on non-standard pins or ESP32s with built-in flash.
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#define PSRAM_SPIQ_SD0_IO 7
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#define PSRAM_SPID_SD1_IO 8
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#define PSRAM_SPIWP_SD3_IO 10
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#define PSRAM_SPIHD_SD2_IO 9
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#define FLASH_HSPI_CLK_IO 14
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#define FLASH_HSPI_CS_IO 15
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#define PSRAM_HSPI_SPIQ_SD0_IO 12
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#define PSRAM_HSPI_SPID_SD1_IO 13
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#define PSRAM_HSPI_SPIWP_SD3_IO 2
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#define PSRAM_HSPI_SPIHD_SD2_IO 4
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#ifdef CONFIG_SPIRAM
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// PSRAM clock and cs IO should be configured based on hardware design.
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// For ESP32-WROVER or ESP32-WROVER-B module, the clock IO is IO17, the cs IO is IO16,
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// they are the default value for these two configs.
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#define D0WD_PSRAM_CLK_IO CONFIG_D0WD_PSRAM_CLK_IO // Default value is 17
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#define D0WD_PSRAM_CS_IO CONFIG_D0WD_PSRAM_CS_IO // Default value is 16
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#define D2WD_PSRAM_CLK_IO CONFIG_D2WD_PSRAM_CLK_IO // Default value is 9
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#define D2WD_PSRAM_CS_IO CONFIG_D2WD_PSRAM_CS_IO // Default value is 10
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// There is no reason to change the pin of an embedded psram.
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// So define the number of pin directly, instead of configurable.
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#define D0WDR2_V3_PSRAM_CLK_IO 6
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#define D0WDR2_V3_PSRAM_CS_IO 16
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// For ESP32-PICO chip, the psram share clock with flash. The flash clock pin is fixed, which is IO6.
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#define PICO_PSRAM_CLK_IO 6
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#define PICO_PSRAM_CS_IO CONFIG_PICO_PSRAM_CS_IO // Default value is 10
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#define PICO_V3_02_PSRAM_CLK_IO 10
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#define PICO_V3_02_PSRAM_CS_IO 9
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#endif // CONFIG_SPIRAM
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static void _never_reset_spi_ram_flash(void) {
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#if defined(CONFIG_IDF_TARGET_ESP32)
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#if defined(CONFIG_SPIRAM)
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uint32_t pkg_ver = esp_efuse_get_pkg_ver();
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if (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5) {
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never_reset_pin_number(D2WD_PSRAM_CLK_IO);
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never_reset_pin_number(D2WD_PSRAM_CS_IO);
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} else if (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4 && esp_efuse_get_chip_ver() >= 3) {
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// This chip is ESP32-PICO-V3 and doesn't have PSRAM.
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} else if ((pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD2) || (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4)) {
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never_reset_pin_number(PICO_PSRAM_CLK_IO);
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never_reset_pin_number(PICO_PSRAM_CS_IO);
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} else if (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOV302) {
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never_reset_pin_number(PICO_V3_02_PSRAM_CLK_IO);
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never_reset_pin_number(PICO_V3_02_PSRAM_CS_IO);
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} else if ((pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32D0WDQ6) || (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32D0WDQ5)) {
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never_reset_pin_number(D0WD_PSRAM_CLK_IO);
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never_reset_pin_number(D0WD_PSRAM_CS_IO);
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} else if (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32D0WDR2V3) {
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never_reset_pin_number(D0WDR2_V3_PSRAM_CLK_IO);
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never_reset_pin_number(D0WDR2_V3_PSRAM_CS_IO);
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}
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#endif // CONFIG_SPIRAM
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const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info();
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if (spiconfig == ESP_ROM_EFUSE_FLASH_DEFAULT_SPI) {
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never_reset_pin_number(SPI_IOMUX_PIN_NUM_CLK);
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never_reset_pin_number(SPI_IOMUX_PIN_NUM_CS);
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never_reset_pin_number(PSRAM_SPIQ_SD0_IO);
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never_reset_pin_number(PSRAM_SPID_SD1_IO);
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never_reset_pin_number(PSRAM_SPIWP_SD3_IO);
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never_reset_pin_number(PSRAM_SPIHD_SD2_IO);
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} else if (spiconfig == ESP_ROM_EFUSE_FLASH_DEFAULT_HSPI) {
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never_reset_pin_number(FLASH_HSPI_CLK_IO);
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never_reset_pin_number(FLASH_HSPI_CS_IO);
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never_reset_pin_number(PSRAM_HSPI_SPIQ_SD0_IO);
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never_reset_pin_number(PSRAM_HSPI_SPID_SD1_IO);
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never_reset_pin_number(PSRAM_HSPI_SPIWP_SD3_IO);
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never_reset_pin_number(PSRAM_HSPI_SPIHD_SD2_IO);
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} else {
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never_reset_pin_number(EFUSE_SPICONFIG_RET_SPICLK(spiconfig));
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never_reset_pin_number(EFUSE_SPICONFIG_RET_SPICS0(spiconfig));
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never_reset_pin_number(EFUSE_SPICONFIG_RET_SPIQ(spiconfig));
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never_reset_pin_number(EFUSE_SPICONFIG_RET_SPID(spiconfig));
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never_reset_pin_number(EFUSE_SPICONFIG_RET_SPIHD(spiconfig));
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never_reset_pin_number(bootloader_flash_get_wp_pin());
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}
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#endif // CONFIG_IDF_TARGET_ESP32
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}
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safe_mode_t port_init(void) {
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esp_timer_create_args_t args;
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args.callback = &tick_timer_cb;
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args.arg = NULL;
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args.dispatch_method = ESP_TIMER_TASK;
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args.name = "CircuitPython Tick";
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esp_timer_create(&args, &_tick_timer);
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args.callback = &sleep_timer_cb;
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args.arg = NULL;
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args.dispatch_method = ESP_TIMER_TASK;
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args.name = "CircuitPython Sleep";
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esp_timer_create(&args, &_sleep_timer);
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circuitpython_task = xTaskGetCurrentTaskHandle();
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// Send the ROM output out of the UART. This includes early logs.
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#ifdef DEBUG
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ets_install_uart_printf();
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#endif
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heap = NULL;
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#ifndef DEBUG
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#define DEBUG (0)
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#endif
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#define pin_GPIOn(n) pin_GPIO##n
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#define pin_GPIOn_EXPAND(x) pin_GPIOn(x)
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#ifdef CONFIG_CONSOLE_UART_TX_GPIO
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common_hal_never_reset_pin(&pin_GPIOn_EXPAND(CONFIG_CONSOLE_UART_TX_GPIO));
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#endif
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#ifdef CONFIG_CONSOLE_UART_RX_GPIO
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common_hal_never_reset_pin(&pin_GPIOn_EXPAND(CONFIG_CONSOLE_UART_RX_GPIO));
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#endif
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#if DEBUG
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// debug UART
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#ifdef CONFIG_IDF_TARGET_ESP32C3
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common_hal_never_reset_pin(&pin_GPIO20);
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common_hal_never_reset_pin(&pin_GPIO21);
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#elif defined(CONFIG_IDF_TARGET_ESP32S2) || defined(CONFIG_IDF_TARGET_ESP32S3)
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common_hal_never_reset_pin(&pin_GPIO43);
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common_hal_never_reset_pin(&pin_GPIO44);
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#endif
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#endif
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#ifndef ENABLE_JTAG
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#define ENABLE_JTAG (defined(DEBUG) && DEBUG)
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#endif
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#if ENABLE_JTAG
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// JTAG
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#ifdef CONFIG_IDF_TARGET_ESP32C3
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common_hal_never_reset_pin(&pin_GPIO4);
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common_hal_never_reset_pin(&pin_GPIO5);
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common_hal_never_reset_pin(&pin_GPIO6);
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common_hal_never_reset_pin(&pin_GPIO7);
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#elif defined(CONFIG_IDF_TARGET_ESP32S2) || defined(CONFIG_IDF_TARGET_ESP32S3)
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common_hal_never_reset_pin(&pin_GPIO39);
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common_hal_never_reset_pin(&pin_GPIO40);
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common_hal_never_reset_pin(&pin_GPIO41);
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common_hal_never_reset_pin(&pin_GPIO42);
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#endif
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#endif
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#ifdef CONFIG_SPIRAM
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{
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intptr_t heap_start = common_hal_espidf_get_psram_start();
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intptr_t heap_end = common_hal_espidf_get_psram_end();
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size_t spiram_size = heap_end - heap_start;
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if (spiram_size > 0) {
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heap = (uint32_t *)heap_start;
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heap_size = (heap_end - heap_start) / sizeof(uint32_t);
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} else {
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ESP_LOGE(TAG, "CONFIG_SPIRAM enabled but no spiram heap available");
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}
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}
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#endif
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_never_reset_spi_ram_flash();
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if (heap == NULL) {
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size_t heap_total = heap_caps_get_total_size(MALLOC_CAP_8BIT);
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heap_size = MIN(heap_caps_get_largest_free_block(MALLOC_CAP_8BIT), heap_total / 2);
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heap = malloc(heap_size);
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heap_size = heap_size / sizeof(uint32_t);
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}
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if (heap == NULL) {
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heap_size = 0;
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return SAFE_MODE_NO_HEAP;
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}
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esp_reset_reason_t reason = esp_reset_reason();
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switch (reason) {
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case ESP_RST_BROWNOUT:
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return SAFE_MODE_BROWNOUT;
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case ESP_RST_PANIC:
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return SAFE_MODE_HARD_FAULT;
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case ESP_RST_INT_WDT:
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// The interrupt watchdog is used internally to make sure that latency sensitive
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// interrupt code isn't blocked. User watchdog resets come through ESP_RST_WDT.
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return SAFE_MODE_WATCHDOG;
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case ESP_RST_WDT:
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default:
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break;
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}
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return SAFE_MODE_NONE;
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}
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void reset_port(void) {
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// TODO deinit for esp32-camera
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#if CIRCUITPY_ESPCAMERA
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esp_camera_deinit();
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#endif
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reset_all_pins();
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#if CIRCUITPY_ANALOGIO
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analogout_reset();
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#endif
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#if CIRCUITPY_AUDIOBUSIO
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i2s_reset();
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#endif
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#if CIRCUITPY_BUSIO
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i2c_reset();
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spi_reset();
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uart_reset();
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#endif
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#if CIRCUITPY_COUNTIO || CIRCUITPY_ROTARYIO || CIRCUITPY_FREQUENCYIO
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peripherals_pcnt_reset();
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#endif
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#if CIRCUITPY_DUALBANK
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dualbank_reset();
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#endif
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#if CIRCUITPY_ESPULP
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espulp_reset();
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#endif
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#if CIRCUITPY_FREQUENCYIO
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peripherals_timer_reset();
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#endif
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#if CIRCUITPY_PS2IO
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ps2_reset();
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#endif
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#if CIRCUITPY_PULSEIO
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peripherals_rmt_reset();
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pulsein_reset();
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#endif
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#if CIRCUITPY_PWMIO
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pwmout_reset();
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#endif
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#if CIRCUITPY_RTC
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rtc_reset();
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#endif
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#if CIRCUITPY_SOCKETPOOL
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socketpool_user_reset();
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#endif
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#if CIRCUITPY_TOUCHIO_USE_NATIVE
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peripherals_touch_reset();
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#endif
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#if CIRCUITPY_WATCHDOG
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watchdog_reset();
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#endif
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// Yield so the idle task can run and do any IDF cleanup needed.
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port_yield();
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}
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void reset_to_bootloader(void) {
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common_hal_mcu_on_next_reset(RUNMODE_BOOTLOADER);
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esp_restart();
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}
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void reset_cpu(void) {
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#ifndef CONFIG_IDF_TARGET_ESP32C3
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esp_backtrace_print(100);
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#endif
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esp_restart();
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}
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uint32_t *port_heap_get_bottom(void) {
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return heap;
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}
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uint32_t *port_heap_get_top(void) {
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return heap + heap_size;
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}
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uint32_t *port_stack_get_limit(void) {
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#pragma GCC diagnostic push
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#pragma GCC diagnostic ignored "-Wcast-align"
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return (uint32_t *)pxTaskGetStackStart(NULL);
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#pragma GCC diagnostic pop
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}
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uint32_t *port_stack_get_top(void) {
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// The sizeof-arithmetic is so that the pointer arithmetic is done on units
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// of uint32_t instead of units of StackType_t. StackType_t is an alias
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// for a byte sized type.
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//
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// The main stack is bigger than CONFIG_ESP_MAIN_TASK_STACK_SIZE -- an
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// "extra" size is added to it (TASK_EXTRA_STACK_SIZE). This total size is
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// available as ESP_TASK_MAIN_STACK. Presumably TASK_EXTRA_STACK_SIZE is
|
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// additional stack that can be used by the esp-idf runtime. But what's
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// important for us is that some very outermost stack frames, such as
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// pyexec_friendly_repl, could lie inside the "extra" area and be invisible
|
|
// to the garbage collector.
|
|
return port_stack_get_limit() + ESP_TASK_MAIN_STACK / (sizeof(uint32_t) / sizeof(StackType_t));
|
|
}
|
|
|
|
bool port_has_fixed_stack(void) {
|
|
return true;
|
|
}
|
|
|
|
// Place the word to save just after our BSS section that gets blanked.
|
|
void port_set_saved_word(uint32_t value) {
|
|
REG_WRITE(RTC_CNTL_STORE0_REG, value);
|
|
}
|
|
|
|
uint32_t port_get_saved_word(void) {
|
|
return REG_READ(RTC_CNTL_STORE0_REG);
|
|
}
|
|
|
|
uint64_t port_get_raw_ticks(uint8_t *subticks) {
|
|
// Convert microseconds to subticks of 1/32768 seconds
|
|
// 32768/1000000 = 64/15625 in lowest terms
|
|
// this arithmetic overflows after 570 years
|
|
int64_t all_subticks = esp_timer_get_time() * 512 / 15625;
|
|
if (subticks != NULL) {
|
|
*subticks = all_subticks % 32;
|
|
}
|
|
return all_subticks / 32;
|
|
}
|
|
|
|
// Enable 1/1024 second tick.
|
|
void port_enable_tick(void) {
|
|
esp_timer_start_periodic(_tick_timer, 1000000 / 1024);
|
|
}
|
|
|
|
// Disable 1/1024 second tick.
|
|
void port_disable_tick(void) {
|
|
esp_timer_stop(_tick_timer);
|
|
}
|
|
|
|
void port_wake_main_task() {
|
|
xTaskNotifyGive(circuitpython_task);
|
|
}
|
|
|
|
void port_wake_main_task_from_isr() {
|
|
BaseType_t xHigherPriorityTaskWoken = pdFALSE;
|
|
vTaskNotifyGiveFromISR(circuitpython_task, &xHigherPriorityTaskWoken);
|
|
if (xHigherPriorityTaskWoken == pdTRUE) {
|
|
portYIELD_FROM_ISR();
|
|
}
|
|
}
|
|
|
|
void port_yield() {
|
|
vTaskDelay(4);
|
|
}
|
|
|
|
void sleep_timer_cb(void *arg) {
|
|
port_wake_main_task();
|
|
}
|
|
|
|
void port_interrupt_after_ticks(uint32_t ticks) {
|
|
uint64_t timeout_us = ticks * 1000000ull / 1024;
|
|
if (esp_timer_start_once(_sleep_timer, timeout_us) != ESP_OK) {
|
|
esp_timer_stop(_sleep_timer);
|
|
esp_timer_start_once(_sleep_timer, timeout_us);
|
|
}
|
|
}
|
|
|
|
// On the ESP we use FreeRTOS notifications instead of interrupts so this is a
|
|
// bit of a misnomer.
|
|
void port_idle_until_interrupt(void) {
|
|
if (!background_callback_pending() && !autoreload_pending()) {
|
|
xTaskNotifyWait(0x01, 0x01, NULL, portMAX_DELAY);
|
|
}
|
|
}
|
|
|
|
void port_post_boot_py(bool heap_valid) {
|
|
if (!heap_valid && filesystem_present()) {
|
|
mp_int_t reserved;
|
|
if (common_hal_os_getenv_int("CIRCUITPY_RESERVED_PSRAM", &reserved) == GETENV_OK) {
|
|
common_hal_espidf_set_reserved_psram(reserved);
|
|
}
|
|
common_hal_espidf_reserve_psram();
|
|
}
|
|
}
|
|
|
|
// Wrap main in app_main that the IDF expects.
|
|
extern void main(void);
|
|
extern void app_main(void);
|
|
void app_main(void) {
|
|
main();
|
|
}
|