1866ed7e2e
This commit implements 10/100 Mbit Ethernet support in the mimxrt port. The following boards are configured without ETH network: - MIMXRT1010_EVK - Teensy 4.0 The following boards are configured with ETH network: - MIMXRT1020_EVK - MIMXRT1050_EVK - MIMXRT1060_EVK - MIMXRT1064_EVK - Teensy 4.1 Ethernet support tested with TEENSY 4.1, MIMRTX1020_EVK and MIMXRT1050_EVK. Build tested with Teensy 4.0 and MIMXRT1010_EVK to be still working. Compiles and builds properly for MIMXRT1060_EVK and MIMXRT1064_EVK, but not tested lacking suitable boards. Tested functions are: - ping works bothway - simple UDP transfer works bothway - ntptime works - the ftp server works - secure socker works - telnet and webrepl works The MAC address is 0x02 plus 5 bytes from the manifacturing info field, which can be considered as unique per device. Some boards do not wire the RESET and INT pin of the PHY transceiver. For operation, these are not required. If they are defined, they will be used.
89 lines
3.7 KiB
C
89 lines
3.7 KiB
C
#define MICROPY_HW_BOARD_NAME "Teensy 4.1"
|
|
#define MICROPY_HW_MCU_NAME "MIMXRT1062DVJ6A"
|
|
|
|
// Teensy 4.1 has 1 board LED
|
|
#define MICROPY_HW_LED1_PIN (pin_GPIO_B0_03)
|
|
#define MICROPY_HW_LED_ON(pin) (mp_hal_pin_high(pin))
|
|
#define MICROPY_HW_LED_OFF(pin) (mp_hal_pin_low(pin))
|
|
|
|
#define MICROPY_HW_NUM_PIN_IRQS (4 * 32 + 3)
|
|
|
|
// UART config: 8 UARTs at the pins for Teensy 4.1
|
|
#define MICROPY_HW_UART_NUM (sizeof(uart_index_table) / sizeof(uart_index_table)[0])
|
|
#define MICROPY_HW_UART_INDEX { 0, 6, 4, 2, 3, 8, 1, 7, 5 }
|
|
|
|
#define IOMUX_TABLE_UART \
|
|
{ IOMUXC_GPIO_AD_B0_12_LPUART1_TX }, { IOMUXC_GPIO_AD_B0_13_LPUART1_RX }, \
|
|
{ IOMUXC_GPIO_AD_B1_02_LPUART2_TX }, { IOMUXC_GPIO_AD_B1_03_LPUART2_RX }, \
|
|
{ IOMUXC_GPIO_AD_B1_06_LPUART3_TX }, { IOMUXC_GPIO_AD_B1_07_LPUART3_RX }, \
|
|
{ IOMUXC_GPIO_B1_00_LPUART4_TX }, { IOMUXC_GPIO_B1_01_LPUART4_RX }, \
|
|
{ IOMUXC_GPIO_B1_12_LPUART5_TX }, { IOMUXC_GPIO_B1_13_LPUART5_RX }, \
|
|
{ IOMUXC_GPIO_AD_B0_02_LPUART6_TX }, { IOMUXC_GPIO_AD_B0_03_LPUART6_RX }, \
|
|
{ IOMUXC_GPIO_EMC_31_LPUART7_TX }, { IOMUXC_GPIO_EMC_32_LPUART7_RX }, \
|
|
{ IOMUXC_GPIO_AD_B1_10_LPUART8_TX }, { IOMUXC_GPIO_AD_B1_11_LPUART8_RX },
|
|
|
|
#define MICROPY_HW_SPI_INDEX { 4, 3, 1 }
|
|
|
|
#define IOMUX_TABLE_SPI \
|
|
{ IOMUXC_GPIO_SD_B0_00_LPSPI1_SCK }, { IOMUXC_GPIO_SD_B0_01_LPSPI1_PCS0 }, \
|
|
{ IOMUXC_GPIO_SD_B0_02_LPSPI1_SDO }, { IOMUXC_GPIO_SD_B0_03_LPSPI1_SDI }, \
|
|
{ 0 }, { 0 }, \
|
|
{ 0 }, { 0 }, \
|
|
{ IOMUXC_GPIO_AD_B1_15_LPSPI3_SCK }, { IOMUXC_GPIO_AD_B1_12_LPSPI3_PCS0 }, \
|
|
{ IOMUXC_GPIO_AD_B1_14_LPSPI3_SDO }, { IOMUXC_GPIO_AD_B1_13_LPSPI3_SDI }, \
|
|
{ IOMUXC_GPIO_B0_03_LPSPI4_SCK }, { IOMUXC_GPIO_B0_00_LPSPI4_PCS0 }, \
|
|
{ IOMUXC_GPIO_B0_02_LPSPI4_SDO }, { IOMUXC_GPIO_B0_01_LPSPI4_SDI },
|
|
|
|
#define DMA_REQ_SRC_RX { 0, kDmaRequestMuxLPSPI1Rx, kDmaRequestMuxLPSPI2Rx, \
|
|
kDmaRequestMuxLPSPI3Rx, kDmaRequestMuxLPSPI4Rx }
|
|
|
|
#define DMA_REQ_SRC_TX { 0, kDmaRequestMuxLPSPI1Tx, kDmaRequestMuxLPSPI2Tx, \
|
|
kDmaRequestMuxLPSPI3Tx, kDmaRequestMuxLPSPI4Tx }
|
|
|
|
// Define mapping hardware I2C # to logical I2C #
|
|
// SDA/SCL HW-I2C Logical I2C
|
|
// 17/16 LPI2C3 -> 0
|
|
// 18/19 LPI2C1 -> 1
|
|
// 25/24 LPI2C4 -> 2
|
|
|
|
#define MICROPY_HW_I2C_INDEX { 1, 3, 4 }
|
|
|
|
#define IOMUX_TABLE_I2C \
|
|
{ IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL }, { IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA }, \
|
|
{ 0 }, { 0 }, \
|
|
{ IOMUXC_GPIO_AD_B1_07_LPI2C3_SCL }, { IOMUXC_GPIO_AD_B1_06_LPI2C3_SDA }, \
|
|
{ IOMUXC_GPIO_AD_B0_12_LPI2C4_SCL }, { IOMUXC_GPIO_AD_B0_13_LPI2C4_SDA },
|
|
|
|
#define USDHC_DUMMY_PIN NULL, 0
|
|
#define MICROPY_USDHC1 \
|
|
{ \
|
|
.cmd = {GPIO_SD_B0_00_USDHC1_CMD}, \
|
|
.clk = { GPIO_SD_B0_01_USDHC1_CLK }, \
|
|
.cd_b = { USDHC_DUMMY_PIN }, \
|
|
.data0 = { GPIO_SD_B0_02_USDHC1_DATA0 }, \
|
|
.data1 = { GPIO_SD_B0_03_USDHC1_DATA1 }, \
|
|
.data2 = { GPIO_SD_B0_04_USDHC1_DATA2 }, \
|
|
.data3 = { GPIO_SD_B0_05_USDHC1_DATA3 }, \
|
|
}
|
|
|
|
// Network definitions
|
|
// Transceiver Phy Address & Type
|
|
#define ENET_PHY_ADDRESS (0)
|
|
#define ENET_PHY_OPS phydp83825_ops
|
|
|
|
// Ethernet PIN definitions
|
|
#define ENET_RESET_PIN pin_GPIO_B0_14
|
|
#define ENET_INT_PIN pin_GPIO_B0_15
|
|
|
|
#define IOMUX_TABLE_ENET \
|
|
{ IOMUXC_GPIO_B1_04_ENET_RX_DATA00, 0, 0xB0E9u }, \
|
|
{ IOMUXC_GPIO_B1_05_ENET_RX_DATA01, 0, 0xB0E9u }, \
|
|
{ IOMUXC_GPIO_B1_06_ENET_RX_EN, 0, 0xB0E9u }, \
|
|
{ IOMUXC_GPIO_B1_07_ENET_TX_DATA00, 0, 0xB0E9u }, \
|
|
{ IOMUXC_GPIO_B1_08_ENET_TX_DATA01, 0, 0xB0E9u }, \
|
|
{ IOMUXC_GPIO_B1_09_ENET_TX_EN, 0, 0xB0E9u }, \
|
|
{ IOMUXC_GPIO_B1_10_ENET_REF_CLK, 1, 0x71u }, \
|
|
{ IOMUXC_GPIO_B1_11_ENET_RX_ER, 0, 0xB0E9u }, \
|
|
{ IOMUXC_GPIO_B1_15_ENET_MDIO, 0, 0xB0E9u }, \
|
|
{ IOMUXC_GPIO_B1_14_ENET_MDC, 0, 0xB0E9u },
|