109 lines
3.3 KiB
C
109 lines
3.3 KiB
C
/*
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* This file is part of the Micro Python project, http://micropython.org/
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2016 Glenn Ruben Bakke
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#ifndef HAL_SPI_H__
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#define HAL_SPI_H__
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#include <stdbool.h>
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#include "nrf.h"
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#if NRF51
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#define SPI0 ((NRF_SPI_Type *) NRF_SPI0)
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#define SPI0_IRQ_NUM SPI0_TWI0_IRQn
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#define SPI1 ((NRF_SPI_Type *) NRF_SPI1)
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#define SPI1_IRQ_NUM SPI1_TWI1_IRQn
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#elif NRF52
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#define SPI0 ((NRF_SPI_Type *) NRF_SPI0_BASE)
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#define SPI0_IRQ_NUM SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn
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#define SPI1 ((NRF_SPI_Type *) NRF_SPI1_BASE)
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#define SPI1_IRQ_NUM SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn
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#define SPI2 ((NRF_SPI_Type *) NRF_SPI2_BASE)
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#define SPI2_IRQ_NUM SPIM2_SPIS2_SPI2_IRQn
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#else
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#error "Device not supported."
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#endif
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/**
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* @brief SPI clock frequency type definition
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*/
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typedef enum {
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HAL_FREQ_125_Kbps = 0,
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HAL_FREQ_250_Kbps,
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HAL_FREQ_500_Kbps,
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HAL_FREQ_1_Mbps,
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HAL_FREQ_2_Mbps,
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HAL_FREQ_4_Mbps,
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HAL_FREQ_8_Mbps
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} hal_spi_clk_freq_t;
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/**
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* @brief SPI mode type definition
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*/
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typedef enum {
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HAL_SPI_MODE_CPOL0_CPHA0 = 0, // CPOL = 0, CPHA = 0 (data on leading edge)
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HAL_SPI_MODE_CPOL0_CPHA1, // CPOL = 0, CPHA = 1 (data on trailing edge)
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HAL_SPI_MODE_CPOL1_CPHA0, // CPOL = 1, CPHA = 0 (data on leading edge)
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HAL_SPI_MODE_CPOL1_CPHA1 // CPOL = 1, CPHA = 1 (data on trailing edge)
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} hal_spi_mode_t;
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/**
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* @brief SPI Configuration Structure definition
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*/
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typedef struct {
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uint8_t mosi_pin;
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uint8_t miso_pin;
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uint8_t clk_pin;
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uint8_t mosi_pin_port;
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uint8_t miso_pin_port;
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uint8_t clk_pin_port;
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bool lsb_first;
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hal_spi_mode_t mode;
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uint32_t irq_priority;
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hal_spi_clk_freq_t freq;
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} hal_spi_init_t;
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/**
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* @brief SPI handle Structure definition
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*/
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typedef struct __SPI_HandleTypeDef
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{
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NRF_SPI_Type *instance; /* SPI registers base address */
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hal_spi_init_t init; /* SPI initialization parameters */
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} SPI_HandleTypeDef;
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void hal_spi_master_init(NRF_SPI_Type * p_instance, hal_spi_init_t const * p_spi_init);
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void hal_spi_master_tx_rx(NRF_SPI_Type * p_instance,
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uint16_t transfer_size,
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const uint8_t * tx_data,
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uint8_t * rx_data);
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#endif // HAL_SPI_H__
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