186 lines
6.6 KiB
C
186 lines
6.6 KiB
C
/*
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* This file is part of the MicroPython project, http://micropython.org/
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2016 Scott Shawcroft for Adafruit Industries
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hpl_gpio.h"
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#include "py/mphal.h"
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#include "shared-bindings/neopixel_write/__init__.h"
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#include "tick.h"
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#ifdef SAMD51
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#include "hri/hri_cmcc_d51.h"
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#include "hri/hri_nvmctrl_d51.h"
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// This magical macro makes sure the delay isn't optimized out and is the
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// minimal three instructions.
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#define delay_cycles(cycles) \
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{ \
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uint32_t t; \
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asm volatile ( \
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"movs %[t], %[c]\n\t" \
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"loop%=:\n\t" \
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"subs %[t], #1\n\t" \
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"bne.n loop%=" : [t] "=r"(t) : [c] "I" (cycles)); \
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}
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#endif
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uint64_t next_start_tick_ms = 0;
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uint32_t next_start_tick_us = 1000;
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void common_hal_neopixel_write(const digitalio_digitalinout_obj_t* digitalinout, uint8_t *pixels, uint32_t numBytes) {
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// This is adapted directly from the Adafruit NeoPixel library SAMD21G18A code:
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// https://github.com/adafruit/Adafruit_NeoPixel/blob/master/Adafruit_NeoPixel.cpp
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uint8_t *ptr, *end, p, bitMask;
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uint32_t pinMask;
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PortGroup* port;
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// This must be called while interrupts are on in case we're waiting for a
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// future ms tick.
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wait_until(next_start_tick_ms, next_start_tick_us);
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// Turn off interrupts of any kind during timing-sensitive code.
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mp_hal_disable_all_interrupts();
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#ifdef SAMD21
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// Make sure the NVM cache is consistently timed.
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NVMCTRL->CTRLB.bit.READMODE = NVMCTRL_CTRLB_READMODE_DETERMINISTIC_Val;
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#endif
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#ifdef SAMD51
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// When this routine is positioned at certain addresses, the timing logic
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// below can be too fast by about 2.5x. This is some kind of (un)fortunate code
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// positiong with respect to a cache line.
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// Theoretically we should turn on off the CMCC caches and the
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// NVM caches to ensure consistent timing. Testing shows the the NVMCTRL
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// cache disabling seems to make the difference. But turn both off to make sure.
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// It's difficult to test because additions to the code before the timing loop
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// below change instruction placement. Testing was done by adding cache changes
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// below the loop (so only the first time through is wrong).
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//
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// Turn off instruction, data, and NVM caches to force consistent timing.
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// Invalidate existing cache entries.
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hri_cmcc_set_CFG_reg(CMCC, CMCC_CFG_DCDIS | CMCC_CFG_ICDIS);
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hri_cmcc_write_MAINT0_reg(CMCC, CMCC_MAINT0_INVALL);
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hri_nvmctrl_set_CTRLA_CACHEDIS0_bit(NVMCTRL);
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hri_nvmctrl_set_CTRLA_CACHEDIS1_bit(NVMCTRL);
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#endif
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uint32_t pin = digitalinout->pin->pin;
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port = &PORT->Group[GPIO_PORT(pin)]; // Convert GPIO # to port register
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pinMask = (1UL << (pin % 32)); // From port_pin_set_output_level ASF code.
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ptr = pixels;
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end = ptr + numBytes;
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p = *ptr++;
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bitMask = 0x80;
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volatile uint32_t *set = &(port->OUTSET.reg),
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*clr = &(port->OUTCLR.reg);
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for(;;) {
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*set = pinMask;
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// This is the time where the line is always high regardless of the bit.
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// For the SK6812 its 0.3us +- 0.15us
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#ifdef SAMD21
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asm("nop; nop;");
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#endif
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#ifdef SAMD51
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delay_cycles(3);
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#endif
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if((p & bitMask) != 0) {
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// This is the high delay unique to a one bit.
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// For the SK6812 its 0.3us
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#ifdef SAMD21
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asm("nop; nop; nop; nop; nop; nop; nop;");
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#endif
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#ifdef SAMD51
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delay_cycles(3);
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#endif
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*clr = pinMask;
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} else {
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*clr = pinMask;
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// This is the low delay unique to a zero bit.
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// For the SK6812 its 0.3us
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#ifdef SAMD21
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asm("nop; nop;");
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#endif
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#ifdef SAMD51
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delay_cycles(3);
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#endif
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}
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if((bitMask >>= 1) != 0) {
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// This is the delay between bits in a byte and is the 1 code low
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// level time from the datasheet.
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// For the SK6812 its 0.6us +- 0.15us
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#ifdef SAMD21
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asm("nop; nop; nop; nop; nop;");
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#endif
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#ifdef SAMD51
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delay_cycles(4);
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#endif
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} else {
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if(ptr >= end) break;
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p = *ptr++;
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bitMask = 0x80;
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// This is the delay between bytes. It's similar to the other branch
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// in the if statement except its tuned to account for the time the
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// above operations take.
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// For the SK6812 its 0.6us +- 0.15us
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#ifdef SAMD51
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delay_cycles(3);
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#endif
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}
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}
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#ifdef SAMD21
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// Speed up! (But inconsistent timing.)
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NVMCTRL->CTRLB.bit.READMODE = NVMCTRL_CTRLB_READMODE_NO_MISS_PENALTY_Val;
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#endif
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#ifdef SAMD51
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// Turn instruction, data, and NVM caches back on.
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hri_cmcc_clear_CFG_reg(CMCC, CMCC_CFG_DCDIS | CMCC_CFG_ICDIS);
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hri_nvmctrl_clear_CTRLA_CACHEDIS0_bit(NVMCTRL);
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hri_nvmctrl_clear_CTRLA_CACHEDIS1_bit(NVMCTRL);
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#endif
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// ticks_ms may be out of date at this point because we stopped the
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// interrupt. We'll risk it anyway.
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current_tick(&next_start_tick_ms, &next_start_tick_us);
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if (next_start_tick_us < 100) {
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next_start_tick_ms += 1;
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next_start_tick_us = 100 - next_start_tick_us;
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} else {
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next_start_tick_us -= 100;
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}
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// Turn on interrupts after timing-sensitive code.
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mp_hal_enable_all_interrupts();
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}
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