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silabs-BelaV 4e25a4f6b3
Silabs' new Pull Request for submoduling the ports/silabs/tools/slc_cli_linux/ (#7874) 
Doing a squash merge to avoid having the `slc_cli_linux` .zip files in the history. They were added in one commit and removed and replaced with a submodule in another.

* Initial commit for xg24

* Fix SLC issue

* Fix SLC extract fail

* Change board's name

* Correct spelling of code

Build immediately after slc generate

* Remove VID and PID

* Change creator and creation id

* Apply new creator_id and creation_id

* Update makefile, error message, mcu_processor function

* Update mpconfigboard.mk

* Update Board extensions, PORT_DEPS

* Update makefile

* Add exclude_patterns

* Show java, jinja2 version

* Show path for debugging CI

* Add requirements-dev for slc

* Add PATH slc_cli

* Update background function

* Add jinja2 PATH

* Show PATH

* Update jinja2 path

* Update jinja2 path

* Update jinja2 path

* Update jinja2 path

* Change slc folder

* Change markupsafe folder

* Add symbolic link for slc

* Update makefile

* Update makefile

* Update MX25R3235F.toml from submodule nvm.toml

* alphabetize the list

* Remove slc_cli_linux folder

* Update slc_cli submodule

---------

Co-authored-by: Chat Nguyen <cvnguyen@silabs.com>
Co-authored-by: silabs-ChatNguyen <chat.nguyen@silabs.com>
Co-authored-by: silabs-ChatNguyen <126220343+silabs-ChatNguyen@users.noreply.github.com>
 		2023-04-18 12:42:16 -04:00
..
README.md Silabs' new Pull Request for submoduling the ports/silabs/tools/slc_cli_linux/ (#7874) 2023-04-18 12:42:16 -04:00
board.c Silabs' new Pull Request for submoduling the ports/silabs/tools/slc_cli_linux/ (#7874) 2023-04-18 12:42:16 -04:00
custom_brd2704a_cp_support.slcc Silabs' new Pull Request for submoduling the ports/silabs/tools/slc_cli_linux/ (#7874) 2023-04-18 12:42:16 -04:00
mpconfigboard.h Silabs' new Pull Request for submoduling the ports/silabs/tools/slc_cli_linux/ (#7874) 2023-04-18 12:42:16 -04:00
mpconfigboard.mk Silabs' new Pull Request for submoduling the ports/silabs/tools/slc_cli_linux/ (#7874) 2023-04-18 12:42:16 -04:00
pin_functions.csv Silabs' new Pull Request for submoduling the ports/silabs/tools/slc_cli_linux/ (#7874) 2023-04-18 12:42:16 -04:00
pins.csv Silabs' new Pull Request for submoduling the ports/silabs/tools/slc_cli_linux/ (#7874) 2023-04-18 12:42:16 -04:00

README.md

Gen Pin instructions

Input File

pins.csv : contain pin name, port number ,pin number pin_functions.csv : contain list of pin support for peripheral make_pins.py : python script to gen pin

Run make_pins.py

Copy above input file to folder boards/brd2601b/ Run CMD: $ cd boards/brd2601b/ $ python make_pins.py -s pins.c -e pin_functions.h pins.csv pin_functions.csv

    -s: name/directory of output source file
    -e: name/directory of output header file

Output

pins.c : register pin to board_module_globals_table generate array contains supported function of pin pin_functions.h : define index of functions Example: pin_pa0_functions[FN_EUSART0_RX] == 1 // Can assign pin pa0 for EUSART0_RX pin_pa0_functions[FN_EUSART0_RX] == 255 // Can't assign pin pa0 for EUSART0_RX

Read pin define on REPL

import board dir(board)