bcf041f1a3
Allows to create socket objects that support TCP and UDP in server and client mode. Interface is very close to standard Python socket class, except bind and accept do not work the same (due to hardware not supporting them in the usual way). Not compiled by default. To compile this module, use: make MICROPY_PY_WIZNET5K=1
300 lines
7.4 KiB
Makefile
300 lines
7.4 KiB
Makefile
# Select the board to build for: if not given on the command line,
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# then default to PYBV10.
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BOARD ?= PYBV10
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ifeq ($(wildcard boards/$(BOARD)/.),)
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$(error Invalid BOARD specified)
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endif
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# If the build directory is not given, make it reflect the board name.
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BUILD ?= build-$(BOARD)
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include ../py/mkenv.mk
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-include mpconfigport.mk
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# qstr definitions (must come before including py.mk)
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QSTR_DEFS = qstrdefsport.h $(BUILD)/pins_qstr.h
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# include py core make definitions
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include ../py/py.mk
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CMSIS_DIR=cmsis
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HAL_DIR=hal
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USBDEV_DIR=usbdev
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#USBHOST_DIR=usbhost
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FATFS_DIR=fatfs
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CC3K_DIR=cc3k
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DFU=../tools/dfu.py
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# may need to prefix dfu-util with sudo
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DFU_UTIL ?= dfu-util
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DEVICE=0483:df11
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CROSS_COMPILE = arm-none-eabi-
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INC = -I.
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INC += -I$(PY_SRC)
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INC += -I$(BUILD)
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INC += -I$(CMSIS_DIR)/inc
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INC += -I$(CMSIS_DIR)/devinc
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INC += -I$(HAL_DIR)/inc
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INC += -I$(USBDEV_DIR)/core/inc -I$(USBDEV_DIR)/class/cdc_msc_hid/inc
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#INC += -I$(USBHOST_DIR)
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INC += -I$(FATFS_DIR)/src
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INC += -I$(CC3K_DIR)
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CFLAGS_CORTEX_M4 = -mthumb -mtune=cortex-m4 -mabi=aapcs-linux -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -fsingle-precision-constant -Wdouble-promotion
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CFLAGS = $(INC) -Wall -Werror -ansi -std=gnu99 -nostdlib $(CFLAGS_MOD) $(CFLAGS_CORTEX_M4) $(COPT)
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CFLAGS += -Iboards/$(BOARD)
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LDFLAGS = -nostdlib -T stm32f405.ld -Map=$(@:.elf=.map) --cref
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LIBS =
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# Debugging/Optimization
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ifeq ($(DEBUG), 1)
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CFLAGS += -g -DPENDSV_DEBUG
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COPT = -O0
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else
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CFLAGS += -fdata-sections -ffunction-sections
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COPT += -Os -DNDEBUG
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LDFLAGS += --gc-sections
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endif
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# uncomment this if you want libgcc
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#LIBS += $(shell $(CC) -print-libgcc-file-name)
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SRC_LIB = $(addprefix lib/,\
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libm/math.c \
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libm/mathsincos.c \
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libm/atanf.c \
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libm/atan2f.c \
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)
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SRC_C = \
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main.c \
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string0.c \
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system_stm32f4xx.c \
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stm32f4xx_it.c \
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stm32f4xx_hal_msp.c \
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usbd_conf.c \
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usbd_desc_cdc_msc.c \
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usbd_cdc_interface.c \
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usbd_msc_storage.c \
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irq.c \
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pendsv.c \
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systick.c \
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timer.c \
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led.c \
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pin.c \
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pin_defs_stmhal.c \
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pin_named_pins.c \
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bufhelper.c \
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i2c.c \
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spi.c \
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uart.c \
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usb.c \
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printf.c \
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gccollect.c \
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pybstdio.c \
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readline.c \
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pyexec.c \
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help.c \
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input.c \
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modos.c \
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modpyb.c \
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modstm.c \
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modtime.c \
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import.c \
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lexerfatfs.c \
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extint.c \
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usrsw.c \
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rng.c \
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rtc.c \
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flash.c \
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storage.c \
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file.c \
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sdcard.c \
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diskio.c \
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ffconf.c \
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lcd.c \
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accel.c \
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servo.c \
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dac.c \
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adc.c \
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pybwlan.c \
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SRC_S = \
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startup_stm32f40xx.s \
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gchelper.s \
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SRC_HAL = $(addprefix $(HAL_DIR)/src/,\
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stm32f4xx_hal.c \
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stm32f4xx_hal_adc.c \
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stm32f4xx_hal_adc_ex.c \
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stm32f4xx_hal_cortex.c \
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stm32f4xx_hal_dac.c \
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stm32f4xx_hal_dac_ex.c \
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stm32f4xx_hal_dma.c \
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stm32f4xx_hal_flash.c \
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stm32f4xx_hal_flash_ex.c \
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stm32f4xx_hal_gpio.c \
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stm32f4xx_hal_i2c.c \
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stm32f4xx_hal_pcd.c \
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stm32f4xx_hal_pcd_ex.c \
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stm32f4xx_hal_rcc.c \
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stm32f4xx_hal_rcc_ex.c \
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stm32f4xx_hal_rng.c \
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stm32f4xx_hal_rtc.c \
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stm32f4xx_hal_rtc_ex.c \
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stm32f4xx_hal_sd.c \
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stm32f4xx_hal_spi.c \
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stm32f4xx_hal_tim.c \
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stm32f4xx_hal_tim_ex.c \
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stm32f4xx_hal_uart.c \
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stm32f4xx_ll_sdmmc.c \
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stm32f4xx_ll_usb.c \
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)
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SRC_USBDEV = $(addprefix $(USBDEV_DIR)/,\
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core/src/usbd_core.c \
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core/src/usbd_ctlreq.c \
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core/src/usbd_ioreq.c \
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class/cdc_msc_hid/src/usbd_cdc_msc_hid.c \
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class/cdc_msc_hid/src/usbd_msc_bot.c \
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class/cdc_msc_hid/src/usbd_msc_scsi.c \
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class/cdc_msc_hid/src/usbd_msc_data.c \
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)
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# class/cdc/src/usbd_cdc.c \
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class/msc/src/usbd_msc.c \
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# usbd_core.c \
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usbd_ioreq.c \
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usbd_req.c \
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usbd_usr.c \
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usbd_desc.c \
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usbd_pyb_core.c \
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usbd_pyb_core2.c \
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usbd_cdc_vcp.c \
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usbd_msc_bot.c \
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usbd_msc_data.c \
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usbd_msc_scsi.c \
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usbd_storage_msd.c \
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)
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SRC_FATFS = $(addprefix $(FATFS_DIR)/src/,\
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ff.c \
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option/ccsbcs.c \
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)
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SRC_CC3K = $(addprefix $(CC3K_DIR)/,\
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cc3000_common.c \
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evnt_handler.c \
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hci.c \
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netapp.c \
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nvmem.c \
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security.c \
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socket.c \
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wlan.c \
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ccspi.c \
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pybcc3k.c \
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)
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ifeq ($(MICROPY_PY_WIZNET5K),1)
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WIZNET5K_DIR=drivers/wiznet5k
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INC += -I$(TOP)/$(WIZNET5K_DIR)
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CFLAGS_MOD += -DMICROPY_PY_WIZNET5K=1
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SRC_MOD += modwiznet5k.c
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SRC_MOD += $(addprefix $(WIZNET5K_DIR)/,\
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ethernet/w5200/w5200.c \
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ethernet/wizchip_conf.c \
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ethernet/socket.c \
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internet/dns/dns.c \
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)
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endif
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OBJ =
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OBJ += $(PY_O)
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OBJ += $(addprefix $(BUILD)/, $(SRC_LIB:.c=.o))
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OBJ += $(addprefix $(BUILD)/, $(SRC_C:.c=.o))
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OBJ += $(addprefix $(BUILD)/, $(SRC_S:.s=.o))
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OBJ += $(addprefix $(BUILD)/, $(SRC_HAL:.c=.o))
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OBJ += $(addprefix $(BUILD)/, $(SRC_USBDEV:.c=.o))
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OBJ += $(addprefix $(BUILD)/, $(SRC_FATFS:.c=.o))
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OBJ += $(addprefix $(BUILD)/, $(SRC_CC3K:.c=.o))
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OBJ += $(addprefix $(BUILD)/, $(SRC_MOD:.c=.o))
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OBJ += $(BUILD)/pins_$(BOARD).o
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# We put ff.o and stm32f4xx_hal_sd.o into the first 16K section with the ISRs.
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# If we compile these using -O0 then it won't fit. So if you really want these
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# to be compiled with -O0, then edit stm32f405.ld (in the .isr_vector section)
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# and comment out the following 2 lines.
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$(BUILD)/$(FATFS_DIR)/src/ff.o: COPT += -Os
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$(BUILD)/$(HAL_DIR)/src/stm32f4xx_hal_sd.o: COPT += -Os
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all: $(BUILD)/firmware.dfu $(BUILD)/firmware.hex
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.PHONY: deploy
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deploy: $(BUILD)/firmware.dfu
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$(ECHO) "Writing $< to the board"
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$(Q)$(DFU_UTIL) -a 0 -d $(DEVICE) -D $<
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$(BUILD)/firmware.dfu: $(BUILD)/firmware.elf
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$(ECHO) "Create $@"
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$(Q)$(OBJCOPY) -O binary -j .isr_vector $^ $(BUILD)/firmware0.bin
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$(Q)$(OBJCOPY) -O binary -j .text -j .data $^ $(BUILD)/firmware1.bin
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$(Q)$(PYTHON) $(DFU) -b 0x08000000:$(BUILD)/firmware0.bin -b 0x08020000:$(BUILD)/firmware1.bin $@
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$(BUILD)/firmware.hex: $(BUILD)/firmware.elf
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$(ECHO) "Create $@"
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$(Q)$(OBJCOPY) -O ihex $< $@
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$(BUILD)/firmware.elf: $(OBJ)
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$(ECHO) "LINK $@"
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$(Q)$(LD) $(LDFLAGS) -o $@ $(OBJ) $(LIBS)
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$(Q)$(SIZE) $@
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MAKE_PINS = boards/make-pins.py
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BOARD_PINS = boards/$(BOARD)/pins.csv
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AF_FILE = boards/stm32f4xx_af.csv
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PREFIX_FILE = boards/stm32f4xx_prefix.c
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GEN_PINS_SRC = $(BUILD)/pins_$(BOARD).c
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GEN_PINS_HDR = $(HEADER_BUILD)/pins.h
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GEN_PINS_QSTR = $(BUILD)/pins_qstr.h
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GEN_PINS_AF_CONST = $(HEADER_BUILD)/pins_af_const.h
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GEN_PINS_AF_PY = $(BUILD)/pins_af.py
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INSERT_USB_IDS = ../tools/insert-usb-ids.py
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FILE2H = ../tools/file2h.py
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USB_IDS_FILE = usbd_desc_cdc_msc.c
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CDCINF_TEMPLATE = pybcdc.inf_template
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GEN_CDCINF_FILE = $(HEADER_BUILD)/pybcdc.inf
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GEN_CDCINF_HEADER = $(HEADER_BUILD)/pybcdc_inf.h
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# Making OBJ use an order-only depenedency on the generated pins.h file
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# has the side effect of making the pins.h file before we actually compile
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# any of the objects. The normal dependency generation will deal with the
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# case when pins.h is modified. But when it doesn't exist, we don't know
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# which source files might need it.
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$(OBJ): | $(HEADER_BUILD)/pins.h
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$(BUILD)/main.o: $(GEN_CDCINF_HEADER)
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# Use a pattern rule here so that make will only call make-pins.py once to make
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# both pins_$(BOARD).c and pins.h
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$(BUILD)/%_$(BOARD).c $(HEADER_BUILD)/%.h $(HEADER_BUILD)/%_af_const.h $(BUILD)/%_qstr.h: boards/$(BOARD)/%.csv $(MAKE_PINS) $(AF_FILE) $(PREFIX_FILE) | $(HEADER_BUILD)
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$(ECHO) "Create $@"
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$(Q)$(PYTHON) $(MAKE_PINS) --board $(BOARD_PINS) --af $(AF_FILE) --prefix $(PREFIX_FILE) --hdr $(GEN_PINS_HDR) --qstr $(GEN_PINS_QSTR) --af-const $(GEN_PINS_AF_CONST) --af-py $(GEN_PINS_AF_PY) > $(GEN_PINS_SRC)
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$(BUILD)/pins_$(BOARD).o: $(BUILD)/pins_$(BOARD).c
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$(call compile_c)
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$(GEN_CDCINF_HEADER): $(GEN_CDCINF_FILE) $(FILE2H)
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$(ECHO) "Create $@"
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$(Q)$(PYTHON) $(FILE2H) $< > $@
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$(GEN_CDCINF_FILE): $(CDCINF_TEMPLATE) $(INSERT_USB_IDS) $(USB_IDS_FILE)
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$(ECHO) "Create $@"
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$(Q)$(PYTHON) $(INSERT_USB_IDS) $(USB_IDS_FILE) $< > $@
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include ../py/mkrules.mk
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