09bc415751
This unifies the flash config to the settings used by the Boot ROM. This makes the config unique per board which allows for changing quad enable and status bit differences per flash device. It also allows for timing differences due to the board layout. This change also tweaks linker layout to leave more ram space for the CircuitPython heap.
170 lines
7.2 KiB
C
170 lines
7.2 KiB
C
/*
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* Copyright 2017 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include "fsl_flexspi_nor_boot.h"
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#include "boards/board.h"
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__attribute__((section(".boot_hdr.ivt")))
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/*************************************
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* IVT Data
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*************************************/
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const ivt image_vector_table = {
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IVT_HEADER, /* IVT Header */
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IMAGE_ENTRY_ADDRESS, /* Image Entry Function */
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IVT_RSVD, /* Reserved = 0 */
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(uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */
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(uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */
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(uint32_t)&image_vector_table, /* Pointer to IVT Self (absolute address */
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(uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */
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IVT_RSVD /* Reserved = 0 */
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};
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__attribute__((section(".boot_hdr.boot_data")))
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/*************************************
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* Boot Data
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*************************************/
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const BOOT_DATA_T boot_data = {
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FLASH_BASE, /* boot start location */
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FLASH_SIZE, /* size */
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PLUGIN_FLAG, /* Plugin flag*/
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0xFFFFFFFF /* empty - extra data word */
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};
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// Config for AT25SF128A with QSPI routed.
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__attribute__((section(".boot_hdr.conf")))
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const flexspi_nor_config_t qspiflash_config = {
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.pageSize = 256u,
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.sectorSize = 4u * 1024u,
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.ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz,
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.blockSize = 0x00010000,
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.isUniformBlockSize = false,
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.memConfig =
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{
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.tag = FLEXSPI_CFG_BLK_TAG,
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.version = FLEXSPI_CFG_BLK_VERSION,
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.readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad,
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.csHoldTime = 3u,
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.csSetupTime = 3u,
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.busyOffset = 0u, // Status bit 0 indicates busy.
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.busyBitPolarity = 0u, // Busy when the bit is 1.
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.deviceModeCfgEnable = 1u,
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.deviceModeType = kDeviceConfigCmdType_QuadEnable,
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.deviceModeSeq = {
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.seqId = 4u,
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.seqNum = 1u,
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},
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.deviceModeArg = 0x02,
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.deviceType = kFlexSpiDeviceType_SerialNOR,
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.sflashPadType = kSerialFlash_4Pads,
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.serialClkFreq = kFlexSpiSerialClk_60MHz,
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.sflashA1Size = FLASH_SIZE,
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.lookupTable =
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{
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// FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1)
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// The high 16 bits is command 1 and the low are command 0.
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// Within a command, the top 6 bits are the opcode, the next two are the number
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// of pads and then last byte is the operand. The operand's meaning changes
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// per opcode.
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// Indices with ROM should always have the same function because the ROM
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// bootloader uses it.
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// 0: ROM: Read LUTs
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// Quad version
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SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* the command to send */,
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RADDR_SDR, FLEXSPI_4PAD, 24 /* bits to transmit */),
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FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */,
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READ_SDR, FLEXSPI_4PAD, 0x04),
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// Single fast read version, good for debugging.
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// FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* the command to send */,
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// RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */),
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// FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */,
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// READ_SDR, FLEXSPI_1PAD, 0x04),
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TWO_EMPTY_STEPS,
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TWO_EMPTY_STEPS),
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// 1: ROM: Read status
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SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* the command to send */,
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READ_SDR, FLEXSPI_1PAD, 0x02),
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TWO_EMPTY_STEPS,
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TWO_EMPTY_STEPS,
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TWO_EMPTY_STEPS),
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// 2: Empty
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EMPTY_SEQUENCE,
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// 3: ROM: Write Enable
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SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */,
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STOP, FLEXSPI_1PAD, 0x00),
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TWO_EMPTY_STEPS,
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TWO_EMPTY_STEPS,
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TWO_EMPTY_STEPS),
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// 4: Config: Write Status
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SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x31 /* the command to send */,
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WRITE_SDR, FLEXSPI_1PAD, 0x01),
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TWO_EMPTY_STEPS,
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TWO_EMPTY_STEPS,
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TWO_EMPTY_STEPS),
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// 5: ROM: Erase Sector
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SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* the command to send */,
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RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */),
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TWO_EMPTY_STEPS,
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TWO_EMPTY_STEPS,
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TWO_EMPTY_STEPS),
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// 6: Empty
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EMPTY_SEQUENCE,
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// 7: Empty
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EMPTY_SEQUENCE,
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// 8: Block Erase
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SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* the command to send */,
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RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */),
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TWO_EMPTY_STEPS,
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TWO_EMPTY_STEPS,
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TWO_EMPTY_STEPS),
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// 9: ROM: Page program
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SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* the command to send */,
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RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */),
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FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */,
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STOP, FLEXSPI_1PAD, 0),
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TWO_EMPTY_STEPS,
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TWO_EMPTY_STEPS),
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// 10: Empty
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EMPTY_SEQUENCE,
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// 11: ROM: Chip erase
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SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */,
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STOP, FLEXSPI_1PAD, 0),
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TWO_EMPTY_STEPS,
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TWO_EMPTY_STEPS,
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TWO_EMPTY_STEPS),
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// 12: Empty
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EMPTY_SEQUENCE,
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// 13: ROM: Read SFDP
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EMPTY_SEQUENCE,
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// 14: ROM: Restore no cmd
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EMPTY_SEQUENCE,
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// 15: ROM: Dummy
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EMPTY_SEQUENCE
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},
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},
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};
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