322 lines
11 KiB
C
322 lines
11 KiB
C
/*
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* This file is part of the MicroPython project, http://micropython.org/
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2018 hathach for Adafruit Industries
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* Copyright (c) 2018 Scott Shawcroft for Adafruit Industries
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "supervisor/spi_flash_api.h"
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#include "supervisor/qspi_flash.h"
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#include <stdint.h>
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#include <string.h>
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#include "py/mpconfig.h" // for EXTERNAL_FLASH_QSPI_DUAL
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#include "nrfx_qspi.h"
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#include "shared-bindings/microcontroller/__init__.h"
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#include "supervisor/shared/external_flash/common_commands.h"
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#include "supervisor/shared/external_flash/qspi_flash.h"
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#ifdef QSPI_FLASH_POWERDOWN
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// Parameters for external QSPI Flash power-down
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// for W25Q128FV,
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// tDP (nCS high to Power-down mode) = 3us
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// tRES (nCS high to Standby mode) = 3us
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// sck_delay = max(tDP, tRES) / 62.5ns = 48 -> 50 (w/ margin)
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#define DUR_DPM_ENTER 1 // tDP in (256*62.5ns) units
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#define DUR_DPM_EXIT 1 // tRES in (256*62.5ns) units
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#define SCK_DELAY 50 // max(tDP, tRES) in (62.5ns) units
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// wait necessary just after DPM enter/exit (cut and try)
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#define WAIT_AFTER_DPM_ENTER 10 // usec
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#define WAIT_AFTER_DPM_EXIT 50 // usec
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static int sck_delay_saved = 0;
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#endif
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// When USB is disconnected, disable QSPI in sleep mode to save energy
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void qspi_disable(void) {
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// If VBUS is detected, no need to disable QSPI
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if (NRF_QSPI->ENABLE && !(NRF_POWER->USBREGSTATUS & POWER_USBREGSTATUS_VBUSDETECT_Msk)) {
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// Keep CS high when QSPI is diabled
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nrf_gpio_cfg_output(MICROPY_QSPI_CS);
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nrf_gpio_pin_write(MICROPY_QSPI_CS, 1);
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// Workaround to disable QSPI according to nRF52840 Revision 1 Errata V1.4 - 3.8
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NRF_QSPI->TASKS_DEACTIVATE = 1;
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*(volatile uint32_t *)0x40029054 = 1;
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NRF_QSPI->ENABLE = 0;
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}
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}
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STATIC void qspi_enable(void) {
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if (NRF_QSPI->ENABLE) {
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return;
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}
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nrf_qspi_enable(NRF_QSPI);
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nrf_qspi_event_clear(NRF_QSPI, NRF_QSPI_EVENT_READY);
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nrf_qspi_task_trigger(NRF_QSPI, NRF_QSPI_TASK_ACTIVATE);
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uint32_t remaining_attempts = 100;
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do {
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if (nrf_qspi_event_check(NRF_QSPI, NRF_QSPI_EVENT_READY)) {
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break;
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}
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NRFX_DELAY_US(10);
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} while (--remaining_attempts);
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}
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bool spi_flash_command(uint8_t command) {
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qspi_enable();
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nrf_qspi_cinstr_conf_t cinstr_cfg = {
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.opcode = command,
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.length = 1,
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.io2_level = true,
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.io3_level = true,
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.wipwait = false,
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.wren = false
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};
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return nrfx_qspi_cinstr_xfer(&cinstr_cfg, NULL, NULL) == NRFX_SUCCESS;
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}
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bool spi_flash_read_command(uint8_t command, uint8_t *response, uint32_t length) {
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qspi_enable();
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nrf_qspi_cinstr_conf_t cinstr_cfg = {
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.opcode = command,
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.length = length + 1,
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.io2_level = true,
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.io3_level = true,
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.wipwait = false,
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.wren = false
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};
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return nrfx_qspi_cinstr_xfer(&cinstr_cfg, NULL, response) == NRFX_SUCCESS;
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}
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bool spi_flash_write_command(uint8_t command, uint8_t *data, uint32_t length) {
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qspi_enable();
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nrf_qspi_cinstr_conf_t cinstr_cfg = {
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.opcode = command,
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.length = length + 1,
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.io2_level = true,
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.io3_level = true,
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.wipwait = false,
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.wren = false // We do this manually.
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};
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return nrfx_qspi_cinstr_xfer(&cinstr_cfg, data, NULL) == NRFX_SUCCESS;
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}
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bool spi_flash_sector_command(uint8_t command, uint32_t address) {
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qspi_enable();
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if (command != CMD_SECTOR_ERASE) {
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return false;
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}
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return nrfx_qspi_erase(NRF_QSPI_ERASE_LEN_4KB, address) == NRFX_SUCCESS;
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}
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bool spi_flash_write_data(uint32_t address, uint8_t *data, uint32_t length) {
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qspi_enable();
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// TODO: In theory, this also needs to handle unaligned data and
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// non-multiple-of-4 length. (in practice, I don't think the fat layer
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// generates such writes)
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return nrfx_qspi_write(data, length, address) == NRFX_SUCCESS;
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}
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bool spi_flash_read_data(uint32_t address, uint8_t *data, uint32_t length) {
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qspi_enable();
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int misaligned = ((intptr_t)data) & 3;
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// If the data is misaligned, we need to read 4 bytes
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// into an aligned buffer, and then copy 1, 2, or 3 bytes from the aligned
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// buffer to data.
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if (misaligned) {
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int sz = 4 - misaligned;
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__attribute__((aligned(4))) uint8_t buf[4];
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if (nrfx_qspi_read(buf, 4, address) != NRFX_SUCCESS) {
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return false;
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}
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memcpy(data, buf, sz);
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data += sz;
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address += sz;
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length -= sz;
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}
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// nrfx_qspi_read works in 4 byte increments, though it doesn't
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// signal an error if sz is not a multiple of 4. Read (directly into data)
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// all but the last 1, 2, or 3 bytes depending on the (remaining) length.
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uint32_t sz = length & ~(uint32_t)3;
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if (nrfx_qspi_read(data, sz, address) != NRFX_SUCCESS) {
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return false;
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}
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data += sz;
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address += sz;
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length -= sz;
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// Now, if we have any bytes left over, we must do a final read of 4
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// bytes and copy 1, 2, or 3 bytes to data.
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if (length) {
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__attribute__((aligned(4))) uint8_t buf[4];
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if (nrfx_qspi_read(buf, 4, address) != NRFX_SUCCESS) {
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return false;
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}
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memcpy(data, buf, length);
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}
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return true;
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}
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void spi_flash_init(void) {
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// Init QSPI flash
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nrfx_qspi_config_t qspi_cfg = {
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.xip_offset = 0,
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.pins = {
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.sck_pin = MICROPY_QSPI_SCK,
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.csn_pin = MICROPY_QSPI_CS,
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.io0_pin = MICROPY_QSPI_DATA0,
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.io1_pin = NRF_QSPI_PIN_NOT_CONNECTED,
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.io2_pin = NRF_QSPI_PIN_NOT_CONNECTED,
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.io3_pin = NRF_QSPI_PIN_NOT_CONNECTED,
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},
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.prot_if = {
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.readoc = NRF_QSPI_READOC_FASTREAD,
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.writeoc = NRF_QSPI_WRITEOC_PP,
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.addrmode = NRF_QSPI_ADDRMODE_24BIT,
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#ifdef QSPI_FLASH_POWERDOWN
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.dpmconfig = true
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#else
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.dpmconfig = false
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#endif
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},
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.phy_if = {
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.sck_freq = NRF_QSPI_FREQ_32MDIV16, // Start at a slow 2MHz and speed up once we know what we're talking to.
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.sck_delay = 10, // min time CS must stay high before going low again. in unit of 62.5 ns
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.spi_mode = NRF_QSPI_MODE_0,
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.dpmen = false
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},
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.irq_priority = 7,
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};
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#if defined(EXTERNAL_FLASH_QSPI_DUAL)
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qspi_cfg.pins.io1_pin = MICROPY_QSPI_DATA1;
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qspi_cfg.prot_if.readoc = NRF_QSPI_READOC_READ2O;
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qspi_cfg.prot_if.writeoc = NRF_QSPI_WRITEOC_PP2O;
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#else
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qspi_cfg.pins.io1_pin = MICROPY_QSPI_DATA1;
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qspi_cfg.pins.io2_pin = MICROPY_QSPI_DATA2;
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qspi_cfg.pins.io3_pin = MICROPY_QSPI_DATA3;
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qspi_cfg.prot_if.readoc = NRF_QSPI_READOC_READ4IO;
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qspi_cfg.prot_if.writeoc = NRF_QSPI_WRITEOC_PP4O;
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#endif
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// No callback for blocking API
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nrfx_qspi_init(&qspi_cfg, NULL, NULL);
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#ifdef QSPI_FLASH_POWERDOWN
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// If pin-reset while flash is in power-down mode,
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// the flash cannot accept any commands. Send CMD_WAKE to release it.
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spi_flash_write_command(CMD_WAKE, NULL, 0);
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NRFX_DELAY_US(WAIT_AFTER_DPM_EXIT);
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#endif
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}
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void spi_flash_init_device(const external_flash_device *device) {
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check_quad_enable(device);
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// Switch to single output line if the device doesn't support quad programs.
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if (!device->supports_qspi_writes) {
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NRF_QSPI->IFCONFIG0 &= ~QSPI_IFCONFIG0_WRITEOC_Msk;
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NRF_QSPI->IFCONFIG0 |= QSPI_IFCONFIG0_WRITEOC_PP << QSPI_IFCONFIG0_WRITEOC_Pos;
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}
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// Speed up as much as we can.
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// Start at 16 MHz and go down.
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// At 32 MHz GD25Q16C doesn't work reliably on Feather 52840, even though it should work up to 104 MHz.
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// sckfreq = 0 is 32 Mhz
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// sckfreq = 1 is 16 MHz, etc.
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uint8_t sckfreq = 1;
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while (32000000 / (sckfreq + 1) > device->max_clock_speed_mhz * 1000000 && sckfreq < 16) {
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sckfreq += 1;
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}
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NRF_QSPI->IFCONFIG1 &= ~QSPI_IFCONFIG1_SCKFREQ_Msk;
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NRF_QSPI->IFCONFIG1 |= sckfreq << QSPI_IFCONFIG1_SCKFREQ_Pos;
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}
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void qspi_flash_enter_sleep(void) {
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#ifdef QSPI_FLASH_POWERDOWN
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uint32_t r;
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NRF_QSPI->DPMDUR =
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((DUR_DPM_ENTER & 0xFFFF) << 16) | (DUR_DPM_EXIT & 0xFFFF);
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// set sck_delay tempolarily
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r = NRF_QSPI->IFCONFIG1;
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sck_delay_saved = (r & QSPI_IFCONFIG1_SCKDELAY_Msk)
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>> QSPI_IFCONFIG1_SCKDELAY_Pos;
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NRF_QSPI->IFCONFIG1
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= (NRF_QSPI->IFCONFIG1 & ~QSPI_IFCONFIG1_SCKDELAY_Msk)
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| (SCK_DELAY << QSPI_IFCONFIG1_SCKDELAY_Pos);
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// enabling IFCONFIG0.DPMENABLE here won't work.
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// -> do it in spi_flash_init()
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// NRF_QSPI->IFCONFIG0 |= QSPI_IFCONFIG0_DPMENABLE_Msk;
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// enter deep power-down mode (DPM)
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NRF_QSPI->IFCONFIG1 |= QSPI_IFCONFIG1_DPMEN_Msk;
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NRFX_DELAY_US(WAIT_AFTER_DPM_ENTER);
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if (!(NRF_QSPI->STATUS & QSPI_STATUS_DPM_Msk)) {
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#ifdef NRF_DEBUG_PRINT
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mp_printf(&mp_plat_print, "qspi flash: DPM failed\r\n");
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#endif
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}
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#endif
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qspi_disable();
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}
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void qspi_flash_exit_sleep(void) {
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qspi_enable();
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#ifdef QSPI_FLASH_POWERDOWN
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if (NRF_QSPI->STATUS & QSPI_STATUS_DPM_Msk) {
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// exit deep power-down mode
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NRF_QSPI->IFCONFIG1 &= ~QSPI_IFCONFIG1_DPMEN_Msk;
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NRFX_DELAY_US(WAIT_AFTER_DPM_EXIT);
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if (NRF_QSPI->STATUS & QSPI_STATUS_DPM_Msk) {
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#ifdef NRF_DEBUG_PRINT
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mp_printf(&mp_plat_print, "qspi flash: exiting DPM failed\r\n");
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#endif
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}
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// restore sck_delay
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if (sck_delay_saved == 0) {
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sck_delay_saved = 10; // default
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}
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NRF_QSPI->IFCONFIG1
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= (NRF_QSPI->IFCONFIG1 & ~QSPI_IFCONFIG1_SCKDELAY_Msk)
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| (sck_delay_saved << QSPI_IFCONFIG1_SCKDELAY_Pos);
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}
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#endif
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}
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