870 lines
22 KiB
C
870 lines
22 KiB
C
/**
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******************************************************************************
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* @file usb_dcd_int.c
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* @author MCD Application Team
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* @version V2.1.0
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* @date 19-March-2012
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* @brief Peripheral Device interrupt subroutines
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
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*
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* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
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* You may not use this file except in compliance with the License.
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* You may obtain a copy of the License at:
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*
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* http://www.st.com/software_license_agreement_liberty_v2
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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******************************************************************************
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*/
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/* Includes ------------------------------------------------------------------*/
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#include "usb_dcd_int.h"
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/** @addtogroup USB_OTG_DRIVER
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* @{
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*/
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/** @defgroup USB_DCD_INT
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* @brief This file contains the interrupt subroutines for the Device mode.
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* @{
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*/
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/** @defgroup USB_DCD_INT_Private_Defines
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* @{
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*/
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/**
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* @}
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*/
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/** @defgroup USB_DCD_INT_Private_TypesDefinitions
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* @{
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*/
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/**
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* @}
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*/
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/** @defgroup USB_DCD_INT_Private_Macros
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* @{
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*/
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/**
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* @}
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*/
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/** @defgroup USB_DCD_INT_Private_Variables
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* @{
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*/
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/**
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* @}
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*/
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/** @defgroup USB_DCD_INT_Private_FunctionPrototypes
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* @{
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*/
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/* static functions */
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static uint32_t DCD_ReadDevInEP (USB_OTG_CORE_HANDLE *pdev, uint8_t epnum);
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/* Interrupt Handlers */
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static uint32_t DCD_HandleInEP_ISR(USB_OTG_CORE_HANDLE *pdev);
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static uint32_t DCD_HandleOutEP_ISR(USB_OTG_CORE_HANDLE *pdev);
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static uint32_t DCD_HandleSof_ISR(USB_OTG_CORE_HANDLE *pdev);
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static uint32_t DCD_HandleRxStatusQueueLevel_ISR(USB_OTG_CORE_HANDLE *pdev);
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static uint32_t DCD_WriteEmptyTxFifo(USB_OTG_CORE_HANDLE *pdev , uint32_t epnum);
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static uint32_t DCD_HandleUsbReset_ISR(USB_OTG_CORE_HANDLE *pdev);
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static uint32_t DCD_HandleEnumDone_ISR(USB_OTG_CORE_HANDLE *pdev);
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static uint32_t DCD_HandleResume_ISR(USB_OTG_CORE_HANDLE *pdev);
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static uint32_t DCD_HandleUSBSuspend_ISR(USB_OTG_CORE_HANDLE *pdev);
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static uint32_t DCD_IsoINIncomplete_ISR(USB_OTG_CORE_HANDLE *pdev);
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static uint32_t DCD_IsoOUTIncomplete_ISR(USB_OTG_CORE_HANDLE *pdev);
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#ifdef VBUS_SENSING_ENABLED
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static uint32_t DCD_SessionRequest_ISR(USB_OTG_CORE_HANDLE *pdev);
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static uint32_t DCD_OTG_ISR(USB_OTG_CORE_HANDLE *pdev);
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#endif
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/**
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* @}
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*/
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/** @defgroup USB_DCD_INT_Private_Functions
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* @{
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*/
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#ifdef USB_OTG_HS_DEDICATED_EP1_ENABLED
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/**
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* @brief USBD_OTG_EP1OUT_ISR_Handler
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* handles all USB Interrupts
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* @param pdev: device instance
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* @retval status
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*/
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uint32_t USBD_OTG_EP1OUT_ISR_Handler (USB_OTG_CORE_HANDLE *pdev)
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{
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USB_OTG_DOEPINTn_TypeDef doepint;
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USB_OTG_DEPXFRSIZ_TypeDef deptsiz;
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doepint.d32 = USB_OTG_READ_REG32(&pdev->regs.OUTEP_REGS[1]->DOEPINT);
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doepint.d32&= USB_OTG_READ_REG32(&pdev->regs.DREGS->DOUTEP1MSK);
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/* Transfer complete */
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if ( doepint.b.xfercompl )
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{
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/* Clear the bit in DOEPINTn for this interrupt */
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CLEAR_OUT_EP_INTR(1, xfercompl);
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if (pdev->cfg.dma_enable == 1)
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{
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deptsiz.d32 = USB_OTG_READ_REG32(&(pdev->regs.OUTEP_REGS[1]->DOEPTSIZ));
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/*ToDo : handle more than one single MPS size packet */
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pdev->dev.out_ep[1].xfer_count = pdev->dev.out_ep[1].maxpacket - \
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deptsiz.b.xfersize;
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}
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/* Inform upper layer: data ready */
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/* RX COMPLETE */
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USBD_DCD_INT_fops->DataOutStage(pdev , 1);
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}
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/* Endpoint disable */
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if ( doepint.b.epdisabled )
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{
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/* Clear the bit in DOEPINTn for this interrupt */
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CLEAR_OUT_EP_INTR(1, epdisabled);
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}
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return 1;
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}
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/**
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* @brief USBD_OTG_EP1IN_ISR_Handler
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* handles all USB Interrupts
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* @param pdev: device instance
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* @retval status
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*/
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uint32_t USBD_OTG_EP1IN_ISR_Handler (USB_OTG_CORE_HANDLE *pdev)
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{
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USB_OTG_DIEPINTn_TypeDef diepint;
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uint32_t fifoemptymsk, msk, emp;
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msk = USB_OTG_READ_REG32(&pdev->regs.DREGS->DINEP1MSK);
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emp = USB_OTG_READ_REG32(&pdev->regs.DREGS->DIEPEMPMSK);
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msk |= ((emp >> 1 ) & 0x1) << 7;
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diepint.d32 = USB_OTG_READ_REG32(&pdev->regs.INEP_REGS[1]->DIEPINT) & msk;
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if ( diepint.b.xfercompl )
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{
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fifoemptymsk = 0x1 << 1;
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USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DIEPEMPMSK, fifoemptymsk, 0);
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CLEAR_IN_EP_INTR(1, xfercompl);
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/* TX COMPLETE */
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USBD_DCD_INT_fops->DataInStage(pdev , 1);
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}
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if ( diepint.b.epdisabled )
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{
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CLEAR_IN_EP_INTR(1, epdisabled);
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}
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if ( diepint.b.timeout )
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{
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CLEAR_IN_EP_INTR(1, timeout);
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}
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if (diepint.b.intktxfemp)
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{
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CLEAR_IN_EP_INTR(1, intktxfemp);
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}
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if (diepint.b.inepnakeff)
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{
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CLEAR_IN_EP_INTR(1, inepnakeff);
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}
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if (diepint.b.emptyintr)
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{
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DCD_WriteEmptyTxFifo(pdev , 1);
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CLEAR_IN_EP_INTR(1, emptyintr);
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}
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return 1;
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}
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#endif
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/**
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* @brief STM32_USBF_OTG_ISR_Handler
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* handles all USB Interrupts
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* @param pdev: device instance
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* @retval status
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*/
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uint32_t USBD_OTG_ISR_Handler (USB_OTG_CORE_HANDLE *pdev)
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{
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USB_OTG_GINTSTS_TypeDef gintr_status;
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uint32_t retval = 0;
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if (USB_OTG_IsDeviceMode(pdev)) /* ensure that we are in device mode */
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{
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gintr_status.d32 = USB_OTG_ReadCoreItr(pdev);
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if (!gintr_status.d32) /* avoid spurious interrupt */
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{
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return 0;
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}
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if (gintr_status.b.outepintr)
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{
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retval |= DCD_HandleOutEP_ISR(pdev);
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}
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if (gintr_status.b.inepint)
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{
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retval |= DCD_HandleInEP_ISR(pdev);
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}
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if (gintr_status.b.modemismatch)
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{
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USB_OTG_GINTSTS_TypeDef gintsts;
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/* Clear interrupt */
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gintsts.d32 = 0;
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gintsts.b.modemismatch = 1;
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USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTSTS, gintsts.d32);
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}
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if (gintr_status.b.wkupintr)
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{
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retval |= DCD_HandleResume_ISR(pdev);
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}
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if (gintr_status.b.usbsuspend)
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{
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retval |= DCD_HandleUSBSuspend_ISR(pdev);
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}
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if (gintr_status.b.sofintr)
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{
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retval |= DCD_HandleSof_ISR(pdev);
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}
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if (gintr_status.b.rxstsqlvl)
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{
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retval |= DCD_HandleRxStatusQueueLevel_ISR(pdev);
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}
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if (gintr_status.b.usbreset)
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{
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retval |= DCD_HandleUsbReset_ISR(pdev);
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}
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if (gintr_status.b.enumdone)
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{
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retval |= DCD_HandleEnumDone_ISR(pdev);
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}
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if (gintr_status.b.incomplisoin)
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{
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retval |= DCD_IsoINIncomplete_ISR(pdev);
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}
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if (gintr_status.b.incomplisoout)
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{
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retval |= DCD_IsoOUTIncomplete_ISR(pdev);
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}
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#ifdef VBUS_SENSING_ENABLED
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if (gintr_status.b.sessreqintr)
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{
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retval |= DCD_SessionRequest_ISR(pdev);
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}
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if (gintr_status.b.otgintr)
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{
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retval |= DCD_OTG_ISR(pdev);
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}
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#endif
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}
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return retval;
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}
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#ifdef VBUS_SENSING_ENABLED
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/**
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* @brief DCD_SessionRequest_ISR
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* Indicates that the USB_OTG controller has detected a connection
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* @param pdev: device instance
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* @retval status
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*/
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static uint32_t DCD_SessionRequest_ISR(USB_OTG_CORE_HANDLE *pdev)
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{
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USB_OTG_GINTSTS_TypeDef gintsts;
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USBD_DCD_INT_fops->DevConnected (pdev);
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/* Clear interrupt */
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gintsts.d32 = 0;
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gintsts.b.sessreqintr = 1;
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USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GINTSTS, gintsts.d32);
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return 1;
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}
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/**
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* @brief DCD_OTG_ISR
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* Indicates that the USB_OTG controller has detected an OTG event:
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* used to detect the end of session i.e. disconnection
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* @param pdev: device instance
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* @retval status
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*/
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static uint32_t DCD_OTG_ISR(USB_OTG_CORE_HANDLE *pdev)
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{
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USB_OTG_GOTGINT_TypeDef gotgint;
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gotgint.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GOTGINT);
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if (gotgint.b.sesenddet)
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{
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USBD_DCD_INT_fops->DevDisconnected (pdev);
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}
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/* Clear OTG interrupt */
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USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GOTGINT, gotgint.d32);
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return 1;
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}
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#endif
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/**
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* @brief DCD_HandleResume_ISR
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* Indicates that the USB_OTG controller has detected a resume or
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* remote Wake-up sequence
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* @param pdev: device instance
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* @retval status
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*/
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static uint32_t DCD_HandleResume_ISR(USB_OTG_CORE_HANDLE *pdev)
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{
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USB_OTG_GINTSTS_TypeDef gintsts;
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USB_OTG_DCTL_TypeDef devctl;
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USB_OTG_PCGCCTL_TypeDef power;
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if(pdev->cfg.low_power)
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{
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/* un-gate USB Core clock */
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power.d32 = USB_OTG_READ_REG32(&pdev->regs.PCGCCTL);
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power.b.gatehclk = 0;
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power.b.stoppclk = 0;
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USB_OTG_WRITE_REG32(pdev->regs.PCGCCTL, power.d32);
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}
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/* Clear the Remote Wake-up Signaling */
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devctl.d32 = 0;
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devctl.b.rmtwkupsig = 1;
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USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DCTL, devctl.d32, 0);
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/* Inform upper layer by the Resume Event */
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USBD_DCD_INT_fops->Resume (pdev);
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/* Clear interrupt */
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gintsts.d32 = 0;
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gintsts.b.wkupintr = 1;
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USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GINTSTS, gintsts.d32);
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return 1;
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}
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/**
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* @brief USB_OTG_HandleUSBSuspend_ISR
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* Indicates that SUSPEND state has been detected on the USB
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* @param pdev: device instance
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* @retval status
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*/
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static uint32_t DCD_HandleUSBSuspend_ISR(USB_OTG_CORE_HANDLE *pdev)
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{
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USB_OTG_GINTSTS_TypeDef gintsts;
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USB_OTG_PCGCCTL_TypeDef power;
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USB_OTG_DSTS_TypeDef dsts;
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__IO uint8_t prev_status = 0;
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prev_status = pdev->dev.device_status;
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USBD_DCD_INT_fops->Suspend (pdev);
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dsts.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DSTS);
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/* Clear interrupt */
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gintsts.d32 = 0;
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gintsts.b.usbsuspend = 1;
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USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTSTS, gintsts.d32);
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if((pdev->cfg.low_power) && (dsts.b.suspsts == 1) &&
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(pdev->dev.connection_status == 1) &&
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(prev_status == USB_OTG_CONFIGURED))
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{
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/* switch-off the clocks */
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power.d32 = 0;
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power.b.stoppclk = 1;
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USB_OTG_MODIFY_REG32(pdev->regs.PCGCCTL, 0, power.d32);
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power.b.gatehclk = 1;
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USB_OTG_MODIFY_REG32(pdev->regs.PCGCCTL, 0, power.d32);
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/* Request to enter Sleep mode after exit from current ISR */
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SCB->SCR |= (SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk);
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}
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return 1;
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}
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/**
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* @brief DCD_HandleInEP_ISR
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* Indicates that an IN EP has a pending Interrupt
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* @param pdev: device instance
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* @retval status
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*/
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static uint32_t DCD_HandleInEP_ISR(USB_OTG_CORE_HANDLE *pdev)
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{
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USB_OTG_DIEPINTn_TypeDef diepint;
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uint32_t ep_intr;
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uint32_t epnum = 0;
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uint32_t fifoemptymsk;
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diepint.d32 = 0;
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ep_intr = USB_OTG_ReadDevAllInEPItr(pdev);
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while ( ep_intr )
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{
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if (ep_intr&0x1) /* In ITR */
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{
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diepint.d32 = DCD_ReadDevInEP(pdev , epnum); /* Get In ITR status */
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if ( diepint.b.xfercompl )
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{
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fifoemptymsk = 0x1 << epnum;
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USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DIEPEMPMSK, fifoemptymsk, 0);
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CLEAR_IN_EP_INTR(epnum, xfercompl);
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/* TX COMPLETE */
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USBD_DCD_INT_fops->DataInStage(pdev , epnum);
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if (pdev->cfg.dma_enable == 1)
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{
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if((epnum == 0) && (pdev->dev.device_state == USB_OTG_EP0_STATUS_IN))
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{
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/* prepare to rx more setup packets */
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USB_OTG_EP0_OutStart(pdev);
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}
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}
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}
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if ( diepint.b.timeout )
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{
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CLEAR_IN_EP_INTR(epnum, timeout);
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}
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if (diepint.b.intktxfemp)
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{
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CLEAR_IN_EP_INTR(epnum, intktxfemp);
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}
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if (diepint.b.inepnakeff)
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{
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CLEAR_IN_EP_INTR(epnum, inepnakeff);
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}
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if ( diepint.b.epdisabled )
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{
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CLEAR_IN_EP_INTR(epnum, epdisabled);
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}
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if (diepint.b.emptyintr)
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{
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DCD_WriteEmptyTxFifo(pdev , epnum);
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CLEAR_IN_EP_INTR(epnum, emptyintr);
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}
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}
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epnum++;
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ep_intr >>= 1;
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}
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return 1;
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}
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/**
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* @brief DCD_HandleOutEP_ISR
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* Indicates that an OUT EP has a pending Interrupt
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* @param pdev: device instance
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* @retval status
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*/
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static uint32_t DCD_HandleOutEP_ISR(USB_OTG_CORE_HANDLE *pdev)
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{
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uint32_t ep_intr;
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USB_OTG_DOEPINTn_TypeDef doepint;
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USB_OTG_DEPXFRSIZ_TypeDef deptsiz;
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uint32_t epnum = 0;
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doepint.d32 = 0;
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/* Read in the device interrupt bits */
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ep_intr = USB_OTG_ReadDevAllOutEp_itr(pdev);
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while ( ep_intr )
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{
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if (ep_intr&0x1)
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{
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doepint.d32 = USB_OTG_ReadDevOutEP_itr(pdev, epnum);
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/* Transfer complete */
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if ( doepint.b.xfercompl )
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{
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/* Clear the bit in DOEPINTn for this interrupt */
|
|
CLEAR_OUT_EP_INTR(epnum, xfercompl);
|
|
if (pdev->cfg.dma_enable == 1)
|
|
{
|
|
deptsiz.d32 = USB_OTG_READ_REG32(&(pdev->regs.OUTEP_REGS[epnum]->DOEPTSIZ));
|
|
/*ToDo : handle more than one single MPS size packet */
|
|
pdev->dev.out_ep[epnum].xfer_count = pdev->dev.out_ep[epnum].maxpacket - \
|
|
deptsiz.b.xfersize;
|
|
}
|
|
/* Inform upper layer: data ready */
|
|
/* RX COMPLETE */
|
|
USBD_DCD_INT_fops->DataOutStage(pdev , epnum);
|
|
|
|
if (pdev->cfg.dma_enable == 1)
|
|
{
|
|
if((epnum == 0) && (pdev->dev.device_state == USB_OTG_EP0_STATUS_OUT))
|
|
{
|
|
/* prepare to rx more setup packets */
|
|
USB_OTG_EP0_OutStart(pdev);
|
|
}
|
|
}
|
|
}
|
|
/* Endpoint disable */
|
|
if ( doepint.b.epdisabled )
|
|
{
|
|
/* Clear the bit in DOEPINTn for this interrupt */
|
|
CLEAR_OUT_EP_INTR(epnum, epdisabled);
|
|
}
|
|
/* Setup Phase Done (control EPs) */
|
|
if ( doepint.b.setup )
|
|
{
|
|
|
|
/* inform the upper layer that a setup packet is available */
|
|
/* SETUP COMPLETE */
|
|
USBD_DCD_INT_fops->SetupStage(pdev);
|
|
CLEAR_OUT_EP_INTR(epnum, setup);
|
|
}
|
|
}
|
|
epnum++;
|
|
ep_intr >>= 1;
|
|
}
|
|
return 1;
|
|
}
|
|
|
|
/**
|
|
* @brief DCD_HandleSof_ISR
|
|
* Handles the SOF Interrupts
|
|
* @param pdev: device instance
|
|
* @retval status
|
|
*/
|
|
static uint32_t DCD_HandleSof_ISR(USB_OTG_CORE_HANDLE *pdev)
|
|
{
|
|
USB_OTG_GINTSTS_TypeDef GINTSTS;
|
|
|
|
|
|
USBD_DCD_INT_fops->SOF(pdev);
|
|
|
|
/* Clear interrupt */
|
|
GINTSTS.d32 = 0;
|
|
GINTSTS.b.sofintr = 1;
|
|
USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GINTSTS, GINTSTS.d32);
|
|
|
|
return 1;
|
|
}
|
|
|
|
/**
|
|
* @brief DCD_HandleRxStatusQueueLevel_ISR
|
|
* Handles the Rx Status Queue Level Interrupt
|
|
* @param pdev: device instance
|
|
* @retval status
|
|
*/
|
|
static uint32_t DCD_HandleRxStatusQueueLevel_ISR(USB_OTG_CORE_HANDLE *pdev)
|
|
{
|
|
USB_OTG_GINTMSK_TypeDef int_mask;
|
|
USB_OTG_DRXSTS_TypeDef status;
|
|
USB_OTG_EP *ep;
|
|
|
|
/* Disable the Rx Status Queue Level interrupt */
|
|
int_mask.d32 = 0;
|
|
int_mask.b.rxstsqlvl = 1;
|
|
USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, int_mask.d32, 0);
|
|
|
|
/* Get the Status from the top of the FIFO */
|
|
status.d32 = USB_OTG_READ_REG32( &pdev->regs.GREGS->GRXSTSP );
|
|
|
|
ep = &pdev->dev.out_ep[status.b.epnum];
|
|
|
|
switch (status.b.pktsts)
|
|
{
|
|
case STS_GOUT_NAK:
|
|
break;
|
|
case STS_DATA_UPDT:
|
|
if (status.b.bcnt)
|
|
{
|
|
USB_OTG_ReadPacket(pdev,ep->xfer_buff, status.b.bcnt);
|
|
ep->xfer_buff += status.b.bcnt;
|
|
ep->xfer_count += status.b.bcnt;
|
|
}
|
|
break;
|
|
case STS_XFER_COMP:
|
|
break;
|
|
case STS_SETUP_COMP:
|
|
break;
|
|
case STS_SETUP_UPDT:
|
|
/* Copy the setup packet received in FIFO into the setup buffer in RAM */
|
|
USB_OTG_ReadPacket(pdev , pdev->dev.setup_packet, 8);
|
|
ep->xfer_count += status.b.bcnt;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
/* Enable the Rx Status Queue Level interrupt */
|
|
USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, 0, int_mask.d32);
|
|
|
|
return 1;
|
|
}
|
|
|
|
/**
|
|
* @brief DCD_WriteEmptyTxFifo
|
|
* check FIFO for the next packet to be loaded
|
|
* @param pdev: device instance
|
|
* @retval status
|
|
*/
|
|
static uint32_t DCD_WriteEmptyTxFifo(USB_OTG_CORE_HANDLE *pdev, uint32_t epnum)
|
|
{
|
|
USB_OTG_DTXFSTSn_TypeDef txstatus;
|
|
USB_OTG_EP *ep;
|
|
uint32_t len = 0;
|
|
uint32_t len32b;
|
|
txstatus.d32 = 0;
|
|
|
|
ep = &pdev->dev.in_ep[epnum];
|
|
|
|
len = ep->xfer_len - ep->xfer_count;
|
|
|
|
if (len > ep->maxpacket)
|
|
{
|
|
len = ep->maxpacket;
|
|
}
|
|
|
|
len32b = (len + 3) / 4;
|
|
txstatus.d32 = USB_OTG_READ_REG32( &pdev->regs.INEP_REGS[epnum]->DTXFSTS);
|
|
|
|
|
|
|
|
while (txstatus.b.txfspcavail > len32b &&
|
|
ep->xfer_count < ep->xfer_len &&
|
|
ep->xfer_len != 0)
|
|
{
|
|
/* Write the FIFO */
|
|
len = ep->xfer_len - ep->xfer_count;
|
|
|
|
if (len > ep->maxpacket)
|
|
{
|
|
len = ep->maxpacket;
|
|
}
|
|
len32b = (len + 3) / 4;
|
|
|
|
USB_OTG_WritePacket (pdev , ep->xfer_buff, epnum, len);
|
|
|
|
ep->xfer_buff += len;
|
|
ep->xfer_count += len;
|
|
|
|
txstatus.d32 = USB_OTG_READ_REG32(&pdev->regs.INEP_REGS[epnum]->DTXFSTS);
|
|
}
|
|
|
|
return 1;
|
|
}
|
|
|
|
/**
|
|
* @brief DCD_HandleUsbReset_ISR
|
|
* This interrupt occurs when a USB Reset is detected
|
|
* @param pdev: device instance
|
|
* @retval status
|
|
*/
|
|
static uint32_t DCD_HandleUsbReset_ISR(USB_OTG_CORE_HANDLE *pdev)
|
|
{
|
|
USB_OTG_DAINT_TypeDef daintmsk;
|
|
USB_OTG_DOEPMSK_TypeDef doepmsk;
|
|
USB_OTG_DIEPMSK_TypeDef diepmsk;
|
|
USB_OTG_DCFG_TypeDef dcfg;
|
|
USB_OTG_DCTL_TypeDef dctl;
|
|
USB_OTG_GINTSTS_TypeDef gintsts;
|
|
uint32_t i;
|
|
|
|
dctl.d32 = 0;
|
|
daintmsk.d32 = 0;
|
|
doepmsk.d32 = 0;
|
|
diepmsk.d32 = 0;
|
|
dcfg.d32 = 0;
|
|
gintsts.d32 = 0;
|
|
|
|
/* Clear the Remote Wake-up Signaling */
|
|
dctl.b.rmtwkupsig = 1;
|
|
USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DCTL, dctl.d32, 0 );
|
|
|
|
/* Flush the Tx FIFO */
|
|
USB_OTG_FlushTxFifo(pdev , 0 );
|
|
|
|
for (i = 0; i < pdev->cfg.dev_endpoints ; i++)
|
|
{
|
|
USB_OTG_WRITE_REG32( &pdev->regs.INEP_REGS[i]->DIEPINT, 0xFF);
|
|
USB_OTG_WRITE_REG32( &pdev->regs.OUTEP_REGS[i]->DOEPINT, 0xFF);
|
|
}
|
|
USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DAINT, 0xFFFFFFFF );
|
|
|
|
daintmsk.ep.in = 1;
|
|
daintmsk.ep.out = 1;
|
|
USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DAINTMSK, daintmsk.d32 );
|
|
|
|
doepmsk.b.setup = 1;
|
|
doepmsk.b.xfercompl = 1;
|
|
doepmsk.b.epdisabled = 1;
|
|
USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DOEPMSK, doepmsk.d32 );
|
|
#ifdef USB_OTG_HS_DEDICATED_EP1_ENABLED
|
|
USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DOUTEP1MSK, doepmsk.d32 );
|
|
#endif
|
|
diepmsk.b.xfercompl = 1;
|
|
diepmsk.b.timeout = 1;
|
|
diepmsk.b.epdisabled = 1;
|
|
|
|
USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DIEPMSK, diepmsk.d32 );
|
|
#ifdef USB_OTG_HS_DEDICATED_EP1_ENABLED
|
|
USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DINEP1MSK, diepmsk.d32 );
|
|
#endif
|
|
/* Reset Device Address */
|
|
dcfg.d32 = USB_OTG_READ_REG32( &pdev->regs.DREGS->DCFG);
|
|
dcfg.b.devaddr = 0;
|
|
USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DCFG, dcfg.d32);
|
|
|
|
|
|
/* setup EP0 to receive SETUP packets */
|
|
USB_OTG_EP0_OutStart(pdev);
|
|
|
|
/* Clear interrupt */
|
|
gintsts.d32 = 0;
|
|
gintsts.b.usbreset = 1;
|
|
USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GINTSTS, gintsts.d32);
|
|
|
|
/*Reset internal state machine */
|
|
USBD_DCD_INT_fops->Reset(pdev);
|
|
return 1;
|
|
}
|
|
|
|
/**
|
|
* @brief DCD_HandleEnumDone_ISR
|
|
* Read the device status register and set the device speed
|
|
* @param pdev: device instance
|
|
* @retval status
|
|
*/
|
|
static uint32_t DCD_HandleEnumDone_ISR(USB_OTG_CORE_HANDLE *pdev)
|
|
{
|
|
USB_OTG_GINTSTS_TypeDef gintsts;
|
|
USB_OTG_GUSBCFG_TypeDef gusbcfg;
|
|
|
|
USB_OTG_EP0Activate(pdev);
|
|
|
|
/* Set USB turn-around time based on device speed and PHY interface. */
|
|
gusbcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GUSBCFG);
|
|
|
|
/* Full or High speed */
|
|
if ( USB_OTG_GetDeviceSpeed(pdev) == USB_SPEED_HIGH)
|
|
{
|
|
pdev->cfg.speed = USB_OTG_SPEED_HIGH;
|
|
pdev->cfg.mps = USB_OTG_HS_MAX_PACKET_SIZE ;
|
|
gusbcfg.b.usbtrdtim = 9;
|
|
}
|
|
else
|
|
{
|
|
pdev->cfg.speed = USB_OTG_SPEED_FULL;
|
|
pdev->cfg.mps = USB_OTG_FS_MAX_PACKET_SIZE ;
|
|
gusbcfg.b.usbtrdtim = 5;
|
|
}
|
|
|
|
USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GUSBCFG, gusbcfg.d32);
|
|
|
|
/* Clear interrupt */
|
|
gintsts.d32 = 0;
|
|
gintsts.b.enumdone = 1;
|
|
USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GINTSTS, gintsts.d32 );
|
|
return 1;
|
|
}
|
|
|
|
|
|
/**
|
|
* @brief DCD_IsoINIncomplete_ISR
|
|
* handle the ISO IN incomplete interrupt
|
|
* @param pdev: device instance
|
|
* @retval status
|
|
*/
|
|
static uint32_t DCD_IsoINIncomplete_ISR(USB_OTG_CORE_HANDLE *pdev)
|
|
{
|
|
USB_OTG_GINTSTS_TypeDef gintsts;
|
|
|
|
gintsts.d32 = 0;
|
|
|
|
USBD_DCD_INT_fops->IsoINIncomplete (pdev);
|
|
|
|
/* Clear interrupt */
|
|
gintsts.b.incomplisoin = 1;
|
|
USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTSTS, gintsts.d32);
|
|
|
|
return 1;
|
|
}
|
|
|
|
/**
|
|
* @brief DCD_IsoOUTIncomplete_ISR
|
|
* handle the ISO OUT incomplete interrupt
|
|
* @param pdev: device instance
|
|
* @retval status
|
|
*/
|
|
static uint32_t DCD_IsoOUTIncomplete_ISR(USB_OTG_CORE_HANDLE *pdev)
|
|
{
|
|
USB_OTG_GINTSTS_TypeDef gintsts;
|
|
|
|
gintsts.d32 = 0;
|
|
|
|
USBD_DCD_INT_fops->IsoOUTIncomplete (pdev);
|
|
|
|
/* Clear interrupt */
|
|
gintsts.b.incomplisoout = 1;
|
|
USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTSTS, gintsts.d32);
|
|
return 1;
|
|
}
|
|
/**
|
|
* @brief DCD_ReadDevInEP
|
|
* Reads ep flags
|
|
* @param pdev: device instance
|
|
* @retval status
|
|
*/
|
|
static uint32_t DCD_ReadDevInEP (USB_OTG_CORE_HANDLE *pdev, uint8_t epnum)
|
|
{
|
|
uint32_t v, msk, emp;
|
|
msk = USB_OTG_READ_REG32(&pdev->regs.DREGS->DIEPMSK);
|
|
emp = USB_OTG_READ_REG32(&pdev->regs.DREGS->DIEPEMPMSK);
|
|
msk |= ((emp >> epnum) & 0x1) << 7;
|
|
v = USB_OTG_READ_REG32(&pdev->regs.INEP_REGS[epnum]->DIEPINT) & msk;
|
|
return v;
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|