f4942db044
These files come from STM32Cube_FW_L4_V1.3.0, with Windows line endings converted to unix. Only basic HAL files are added. In addition the QSPI support is included to support later external QSPI flash as mass storage.
805 lines
35 KiB
C
805 lines
35 KiB
C
/**
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******************************************************************************
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* @file stm32l4xx_ll_sdmmc.h
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* @author MCD Application Team
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* @version V1.3.0
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* @date 29-January-2016
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* @brief Header file of low layer SDMMC HAL module.
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of STMicroelectronics nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __STM32L4xx_LL_SDMMC_H
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#define __STM32L4xx_LL_SDMMC_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "stm32l4xx_hal_def.h"
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/** @addtogroup STM32L4xx_Driver
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* @{
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*/
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/** @addtogroup SDMMC_LL
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* @{
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*/
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/* Exported types ------------------------------------------------------------*/
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/** @defgroup SDMMC_LL_Exported_Types SDMMC_LL Exported Types
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* @{
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*/
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/**
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* @brief SDMMC Configuration Structure definition
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*/
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typedef struct
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{
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uint32_t ClockEdge; /*!< Specifies the clock transition on which the bit capture is made.
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This parameter can be a value of @ref SDMMC_LL_Clock_Edge */
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uint32_t ClockBypass; /*!< Specifies whether the SDMMC Clock divider bypass is
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enabled or disabled.
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This parameter can be a value of @ref SDMMC_LL_Clock_Bypass */
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uint32_t ClockPowerSave; /*!< Specifies whether SDMMC Clock output is enabled or
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disabled when the bus is idle.
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This parameter can be a value of @ref SDMMC_LL_Clock_Power_Save */
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uint32_t BusWide; /*!< Specifies the SDMMC bus width.
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This parameter can be a value of @ref SDMMC_LL_Bus_Wide */
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uint32_t HardwareFlowControl; /*!< Specifies whether the SDMMC hardware flow control is enabled or disabled.
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This parameter can be a value of @ref SDMMC_LL_Hardware_Flow_Control */
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uint32_t ClockDiv; /*!< Specifies the clock frequency of the SDMMC controller.
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This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
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}SDMMC_InitTypeDef;
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/**
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* @brief SDMMC Command Control structure
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*/
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typedef struct
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{
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uint32_t Argument; /*!< Specifies the SDMMC command argument which is sent
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to a card as part of a command message. If a command
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contains an argument, it must be loaded into this register
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before writing the command to the command register. */
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uint32_t CmdIndex; /*!< Specifies the SDMMC command index. It must be Min_Data = 0 and
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Max_Data = 64 */
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uint32_t Response; /*!< Specifies the SDMMC response type.
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This parameter can be a value of @ref SDMMC_LL_Response_Type */
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uint32_t WaitForInterrupt; /*!< Specifies whether SDMMC wait for interrupt request is
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enabled or disabled.
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This parameter can be a value of @ref SDMMC_LL_Wait_Interrupt_State */
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uint32_t CPSM; /*!< Specifies whether SDMMC Command path state machine (CPSM)
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is enabled or disabled.
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This parameter can be a value of @ref SDMMC_LL_CPSM_State */
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}SDMMC_CmdInitTypeDef;
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/**
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* @brief SDMMC Data Control structure
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*/
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typedef struct
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{
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uint32_t DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */
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uint32_t DataLength; /*!< Specifies the number of data bytes to be transferred. */
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uint32_t DataBlockSize; /*!< Specifies the data block size for block transfer.
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This parameter can be a value of @ref SDMMC_LL_Data_Block_Size */
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uint32_t TransferDir; /*!< Specifies the data transfer direction, whether the transfer
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is a read or write.
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This parameter can be a value of @ref SDMMC_LL_Transfer_Direction */
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uint32_t TransferMode; /*!< Specifies whether data transfer is in stream or block mode.
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This parameter can be a value of @ref SDMMC_LL_Transfer_Type */
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uint32_t DPSM; /*!< Specifies whether SDMMC Data path state machine (DPSM)
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is enabled or disabled.
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This parameter can be a value of @ref SDMMC_LL_DPSM_State */
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}SDMMC_DataInitTypeDef;
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/**
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* @}
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*/
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/* Exported constants --------------------------------------------------------*/
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/** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants
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* @{
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*/
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/** @defgroup SDMMC_LL_Clock_Edge Clock Edge
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* @{
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*/
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#define SDMMC_CLOCK_EDGE_RISING ((uint32_t)0x00000000)
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#define SDMMC_CLOCK_EDGE_FALLING SDMMC_CLKCR_NEGEDGE
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#define IS_SDMMC_CLOCK_EDGE(EDGE) (((EDGE) == SDMMC_CLOCK_EDGE_RISING) || \
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((EDGE) == SDMMC_CLOCK_EDGE_FALLING))
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/**
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* @}
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*/
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/** @defgroup SDMMC_LL_Clock_Bypass Clock Bypass
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* @{
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*/
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#define SDMMC_CLOCK_BYPASS_DISABLE ((uint32_t)0x00000000)
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#define SDMMC_CLOCK_BYPASS_ENABLE SDMMC_CLKCR_BYPASS
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#define IS_SDMMC_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDMMC_CLOCK_BYPASS_DISABLE) || \
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((BYPASS) == SDMMC_CLOCK_BYPASS_ENABLE))
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/**
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* @}
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*/
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/** @defgroup SDMMC_LL_Clock_Power_Save Clock Power Saving
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* @{
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*/
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#define SDMMC_CLOCK_POWER_SAVE_DISABLE ((uint32_t)0x00000000)
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#define SDMMC_CLOCK_POWER_SAVE_ENABLE SDMMC_CLKCR_PWRSAV
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#define IS_SDMMC_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDMMC_CLOCK_POWER_SAVE_DISABLE) || \
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((SAVE) == SDMMC_CLOCK_POWER_SAVE_ENABLE))
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/**
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* @}
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*/
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/** @defgroup SDMMC_LL_Bus_Wide Bus Width
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* @{
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*/
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#define SDMMC_BUS_WIDE_1B ((uint32_t)0x00000000)
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#define SDMMC_BUS_WIDE_4B SDMMC_CLKCR_WIDBUS_0
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#define SDMMC_BUS_WIDE_8B SDMMC_CLKCR_WIDBUS_1
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#define IS_SDMMC_BUS_WIDE(WIDE) (((WIDE) == SDMMC_BUS_WIDE_1B) || \
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((WIDE) == SDMMC_BUS_WIDE_4B) || \
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((WIDE) == SDMMC_BUS_WIDE_8B))
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/**
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* @}
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*/
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/** @defgroup SDMMC_LL_Hardware_Flow_Control Hardware Flow Control
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* @{
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*/
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#define SDMMC_HARDWARE_FLOW_CONTROL_DISABLE ((uint32_t)0x00000000)
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#define SDMMC_HARDWARE_FLOW_CONTROL_ENABLE SDMMC_CLKCR_HWFC_EN
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#define IS_SDMMC_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_DISABLE) || \
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((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_ENABLE))
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/**
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* @}
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*/
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/** @defgroup SDMMC_LL_Clock_Division Clock Division
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* @{
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*/
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#define IS_SDMMC_CLKDIV(DIV) ((DIV) <= 0xFF)
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/**
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* @}
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*/
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/** @defgroup SDMMC_LL_Command_Index Command Index
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* @{
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*/
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#define IS_SDMMC_CMD_INDEX(INDEX) ((INDEX) < 0x40)
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/**
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* @}
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*/
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/** @defgroup SDMMC_LL_Response_Type Response Type
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* @{
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*/
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#define SDMMC_RESPONSE_NO ((uint32_t)0x00000000)
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#define SDMMC_RESPONSE_SHORT SDMMC_CMD_WAITRESP_0
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#define SDMMC_RESPONSE_LONG SDMMC_CMD_WAITRESP
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#define IS_SDMMC_RESPONSE(RESPONSE) (((RESPONSE) == SDMMC_RESPONSE_NO) || \
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((RESPONSE) == SDMMC_RESPONSE_SHORT) || \
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((RESPONSE) == SDMMC_RESPONSE_LONG))
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/**
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* @}
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*/
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/** @defgroup SDMMC_LL_Wait_Interrupt_State Wait Interrupt
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* @{
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*/
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#define SDMMC_WAIT_NO ((uint32_t)0x00000000)
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#define SDMMC_WAIT_IT SDMMC_CMD_WAITINT
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#define SDMMC_WAIT_PEND SDMMC_CMD_WAITPEND
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#define IS_SDMMC_WAIT(WAIT) (((WAIT) == SDMMC_WAIT_NO) || \
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((WAIT) == SDMMC_WAIT_IT) || \
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((WAIT) == SDMMC_WAIT_PEND))
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/**
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* @}
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*/
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/** @defgroup SDMMC_LL_CPSM_State CPSM State
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* @{
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*/
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#define SDMMC_CPSM_DISABLE ((uint32_t)0x00000000)
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#define SDMMC_CPSM_ENABLE SDMMC_CMD_CPSMEN
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#define IS_SDMMC_CPSM(CPSM) (((CPSM) == SDMMC_CPSM_DISABLE) || \
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((CPSM) == SDMMC_CPSM_ENABLE))
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/**
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* @}
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*/
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/** @defgroup SDMMC_LL_Response_Registers Response Register
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* @{
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*/
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#define SDMMC_RESP1 ((uint32_t)0x00000000)
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#define SDMMC_RESP2 ((uint32_t)0x00000004)
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#define SDMMC_RESP3 ((uint32_t)0x00000008)
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#define SDMMC_RESP4 ((uint32_t)0x0000000C)
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#define IS_SDMMC_RESP(RESP) (((RESP) == SDMMC_RESP1) || \
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((RESP) == SDMMC_RESP2) || \
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((RESP) == SDMMC_RESP3) || \
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((RESP) == SDMMC_RESP4))
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/**
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* @}
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*/
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/** @defgroup SDMMC_LL_Data_Length Data Lenght
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* @{
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*/
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#define IS_SDMMC_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF)
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/**
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* @}
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*/
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/** @defgroup SDMMC_LL_Data_Block_Size Data Block Size
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* @{
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*/
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#define SDMMC_DATABLOCK_SIZE_1B ((uint32_t)0x00000000)
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#define SDMMC_DATABLOCK_SIZE_2B SDMMC_DCTRL_DBLOCKSIZE_0
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#define SDMMC_DATABLOCK_SIZE_4B SDMMC_DCTRL_DBLOCKSIZE_1
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#define SDMMC_DATABLOCK_SIZE_8B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1)
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#define SDMMC_DATABLOCK_SIZE_16B SDMMC_DCTRL_DBLOCKSIZE_2
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#define SDMMC_DATABLOCK_SIZE_32B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_2)
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#define SDMMC_DATABLOCK_SIZE_64B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2)
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#define SDMMC_DATABLOCK_SIZE_128B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2)
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#define SDMMC_DATABLOCK_SIZE_256B SDMMC_DCTRL_DBLOCKSIZE_3
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#define SDMMC_DATABLOCK_SIZE_512B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_3)
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#define SDMMC_DATABLOCK_SIZE_1024B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_3)
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#define SDMMC_DATABLOCK_SIZE_2048B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_3)
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#define SDMMC_DATABLOCK_SIZE_4096B (SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3)
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#define SDMMC_DATABLOCK_SIZE_8192B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3)
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#define SDMMC_DATABLOCK_SIZE_16384B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3)
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#define IS_SDMMC_BLOCK_SIZE(SIZE) (((SIZE) == SDMMC_DATABLOCK_SIZE_1B) || \
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((SIZE) == SDMMC_DATABLOCK_SIZE_2B) || \
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((SIZE) == SDMMC_DATABLOCK_SIZE_4B) || \
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((SIZE) == SDMMC_DATABLOCK_SIZE_8B) || \
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((SIZE) == SDMMC_DATABLOCK_SIZE_16B) || \
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((SIZE) == SDMMC_DATABLOCK_SIZE_32B) || \
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((SIZE) == SDMMC_DATABLOCK_SIZE_64B) || \
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((SIZE) == SDMMC_DATABLOCK_SIZE_128B) || \
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((SIZE) == SDMMC_DATABLOCK_SIZE_256B) || \
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((SIZE) == SDMMC_DATABLOCK_SIZE_512B) || \
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((SIZE) == SDMMC_DATABLOCK_SIZE_1024B) || \
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((SIZE) == SDMMC_DATABLOCK_SIZE_2048B) || \
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((SIZE) == SDMMC_DATABLOCK_SIZE_4096B) || \
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((SIZE) == SDMMC_DATABLOCK_SIZE_8192B) || \
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((SIZE) == SDMMC_DATABLOCK_SIZE_16384B))
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/**
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* @}
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*/
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/** @defgroup SDMMC_LL_Transfer_Direction Transfer Direction
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* @{
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*/
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#define SDMMC_TRANSFER_DIR_TO_CARD ((uint32_t)0x00000000)
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#define SDMMC_TRANSFER_DIR_TO_SDMMC SDMMC_DCTRL_DTDIR
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#define IS_SDMMC_TRANSFER_DIR(DIR) (((DIR) == SDMMC_TRANSFER_DIR_TO_CARD) || \
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((DIR) == SDMMC_TRANSFER_DIR_TO_SDMMC))
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/**
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* @}
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*/
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/** @defgroup SDMMC_LL_Transfer_Type Transfer Type
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* @{
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*/
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#define SDMMC_TRANSFER_MODE_BLOCK ((uint32_t)0x00000000)
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#define SDMMC_TRANSFER_MODE_STREAM SDMMC_DCTRL_DTMODE
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#define IS_SDMMC_TRANSFER_MODE(MODE) (((MODE) == SDMMC_TRANSFER_MODE_BLOCK) || \
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((MODE) == SDMMC_TRANSFER_MODE_STREAM))
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/**
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* @}
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*/
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/** @defgroup SDMMC_LL_DPSM_State DPSM State
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* @{
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*/
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#define SDMMC_DPSM_DISABLE ((uint32_t)0x00000000)
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#define SDMMC_DPSM_ENABLE SDMMC_DCTRL_DTEN
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#define IS_SDMMC_DPSM(DPSM) (((DPSM) == SDMMC_DPSM_DISABLE) ||\
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((DPSM) == SDMMC_DPSM_ENABLE))
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/**
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* @}
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*/
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/** @defgroup SDMMC_LL_Read_Wait_Mode Read Wait Mode
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* @{
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*/
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#define SDMMC_READ_WAIT_MODE_DATA2 ((uint32_t)0x00000000)
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#define SDMMC_READ_WAIT_MODE_CLK (SDMMC_DCTRL_RWMOD)
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#define IS_SDMMC_READWAIT_MODE(MODE) (((MODE) == SDMMC_READ_WAIT_MODE_CLK) || \
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((MODE) == SDMMC_READ_WAIT_MODE_DATA2))
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/**
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* @}
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*/
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/** @defgroup SDMMC_LL_Interrupt_sources Interrupt Sources
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* @{
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*/
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#define SDMMC_IT_CCRCFAIL SDMMC_STA_CCRCFAIL
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#define SDMMC_IT_DCRCFAIL SDMMC_STA_DCRCFAIL
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#define SDMMC_IT_CTIMEOUT SDMMC_STA_CTIMEOUT
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#define SDMMC_IT_DTIMEOUT SDMMC_STA_DTIMEOUT
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#define SDMMC_IT_TXUNDERR SDMMC_STA_TXUNDERR
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#define SDMMC_IT_RXOVERR SDMMC_STA_RXOVERR
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#define SDMMC_IT_CMDREND SDMMC_STA_CMDREND
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#define SDMMC_IT_CMDSENT SDMMC_STA_CMDSENT
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#define SDMMC_IT_DATAEND SDMMC_STA_DATAEND
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#define SDMMC_IT_DBCKEND SDMMC_STA_DBCKEND
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#define SDMMC_IT_CMDACT SDMMC_STA_CMDACT
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#define SDMMC_IT_TXACT SDMMC_STA_TXACT
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#define SDMMC_IT_RXACT SDMMC_STA_RXACT
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#define SDMMC_IT_TXFIFOHE SDMMC_STA_TXFIFOHE
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#define SDMMC_IT_RXFIFOHF SDMMC_STA_RXFIFOHF
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#define SDMMC_IT_TXFIFOF SDMMC_STA_TXFIFOF
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#define SDMMC_IT_RXFIFOF SDMMC_STA_RXFIFOF
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#define SDMMC_IT_TXFIFOE SDMMC_STA_TXFIFOE
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#define SDMMC_IT_RXFIFOE SDMMC_STA_RXFIFOE
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#define SDMMC_IT_TXDAVL SDMMC_STA_TXDAVL
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#define SDMMC_IT_RXDAVL SDMMC_STA_RXDAVL
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#define SDMMC_IT_SDIOIT SDMMC_STA_SDIOIT
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/**
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* @}
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*/
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/** @defgroup SDMMC_LL_Flags Flags
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* @{
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*/
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#define SDMMC_FLAG_CCRCFAIL SDMMC_STA_CCRCFAIL
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#define SDMMC_FLAG_DCRCFAIL SDMMC_STA_DCRCFAIL
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#define SDMMC_FLAG_CTIMEOUT SDMMC_STA_CTIMEOUT
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#define SDMMC_FLAG_DTIMEOUT SDMMC_STA_DTIMEOUT
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#define SDMMC_FLAG_TXUNDERR SDMMC_STA_TXUNDERR
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#define SDMMC_FLAG_RXOVERR SDMMC_STA_RXOVERR
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#define SDMMC_FLAG_CMDREND SDMMC_STA_CMDREND
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#define SDMMC_FLAG_CMDSENT SDMMC_STA_CMDSENT
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#define SDMMC_FLAG_DATAEND SDMMC_STA_DATAEND
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#define SDMMC_FLAG_DBCKEND SDMMC_STA_DBCKEND
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#define SDMMC_FLAG_CMDACT SDMMC_STA_CMDACT
|
|
#define SDMMC_FLAG_TXACT SDMMC_STA_TXACT
|
|
#define SDMMC_FLAG_RXACT SDMMC_STA_RXACT
|
|
#define SDMMC_FLAG_TXFIFOHE SDMMC_STA_TXFIFOHE
|
|
#define SDMMC_FLAG_RXFIFOHF SDMMC_STA_RXFIFOHF
|
|
#define SDMMC_FLAG_TXFIFOF SDMMC_STA_TXFIFOF
|
|
#define SDMMC_FLAG_RXFIFOF SDMMC_STA_RXFIFOF
|
|
#define SDMMC_FLAG_TXFIFOE SDMMC_STA_TXFIFOE
|
|
#define SDMMC_FLAG_RXFIFOE SDMMC_STA_RXFIFOE
|
|
#define SDMMC_FLAG_TXDAVL SDMMC_STA_TXDAVL
|
|
#define SDMMC_FLAG_RXDAVL SDMMC_STA_RXDAVL
|
|
#define SDMMC_FLAG_SDIOIT SDMMC_STA_SDIOIT
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/* Exported macro ------------------------------------------------------------*/
|
|
/** @defgroup SDMMC_LL_Exported_macros SDMMC_LL Exported Macros
|
|
* @{
|
|
*/
|
|
|
|
/** @defgroup SDMMC_LL_Register Bits And Addresses Definitions
|
|
* @brief SDMMC_LL registers bit address in the alias region
|
|
* @{
|
|
*/
|
|
/* ---------------------- SDMMC registers bit mask --------------------------- */
|
|
/* --- CLKCR Register ---*/
|
|
/* CLKCR register clear mask */
|
|
#define CLKCR_CLEAR_MASK ((uint32_t)(SDMMC_CLKCR_CLKDIV | SDMMC_CLKCR_PWRSAV |\
|
|
SDMMC_CLKCR_BYPASS | SDMMC_CLKCR_WIDBUS |\
|
|
SDMMC_CLKCR_NEGEDGE | SDMMC_CLKCR_HWFC_EN))
|
|
|
|
/* --- DCTRL Register ---*/
|
|
/* SDMMC DCTRL Clear Mask */
|
|
#define DCTRL_CLEAR_MASK ((uint32_t)(SDMMC_DCTRL_DTEN | SDMMC_DCTRL_DTDIR |\
|
|
SDMMC_DCTRL_DTMODE | SDMMC_DCTRL_DBLOCKSIZE))
|
|
|
|
/* --- CMD Register ---*/
|
|
/* CMD Register clear mask */
|
|
#define CMD_CLEAR_MASK ((uint32_t)(SDMMC_CMD_CMDINDEX | SDMMC_CMD_WAITRESP |\
|
|
SDMMC_CMD_WAITINT | SDMMC_CMD_WAITPEND |\
|
|
SDMMC_CMD_CPSMEN | SDMMC_CMD_SDIOSUSPEND))
|
|
|
|
/* SDMMC Intialization Frequency (400KHz max) */
|
|
#define SDMMC_INIT_CLK_DIV ((uint8_t)0x76)
|
|
|
|
/* SDMMC Data Transfer Frequency (25MHz max) */
|
|
#define SDMMC_TRANSFER_CLK_DIV ((uint8_t)0x0)
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup SDMMC_LL_Interrupt_Clock Interrupt And Clock Configuration
|
|
* @brief macros to handle interrupts and specific clock configurations
|
|
* @{
|
|
*/
|
|
|
|
/**
|
|
* @brief Enable the SDMMC device.
|
|
* @param __INSTANCE__: SDMMC Instance
|
|
* @retval None
|
|
*/
|
|
#define __SDMMC_ENABLE(__INSTANCE__) ((__INSTANCE__)->CLKCR |= SDMMC_CLKCR_CLKEN)
|
|
|
|
/**
|
|
* @brief Disable the SDMMC device.
|
|
* @param __INSTANCE__: SDMMC Instance
|
|
* @retval None
|
|
*/
|
|
#define __SDMMC_DISABLE(__INSTANCE__) ((__INSTANCE__)->CLKCR &= ~SDMMC_CLKCR_CLKEN)
|
|
|
|
/**
|
|
* @brief Enable the SDMMC DMA transfer.
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
#define __SDMMC_DMA_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_DMAEN)
|
|
/**
|
|
* @brief Disable the SDMMC DMA transfer.
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
#define __SDMMC_DMA_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_DMAEN)
|
|
|
|
/**
|
|
* @brief Enable the SDMMC device interrupt.
|
|
* @param __INSTANCE__: Pointer to SDMMC register base
|
|
* @param __INTERRUPT__: specifies the SDMMC interrupt sources to be enabled.
|
|
* This parameter can be one or a combination of the following values:
|
|
* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
|
|
* @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
|
|
* @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
|
|
* @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
|
|
* @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
|
|
* @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
|
|
* @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
|
|
* @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
|
|
* @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
|
|
* @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
|
|
* @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt
|
|
* @arg SDMMC_IT_TXACT: Data transmit in progress interrupt
|
|
* @arg SDMMC_IT_RXACT: Data receive in progress interrupt
|
|
* @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
|
|
* @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
|
|
* @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt
|
|
* @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
|
|
* @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
|
|
* @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt
|
|
* @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt
|
|
* @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt
|
|
* @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
|
|
* @retval None
|
|
*/
|
|
#define __SDMMC_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK |= (__INTERRUPT__))
|
|
|
|
/**
|
|
* @brief Disable the SDMMC device interrupt.
|
|
* @param __INSTANCE__: Pointer to SDMMC register base
|
|
* @param __INTERRUPT__: specifies the SDMMC interrupt sources to be disabled.
|
|
* This parameter can be one or a combination of the following values:
|
|
* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
|
|
* @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
|
|
* @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
|
|
* @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
|
|
* @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
|
|
* @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
|
|
* @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
|
|
* @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
|
|
* @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
|
|
* @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
|
|
* @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt
|
|
* @arg SDMMC_IT_TXACT: Data transmit in progress interrupt
|
|
* @arg SDMMC_IT_RXACT: Data receive in progress interrupt
|
|
* @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
|
|
* @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
|
|
* @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt
|
|
* @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
|
|
* @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
|
|
* @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt
|
|
* @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt
|
|
* @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt
|
|
* @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
|
|
* @retval None
|
|
*/
|
|
#define __SDMMC_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK &= ~(__INTERRUPT__))
|
|
|
|
/**
|
|
* @brief Checks whether the specified SDMMC flag is set or not.
|
|
* @param __INSTANCE__: Pointer to SDMMC register base
|
|
* @param __FLAG__: specifies the flag to check.
|
|
* This parameter can be one of the following values:
|
|
* @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
|
|
* @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
|
|
* @arg SDMMC_FLAG_CTIMEOUT: Command response timeout
|
|
* @arg SDMMC_FLAG_DTIMEOUT: Data timeout
|
|
* @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error
|
|
* @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error
|
|
* @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed)
|
|
* @arg SDMMC_FLAG_CMDSENT: Command sent (no response required)
|
|
* @arg SDMMC_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
|
|
* @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed)
|
|
* @arg SDMMC_FLAG_CMDACT: Command transfer in progress
|
|
* @arg SDMMC_FLAG_TXACT: Data transmit in progress
|
|
* @arg SDMMC_FLAG_RXACT: Data receive in progress
|
|
* @arg SDMMC_FLAG_TXFIFOHE: Transmit FIFO Half Empty
|
|
* @arg SDMMC_FLAG_RXFIFOHF: Receive FIFO Half Full
|
|
* @arg SDMMC_FLAG_TXFIFOF: Transmit FIFO full
|
|
* @arg SDMMC_FLAG_RXFIFOF: Receive FIFO full
|
|
* @arg SDMMC_FLAG_TXFIFOE: Transmit FIFO empty
|
|
* @arg SDMMC_FLAG_RXFIFOE: Receive FIFO empty
|
|
* @arg SDMMC_FLAG_TXDAVL: Data available in transmit FIFO
|
|
* @arg SDMMC_FLAG_RXDAVL: Data available in receive FIFO
|
|
* @arg SDMMC_FLAG_SDMMCIT: SD I/O interrupt received
|
|
* @retval The new state of SDMMC_FLAG (SET or RESET).
|
|
*/
|
|
#define __SDMMC_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != RESET)
|
|
|
|
|
|
/**
|
|
* @brief Clears the SDMMC pending flags.
|
|
* @param __INSTANCE__: Pointer to SDMMC register base
|
|
* @param __FLAG__: specifies the flag to clear.
|
|
* This parameter can be one or a combination of the following values:
|
|
* @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
|
|
* @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
|
|
* @arg SDMMC_FLAG_CTIMEOUT: Command response timeout
|
|
* @arg SDMMC_FLAG_DTIMEOUT: Data timeout
|
|
* @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error
|
|
* @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error
|
|
* @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed)
|
|
* @arg SDMMC_FLAG_CMDSENT: Command sent (no response required)
|
|
* @arg SDMMC_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
|
|
* @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed)
|
|
* @arg SDMMC_FLAG_SDMMCIT: SD I/O interrupt received
|
|
* @retval None
|
|
*/
|
|
#define __SDMMC_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->ICR = (__FLAG__))
|
|
|
|
/**
|
|
* @brief Checks whether the specified SDMMC interrupt has occurred or not.
|
|
* @param __INSTANCE__: Pointer to SDMMC register base
|
|
* @param __INTERRUPT__: specifies the SDMMC interrupt source to check.
|
|
* This parameter can be one of the following values:
|
|
* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
|
|
* @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
|
|
* @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
|
|
* @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
|
|
* @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
|
|
* @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
|
|
* @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
|
|
* @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
|
|
* @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
|
|
* @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
|
|
* @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt
|
|
* @arg SDMMC_IT_TXACT: Data transmit in progress interrupt
|
|
* @arg SDMMC_IT_RXACT: Data receive in progress interrupt
|
|
* @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
|
|
* @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
|
|
* @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt
|
|
* @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
|
|
* @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
|
|
* @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt
|
|
* @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt
|
|
* @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt
|
|
* @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
|
|
* @retval The new state of SDMMC_IT (SET or RESET).
|
|
*/
|
|
#define __SDMMC_GET_IT(__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__))
|
|
|
|
/**
|
|
* @brief Clears the SDMMC's interrupt pending bits.
|
|
* @param __INSTANCE__: Pointer to SDMMC register base
|
|
* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
|
|
* This parameter can be one or a combination of the following values:
|
|
* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
|
|
* @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
|
|
* @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
|
|
* @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
|
|
* @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
|
|
* @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
|
|
* @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
|
|
* @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
|
|
* @arg SDMMC_IT_DATAEND: Data end (data counter, SDMMC_DCOUNT, is zero) interrupt
|
|
* @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
|
|
* @retval None
|
|
*/
|
|
#define __SDMMC_CLEAR_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->ICR = (__INTERRUPT__))
|
|
|
|
/**
|
|
* @brief Enable Start the SD I/O Read Wait operation.
|
|
* @param __INSTANCE__: Pointer to SDMMC register base
|
|
* @retval None
|
|
*/
|
|
#define __SDMMC_START_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_RWSTART)
|
|
|
|
/**
|
|
* @brief Disable Start the SD I/O Read Wait operations.
|
|
* @param __INSTANCE__: Pointer to SDMMC register base
|
|
* @retval None
|
|
*/
|
|
#define __SDMMC_START_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTART)
|
|
|
|
/**
|
|
* @brief Enable Start the SD I/O Read Wait operation.
|
|
* @param __INSTANCE__: Pointer to SDMMC register base
|
|
* @retval None
|
|
*/
|
|
#define __SDMMC_STOP_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_RWSTOP)
|
|
|
|
/**
|
|
* @brief Disable Stop the SD I/O Read Wait operations.
|
|
* @param __INSTANCE__: Pointer to SDMMC register base
|
|
* @retval None
|
|
*/
|
|
#define __SDMMC_STOP_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTOP)
|
|
|
|
/**
|
|
* @brief Enable the SD I/O Mode Operation.
|
|
* @param __INSTANCE__: Pointer to SDMMC register base
|
|
* @retval None
|
|
*/
|
|
#define __SDMMC_OPERATION_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_SDIOEN)
|
|
|
|
/**
|
|
* @brief Disable the SD I/O Mode Operation.
|
|
* @param __INSTANCE__: Pointer to SDMMC register base
|
|
* @retval None
|
|
*/
|
|
#define __SDMMC_OPERATION_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_SDIOEN)
|
|
|
|
/**
|
|
* @brief Enable the SD I/O Suspend command sending.
|
|
* @param __INSTANCE__: Pointer to SDMMC register base
|
|
* @retval None
|
|
*/
|
|
#define __SDMMC_SUSPEND_CMD_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD |= SDMMC_CMD_SDIOSUSPEND)
|
|
|
|
/**
|
|
* @brief Disable the SD I/O Suspend command sending.
|
|
* @param __INSTANCE__: Pointer to SDMMC register base
|
|
* @retval None
|
|
*/
|
|
#define __SDMMC_SUSPEND_CMD_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDMMC_CMD_SDIOSUSPEND)
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/* Exported functions --------------------------------------------------------*/
|
|
/** @addtogroup SDMMC_LL_Exported_Functions
|
|
* @{
|
|
*/
|
|
|
|
/* Initialization/de-initialization functions **********************************/
|
|
/** @addtogroup HAL_SDMMC_LL_Group1
|
|
* @{
|
|
*/
|
|
HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init);
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/* I/O operation functions *****************************************************/
|
|
/** @addtogroup HAL_SDMMC_LL_Group2
|
|
* @{
|
|
*/
|
|
/* Blocking mode: Polling */
|
|
uint32_t SDMMC_ReadFIFO(SDMMC_TypeDef *SDMMCx);
|
|
HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef *SDMMCx, uint32_t *pWriteData);
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/* Peripheral Control functions ************************************************/
|
|
/** @addtogroup HAL_SDMMC_LL_Group3
|
|
* @{
|
|
*/
|
|
HAL_StatusTypeDef SDMMC_PowerState_ON(SDMMC_TypeDef *SDMMCx);
|
|
HAL_StatusTypeDef SDMMC_PowerState_OFF(SDMMC_TypeDef *SDMMCx);
|
|
uint32_t SDMMC_GetPowerState(SDMMC_TypeDef *SDMMCx);
|
|
|
|
/* Command path state machine (CPSM) management functions */
|
|
HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, SDMMC_CmdInitTypeDef *Command);
|
|
uint8_t SDMMC_GetCommandResponse(SDMMC_TypeDef *SDMMCx);
|
|
uint32_t SDMMC_GetResponse(SDMMC_TypeDef *SDMMCx, uint32_t Response);
|
|
|
|
/* Data path state machine (DPSM) management functions */
|
|
HAL_StatusTypeDef SDMMC_DataConfig(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef* Data);
|
|
uint32_t SDMMC_GetDataCounter(SDMMC_TypeDef *SDMMCx);
|
|
uint32_t SDMMC_GetFIFOCount(SDMMC_TypeDef *SDMMCx);
|
|
|
|
/* SDMMC Cards mode management functions */
|
|
HAL_StatusTypeDef SDMMC_SetSDMMCReadWaitMode(SDMMC_TypeDef *SDMMCx, uint32_t SDMMC_ReadWaitMode);
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif /* __STM32L4xx_LL_SDMMC_H */
|
|
|
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|