268 lines
10 KiB
C
268 lines
10 KiB
C
/*
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* This file is part of the MicroPython project, http://micropython.org/
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2013-2018 Damien P. George
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include <stdint.h>
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#include <string.h>
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#include "py/obj.h"
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#include "py/mperrno.h"
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#include "led.h"
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#include "flash.h"
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#include "storage.h"
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#if MICROPY_HW_ENABLE_INTERNAL_FLASH_STORAGE
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// Here we try to automatically configure the location and size of the flash
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// pages to use for the internal storage. We also configure the location of the
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// cache used for writing.
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#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)
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#define CACHE_MEM_START_ADDR (0x10000000) // CCM data RAM, 64k
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#define FLASH_SECTOR_SIZE_MAX (0x10000) // 64k max, size of CCM
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#define FLASH_MEM_SEG1_START_ADDR (0x08004000) // sector 1
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#define FLASH_MEM_SEG1_NUM_BLOCKS (224) // sectors 1,2,3,4: 16k+16k+16k+64k=112k
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// enable this to get an extra 64k of storage (uses the last sector of the flash)
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#if 0
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#define FLASH_MEM_SEG2_START_ADDR (0x080e0000) // sector 11
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#define FLASH_MEM_SEG2_NUM_BLOCKS (128) // sector 11: 128k
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#endif
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#elif defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx)
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STATIC byte flash_cache_mem[0x4000] __attribute__((aligned(4))); // 16k
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#define CACHE_MEM_START_ADDR (&flash_cache_mem[0])
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#define FLASH_SECTOR_SIZE_MAX (0x4000) // 16k max due to size of cache buffer
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#define FLASH_MEM_SEG1_START_ADDR (0x08004000) // sector 1
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#define FLASH_MEM_SEG1_NUM_BLOCKS (128) // sectors 1,2,3,4: 16k+16k+16k+16k(of 64k)=64k
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#elif defined(STM32F429xx)
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#define CACHE_MEM_START_ADDR (0x10000000) // CCM data RAM, 64k
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#define FLASH_SECTOR_SIZE_MAX (0x10000) // 64k max, size of CCM
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#define FLASH_MEM_SEG1_START_ADDR (0x08004000) // sector 1
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#define FLASH_MEM_SEG1_NUM_BLOCKS (224) // sectors 1,2,3,4: 16k+16k+16k+64k=112k
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#elif defined(STM32F439xx)
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#define CACHE_MEM_START_ADDR (0x10000000) // CCM data RAM, 64k
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#define FLASH_SECTOR_SIZE_MAX (0x10000) // 64k max, size of CCM
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#define FLASH_MEM_SEG1_START_ADDR (0x08100000) // sector 12
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#define FLASH_MEM_SEG1_NUM_BLOCKS (384) // sectors 12,13,14,15,16,17: 16k+16k+16k+16k+64k+64k(of 128k)=192k
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#define FLASH_MEM_SEG2_START_ADDR (0x08140000) // sector 18
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#define FLASH_MEM_SEG2_NUM_BLOCKS (128) // sector 18: 64k(of 128k)
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#elif defined(STM32F746xx) || defined(STM32F767xx) || defined(STM32F769xx)
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// The STM32F746 doesn't really have CCRAM, so we use the 64K DTCM for this.
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#define CACHE_MEM_START_ADDR (0x20000000) // DTCM data RAM, 64k
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#define FLASH_SECTOR_SIZE_MAX (0x08000) // 32k max
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#define FLASH_MEM_SEG1_START_ADDR (0x08008000) // sector 1
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#define FLASH_MEM_SEG1_NUM_BLOCKS (192) // sectors 1,2,3: 32k+32k+32=96k
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#elif defined(STM32H743xx)
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// The STM32H743 flash sectors are 128K
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#define CACHE_MEM_START_ADDR (0x20000000) // DTCM data RAM, 128k
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#define FLASH_SECTOR_SIZE_MAX (0x20000) // 128k max
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#define FLASH_MEM_SEG1_START_ADDR (0x08020000) // sector 1
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#define FLASH_MEM_SEG1_NUM_BLOCKS (256) // Sector 1: 128k / 512b = 256 blocks
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#elif defined(STM32L475xx) || defined(STM32L476xx)
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extern uint8_t _flash_fs_start;
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extern uint8_t _flash_fs_end;
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// The STM32L475/6 doesn't have CCRAM, so we use the 32K SRAM2 for this.
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#define CACHE_MEM_START_ADDR (0x10000000) // SRAM2 data RAM, 32k
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#define FLASH_SECTOR_SIZE_MAX (0x00800) // 2k max
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#define FLASH_MEM_SEG1_START_ADDR ((long)&_flash_fs_start)
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#define FLASH_MEM_SEG1_NUM_BLOCKS ((&_flash_fs_end - &_flash_fs_start) / 512)
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#else
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#error "no internal flash storage support for this MCU"
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#endif
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#if !defined(FLASH_MEM_SEG2_START_ADDR)
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#define FLASH_MEM_SEG2_START_ADDR (0) // no second segment
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#define FLASH_MEM_SEG2_NUM_BLOCKS (0) // no second segment
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#endif
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#define FLASH_FLAG_DIRTY (1)
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#define FLASH_FLAG_FORCE_WRITE (2)
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#define FLASH_FLAG_ERASED (4)
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static __IO uint8_t flash_flags = 0;
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static uint32_t flash_cache_sector_id;
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static uint32_t flash_cache_sector_start;
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static uint32_t flash_cache_sector_size;
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static uint32_t flash_tick_counter_last_write;
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static void flash_bdev_irq_handler(void);
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int32_t flash_bdev_ioctl(uint32_t op, uint32_t arg) {
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(void)arg;
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switch (op) {
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case BDEV_IOCTL_INIT:
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flash_flags = 0;
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flash_cache_sector_id = 0;
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flash_tick_counter_last_write = 0;
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return 0;
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case BDEV_IOCTL_NUM_BLOCKS:
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return FLASH_MEM_SEG1_NUM_BLOCKS + FLASH_MEM_SEG2_NUM_BLOCKS;
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case BDEV_IOCTL_IRQ_HANDLER:
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flash_bdev_irq_handler();
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return 0;
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case BDEV_IOCTL_SYNC:
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if (flash_flags & FLASH_FLAG_DIRTY) {
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flash_flags |= FLASH_FLAG_FORCE_WRITE;
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while (flash_flags & FLASH_FLAG_DIRTY) {
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NVIC->STIR = FLASH_IRQn;
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}
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}
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return 0;
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}
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return -MP_EINVAL;
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}
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static uint8_t *flash_cache_get_addr_for_write(uint32_t flash_addr) {
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uint32_t flash_sector_start;
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uint32_t flash_sector_size;
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uint32_t flash_sector_id = flash_get_sector_info(flash_addr, &flash_sector_start, &flash_sector_size);
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if (flash_sector_size > FLASH_SECTOR_SIZE_MAX) {
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flash_sector_size = FLASH_SECTOR_SIZE_MAX;
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}
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if (flash_cache_sector_id != flash_sector_id) {
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flash_bdev_ioctl(BDEV_IOCTL_SYNC, 0);
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memcpy((void*)CACHE_MEM_START_ADDR, (const void*)flash_sector_start, flash_sector_size);
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flash_cache_sector_id = flash_sector_id;
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flash_cache_sector_start = flash_sector_start;
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flash_cache_sector_size = flash_sector_size;
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}
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flash_flags |= FLASH_FLAG_DIRTY;
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led_state(PYB_LED_RED, 1); // indicate a dirty cache with LED on
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flash_tick_counter_last_write = HAL_GetTick();
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return (uint8_t*)CACHE_MEM_START_ADDR + flash_addr - flash_sector_start;
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}
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static uint8_t *flash_cache_get_addr_for_read(uint32_t flash_addr) {
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uint32_t flash_sector_start;
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uint32_t flash_sector_size;
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uint32_t flash_sector_id = flash_get_sector_info(flash_addr, &flash_sector_start, &flash_sector_size);
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if (flash_cache_sector_id == flash_sector_id) {
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// in cache, copy from there
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return (uint8_t*)CACHE_MEM_START_ADDR + flash_addr - flash_sector_start;
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}
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// not in cache, copy straight from flash
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return (uint8_t*)flash_addr;
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}
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static uint32_t convert_block_to_flash_addr(uint32_t block) {
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if (block < FLASH_MEM_SEG1_NUM_BLOCKS) {
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return FLASH_MEM_SEG1_START_ADDR + block * FLASH_BLOCK_SIZE;
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}
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if (block < FLASH_MEM_SEG1_NUM_BLOCKS + FLASH_MEM_SEG2_NUM_BLOCKS) {
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return FLASH_MEM_SEG2_START_ADDR + (block - FLASH_MEM_SEG1_NUM_BLOCKS) * FLASH_BLOCK_SIZE;
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}
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// can add more flash segments here if needed, following above pattern
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// bad block
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return -1;
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}
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static void flash_bdev_irq_handler(void) {
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if (!(flash_flags & FLASH_FLAG_DIRTY)) {
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return;
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}
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// This code uses interrupts to erase the flash
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/*
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if (flash_erase_state == 0) {
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flash_erase_it(flash_cache_sector_start, (const uint32_t*)CACHE_MEM_START_ADDR, flash_cache_sector_size / 4);
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flash_erase_state = 1;
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return;
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}
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if (flash_erase_state == 1) {
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// wait for erase
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// TODO add timeout
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#define flash_erase_done() (__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) == RESET)
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if (!flash_erase_done()) {
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return;
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}
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flash_erase_state = 2;
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}
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*/
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// This code erases the flash directly, waiting for it to finish
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if (!(flash_flags & FLASH_FLAG_ERASED)) {
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flash_erase(flash_cache_sector_start, (const uint32_t*)CACHE_MEM_START_ADDR, flash_cache_sector_size / 4);
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flash_flags |= FLASH_FLAG_ERASED;
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return;
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}
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// If not a forced write, wait at least 5 seconds after last write to flush
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// On file close and flash unmount we get a forced write, so we can afford to wait a while
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if ((flash_flags & FLASH_FLAG_FORCE_WRITE) || HAL_GetTick() - flash_tick_counter_last_write >= 5000) {
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// sync the cache RAM buffer by writing it to the flash page
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flash_write(flash_cache_sector_start, (const uint32_t*)CACHE_MEM_START_ADDR, flash_cache_sector_size / 4);
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// clear the flash flags now that we have a clean cache
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flash_flags = 0;
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// indicate a clean cache with LED off
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led_state(PYB_LED_RED, 0);
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}
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}
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bool flash_bdev_readblock(uint8_t *dest, uint32_t block) {
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// non-MBR block, get data from flash memory, possibly via cache
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uint32_t flash_addr = convert_block_to_flash_addr(block);
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if (flash_addr == -1) {
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// bad block number
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return false;
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}
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uint8_t *src = flash_cache_get_addr_for_read(flash_addr);
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memcpy(dest, src, FLASH_BLOCK_SIZE);
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return true;
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}
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bool flash_bdev_writeblock(const uint8_t *src, uint32_t block) {
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// non-MBR block, copy to cache
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uint32_t flash_addr = convert_block_to_flash_addr(block);
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if (flash_addr == -1) {
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// bad block number
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return false;
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}
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uint8_t *dest = flash_cache_get_addr_for_write(flash_addr);
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memcpy(dest, src, FLASH_BLOCK_SIZE);
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return true;
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}
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#endif // MICROPY_HW_ENABLE_INTERNAL_FLASH_STORAGE
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