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circuitpython/ports
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Damien George a542c6d7e0 stm32/powerctrl: For F7, allow PLLM!=HSE when setting PLLSAI to 48MHz. 
PLLM is shared among all PLL blocks on F7 MCUs, and this calculation to
configure PLLSAI to have 48MHz on the P output previously assumed that PLLM
is equal to HSE (eg PLLM=25 for HSE=25MHz).  This commit relaxes this
assumption to allow other values of PLLM.
2020-01-29 16:49:13 +11:00
..
bare-arm
ports: Allow overriding CROSS_COMPILE in a custom makefile.
2019-12-27 23:53:16 +11:00
cc3200
extmod/vfs: Rename BP_IOCTL_xxx constants to MP_BLOCKDEV_IOCTL_xxx.
2019-10-29 14:17:29 +11:00
esp32
esp32/modnetwork: Add max_clients kw-arg to WLAN.config for AP setting.
2020-01-22 16:43:25 +11:00
esp8266
esp8266/modules: Fix AttributeError in _boot.py if flash not formatted.
2020-01-14 23:53:49 +11:00
javascript
py: Automatically provide weak links from "foo" to "ufoo" module name.
2019-10-22 15:30:52 +11:00
minimal
ports: Allow overriding CROSS_COMPILE in a custom makefile.
2019-12-27 23:53:16 +11:00
nrf
ports: Modify mp_hal_pin_write macro so it can be used as a function.
2020-01-14 23:48:42 +11:00
pic16bit
ports: Allow overriding CROSS_COMPILE in a custom makefile.
2019-12-27 23:53:16 +11:00
powerpc
ports: Allow overriding CROSS_COMPILE in a custom makefile.
2019-12-27 23:53:16 +11:00
qemu-arm
qemu-arm/Makefile: Allow overriding CROSS_COMPILE from another makefile.
2019-12-19 17:59:32 +11:00
samd
ports: Add new make target "submodules" which inits required modules.
2019-10-15 17:14:41 +11:00
stm32
stm32/powerctrl: For F7, allow PLLM!=HSE when setting PLLSAI to 48MHz.
2020-01-29 16:49:13 +11:00
teensy
ports: Modify mp_hal_pin_write macro so it can be used as a function.
2020-01-14 23:48:42 +11:00
unix
unix/unix_mphal: Add compile check for incompatible GIL+ASYNC_KBD_INTR.
2020-01-26 23:31:27 +11:00
windows
windows/windows_mphal: Release GIL during system calls.
2020-01-26 23:27:40 +11:00
zephyr
zephyr/main: Use mp_stack API instead of local pointer for stack top.
2019-10-29 23:05:07 +11:00