5e990cc27f
The RT1176 has two cores, but the actual firmware supports only the CM7. There are currently no good plans on how to use the CM4. The actual MIMXRT1170_EVK board is on par with the existing MIMXRT boards, with the following extensions: - Use 64 MB RAM for the heap. - Support both LAN interfaces as LAN(0) and LAN(1), with LAN(1) being the 1GB interface. The dual LAN port interface can eventually be adapted as well for the RT1062 MCU. This work was done in collaboration with @alphaFred.
272 lines
12 KiB
C
272 lines
12 KiB
C
/*
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* This file is part of the MicroPython project, http://micropython.org/
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2021 Philipp Ebensberger
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#if MICROPY_HW_SDRAM_AVAIL
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#include "modmachine.h"
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#include "fsl_semc.h"
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#include "fsl_iomuxc.h"
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#include "fsl_clock.h"
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// Linker symbols
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extern uint8_t __sdram_start;
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#if defined(MIMXRT117x_SERIES)
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// Pull Up, High drive strength
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#define SDRAM_PIN_CONFIG (0x07UL)
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#else
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// Pull up 22K, high slew rate
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#define SDRAM_PIN_CONFIG (0xE1UL)
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#endif
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void mimxrt_sdram_init(void) {
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#if !defined(MIMXRT117x_SERIES)
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// Set Clocks
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CLOCK_InitSysPfd(kCLOCK_Pfd2, 29); // '29' PLL2 PFD2 frequency = 528MHz * 18 / 29 = 327.72MHz (with 528MHz = PLL2 frequency)
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CLOCK_SetMux(kCLOCK_SemcAltMux, 0); // '0' PLL2 PFD2 will be selected as alternative clock for SEMC root clock
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CLOCK_SetMux(kCLOCK_SemcMux, 1); // '1' SEMC alternative clock will be used as SEMC clock root
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CLOCK_SetDiv(kCLOCK_SemcDiv, 1); // '1' divide by 2 -> SEMC clock = 163.86 MHz
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#endif
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// Set Pins
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// Data Pins 0..15
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IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA00, 0UL);
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IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA00, SDRAM_PIN_CONFIG);
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IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA01, 0UL);
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IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA01, SDRAM_PIN_CONFIG);
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IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA02, 0UL);
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IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA02, SDRAM_PIN_CONFIG);
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IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA03, 0UL);
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IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA03, SDRAM_PIN_CONFIG);
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IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA04, 0UL);
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IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA04, SDRAM_PIN_CONFIG);
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IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA05, 0UL);
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IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA05, SDRAM_PIN_CONFIG);
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IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA06, 0UL);
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IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA06, SDRAM_PIN_CONFIG);
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IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA07, 0UL);
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IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA07, SDRAM_PIN_CONFIG);
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IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA08, 0UL);
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IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA08, SDRAM_PIN_CONFIG);
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IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA09, 0UL);
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IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA09, SDRAM_PIN_CONFIG);
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IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA10, 0UL);
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IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA10, SDRAM_PIN_CONFIG);
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IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA11, 0UL);
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IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA11, SDRAM_PIN_CONFIG);
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IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA12, 0UL);
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IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA12, SDRAM_PIN_CONFIG);
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IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA13, 0UL);
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IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA13, SDRAM_PIN_CONFIG);
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IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA14, 0UL);
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IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA14, SDRAM_PIN_CONFIG);
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IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA15, 0UL);
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IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA15, SDRAM_PIN_CONFIG);
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// Address Pins
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IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_ADDR00, 0UL);
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IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_ADDR00, SDRAM_PIN_CONFIG);
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IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_ADDR01, 0UL);
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IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_ADDR01, SDRAM_PIN_CONFIG);
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IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_ADDR02, 0UL);
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IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_ADDR02, SDRAM_PIN_CONFIG);
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IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_ADDR03, 0UL);
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IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_ADDR03, SDRAM_PIN_CONFIG);
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IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_ADDR04, 0UL);
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IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_ADDR04, SDRAM_PIN_CONFIG);
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IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_ADDR05, 0UL);
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IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_ADDR05, SDRAM_PIN_CONFIG);
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IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_ADDR06, 0UL);
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IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_ADDR06, SDRAM_PIN_CONFIG);
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IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_ADDR07, 0UL);
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IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_ADDR07, SDRAM_PIN_CONFIG);
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IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_ADDR08, 0UL);
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IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_ADDR08, SDRAM_PIN_CONFIG);
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IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_ADDR09, 0UL);
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IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_ADDR09, SDRAM_PIN_CONFIG);
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IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_ADDR10, 0UL);
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IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_ADDR10, SDRAM_PIN_CONFIG);
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IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_ADDR11, 0UL);
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IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_ADDR11, SDRAM_PIN_CONFIG);
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IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_ADDR12, 0UL);
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IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_ADDR12, SDRAM_PIN_CONFIG);
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IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DM00, 0UL);
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IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DM00, SDRAM_PIN_CONFIG);
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IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_BA0, 0UL);
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IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_BA0, SDRAM_PIN_CONFIG);
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IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_BA1, 0UL);
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IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_BA1, SDRAM_PIN_CONFIG);
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IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_CAS, 0UL);
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IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_CAS, SDRAM_PIN_CONFIG);
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IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_RAS, 0UL);
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IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_RAS, SDRAM_PIN_CONFIG);
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IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_CLK, 0UL);
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IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_CLK, SDRAM_PIN_CONFIG);
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IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_CKE, 0UL);
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IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_CKE, SDRAM_PIN_CONFIG);
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IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_WE, 0UL);
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IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_WE, SDRAM_PIN_CONFIG);
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IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DM01, 0UL);
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IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DM01, SDRAM_PIN_CONFIG);
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IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DQS, 1UL);
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IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DQS, SDRAM_PIN_CONFIG);
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#if defined(MIMXRT117x_SERIES)
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// Data Pins 16..31
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IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA16, 0UL);
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IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA16, SDRAM_PIN_CONFIG);
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IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA17, 0UL);
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IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA17, SDRAM_PIN_CONFIG);
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IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA18, 0UL);
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IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA18, SDRAM_PIN_CONFIG);
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IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA19, 0UL);
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IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA19, SDRAM_PIN_CONFIG);
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IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA20, 0UL);
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IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA20, SDRAM_PIN_CONFIG);
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IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA21, 0UL);
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IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA21, SDRAM_PIN_CONFIG);
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IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA22, 0UL);
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IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA22, SDRAM_PIN_CONFIG);
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IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA23, 0UL);
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IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA23, SDRAM_PIN_CONFIG);
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IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA24, 0UL);
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IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA24, SDRAM_PIN_CONFIG);
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IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA25, 0UL);
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IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA25, SDRAM_PIN_CONFIG);
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IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA26, 0UL);
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IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA26, SDRAM_PIN_CONFIG);
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IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA27, 0UL);
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IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA27, SDRAM_PIN_CONFIG);
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IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA28, 0UL);
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IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA28, SDRAM_PIN_CONFIG);
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IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA29, 0UL);
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IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA29, SDRAM_PIN_CONFIG);
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IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA30, 0UL);
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IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA30, SDRAM_PIN_CONFIG);
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IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA31, 0UL);
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IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA31, SDRAM_PIN_CONFIG);
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IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DM02, 0UL);
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IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DM02, SDRAM_PIN_CONFIG);
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IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DM03, 0UL);
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IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DM03, SDRAM_PIN_CONFIG);
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#endif
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// Chip Select Pins
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#ifndef MIMXRT_IOMUXC_SEMC_CS0
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#error No SEMC CS0 defined!
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#endif
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IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_CS0, 0UL);
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IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_CS0, SDRAM_PIN_CONFIG);
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#ifdef MIMXRT_IOMUXC_SEMC_CS1
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IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_CS1, 0UL);
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IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_CS1, SDRAM_PIN_CONFIG);
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#endif
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#ifdef MIMXRT_IOMUXC_SEMC_CS2
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IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_CS2, 0UL);
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IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_CS2, SDRAM_PIN_CONFIG);
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#endif
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#ifdef MIMXRT_IOMUXC_SEMC_CS3
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IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_CS3, 0UL);
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IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_CS3, SDRAM_PIN_CONFIG);
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#endif
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// Configure SEMC
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semc_config_t semc_cfg;
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SEMC_GetDefaultConfig(&semc_cfg);
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semc_cfg.dqsMode = kSEMC_Loopbackdqspad; // For more accurate timing.
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SEMC_Init(SEMC, &semc_cfg);
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#if defined(MIMXRT117x_SERIES)
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uint32_t clock_freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Semc);
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semc_sdram_config_t sdram_cfg = {
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.csxPinMux = kSEMC_MUXCSX0,
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.address = 0x80000000,
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.memsize_kbytes = (MICROPY_HW_SDRAM_SIZE >> 10),
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.portSize = kSEMC_PortSize32Bit, // two 16-bit SDRAMs make up 32-bit portsize
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.burstLen = kSEMC_Sdram_BurstLen8,
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.columnAddrBitNum = kSEMC_SdramColunm_9bit,
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.casLatency = kSEMC_LatencyThree,
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.tPrecharge2Act_Ns = 15, // tRP 15ns
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.tAct2ReadWrite_Ns = 15, // tRCD 15ns
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.tRefreshRecovery_Ns = 70, // Use the maximum of the (Trfc , Txsr).
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.tWriteRecovery_Ns = 2, // tWR 2ns
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.tCkeOff_Ns = 42, // The minimum cycle of SDRAM CLK off state. CKE is off in self refresh at a minimum period tRAS.
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.tAct2Prechage_Ns = 40, // tRAS 40ns
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.tSelfRefRecovery_Ns = 70,
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.tRefresh2Refresh_Ns = 60,
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.tAct2Act_Ns = 2, // tRC/tRDD 2ns
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.tPrescalePeriod_Ns = 160 * (1000000000 / clock_freq),
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.refreshPeriod_nsPerRow = 64 * 1000000 / 8192, // 64ms/8192
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.refreshUrgThreshold = sdram_cfg.refreshPeriod_nsPerRow,
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.refreshBurstLen = 1,
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.delayChain = 2,
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};
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#else
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uint32_t clock_freq = CLOCK_GetFreq(kCLOCK_SemcClk);
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semc_sdram_config_t sdram_cfg = {
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.csxPinMux = kSEMC_MUXCSX0,
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.address = ((uint32_t)&__sdram_start),
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.memsize_kbytes = (MICROPY_HW_SDRAM_SIZE >> 10), // Right shift by 10 == division by 1024
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.portSize = kSEMC_PortSize16Bit,
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.burstLen = kSEMC_Sdram_BurstLen1,
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.columnAddrBitNum = kSEMC_SdramColunm_9bit,
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.casLatency = kSEMC_LatencyThree,
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.tPrecharge2Act_Ns = 18, // Trp 18ns
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.tAct2ReadWrite_Ns = 18, // Trcd 18ns
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.tRefreshRecovery_Ns = (60 + 67),
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.tWriteRecovery_Ns = 12, // 12ns
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.tCkeOff_Ns = 42, // The minimum cycle of SDRAM CLK off state. CKE is off in self refresh at a minimum period tRAS.
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.tAct2Prechage_Ns = 42, // Tras 42ns
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.tSelfRefRecovery_Ns = 67,
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.tRefresh2Refresh_Ns = 60,
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.tAct2Act_Ns = 60,
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.tPrescalePeriod_Ns = 160 * (1000000000 / clock_freq),
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.tIdleTimeout_Ns = 0UL,
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.refreshPeriod_nsPerRow = 64 * 1000000 / 8192, // 64ms/8192
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.refreshUrgThreshold = 64 * 1000000 / 8192, // 64ms/8192
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.refreshBurstLen = 1
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};
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#endif
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(status_t)SEMC_ConfigureSDRAM(SEMC, kSEMC_SDRAM_CS0, &sdram_cfg, clock_freq);
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}
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#endif
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