28642ab10d
This evolves the API from 2.x (and breaks it). Playback devices are now separate from the samples themselves. This allows for greater playback flexibility. Two sample sources are audioio.RawSample and audioio.WaveFile. They can both be mono or stereo. They can be output to audioio.AudioOut or audiobusio.I2SOut. Internally, the dma tracking has changed from a TC counting block transfers to an interrupt generated by the block event sent to the EVSYS. This reduces the overhead of each DMA transfer so multiple can occure without using up TCs. Fixes #652. Fixes #522. Huge progress on #263
302 lines
7.8 KiB
C
302 lines
7.8 KiB
C
/*
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* This file is part of the MicroPython project, http://micropython.org/
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2017 Scott Shawcroft for Adafruit Industries
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include <stdbool.h>
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#include <stdint.h>
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#include "timers.h"
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#include "common-hal/pulseio/PulseOut.h"
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#ifdef SAMD21
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#include "hpl/gclk/hpl_gclk_base.h"
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#endif
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#ifdef SAMD51
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#include "hri/hri_gclk_d51.h"
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#endif
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const uint16_t prescaler[8] = {1, 2, 4, 8, 16, 64, 256, 1024};
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// This bitmask keeps track of which channels of a TCC are currently claimed.
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#ifdef SAMD21
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const uint8_t tcc_cc_num[3] = {4, 2, 2};
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const uint8_t tc_gclk_ids[TC_INST_NUM] = {TC3_GCLK_ID,
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TC4_GCLK_ID,
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TC5_GCLK_ID,
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#ifdef TC6_GCLK_ID
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TC6_GCLK_ID,
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#endif
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#ifdef TC7_GCLK_ID
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TC7_GCLK_ID,
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#endif
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};
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const uint8_t tcc_gclk_ids[3] = {TCC0_GCLK_ID, TCC1_GCLK_ID, TCC2_GCLK_ID};
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#endif
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#ifdef SAMD51
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const uint8_t tcc_cc_num[5] = {6, 4, 3, 2, 2};
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const uint8_t tc_gclk_ids[TC_INST_NUM] = {TC0_GCLK_ID,
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TC1_GCLK_ID,
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TC2_GCLK_ID,
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TC3_GCLK_ID,
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#ifdef TC4_GCLK_ID
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TC4_GCLK_ID,
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#endif
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#ifdef TC5_GCLK_ID
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TC5_GCLK_ID,
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#endif
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#ifdef TC6_GCLK_ID
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TC6_GCLK_ID,
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#endif
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#ifdef TC7_GCLK_ID
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TC7_GCLK_ID,
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#endif
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};
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const uint8_t tcc_gclk_ids[TCC_INST_NUM] = {TCC0_GCLK_ID,
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TCC1_GCLK_ID,
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TCC2_GCLK_ID,
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#ifdef TCC3_GCLK_ID
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TCC3_GCLK_ID,
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#endif
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#ifdef TCC4_GCLK_ID
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TCC4_GCLK_ID
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#endif
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};
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#endif
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Tc* const tc_insts[TC_INST_NUM] = TC_INSTS;
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Tcc* const tcc_insts[TCC_INST_NUM] = TCC_INSTS;
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IRQn_Type const tc_irq[TC_INST_NUM] = {
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#ifdef TC0
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TC0_IRQn,
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#endif
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#ifdef TC1
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TC1_IRQn,
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#endif
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#ifdef TC2
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TC2_IRQn,
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#endif
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#ifdef TC3
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TC3_IRQn,
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#endif
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#ifdef TC4
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TC4_IRQn,
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#endif
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#ifdef TC5
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TC5_IRQn,
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#endif
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#ifdef TC6
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TC6_IRQn,
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#endif
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#ifdef TC7
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TC7_IRQn,
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#endif
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};
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void turn_on_clocks(bool is_tc, uint8_t index, uint32_t gclk_index) {
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uint8_t gclk_id;
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if (is_tc) {
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gclk_id = tc_gclk_ids[index];
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} else {
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gclk_id = tcc_gclk_ids[index];
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}
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// Turn on the clocks for the peripherals.
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#ifdef SAMD51
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if (is_tc) {
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switch (index) {
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case 0:
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MCLK->APBAMASK.reg |= MCLK_APBAMASK_TC0;
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break;
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case 1:
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MCLK->APBAMASK.reg |= MCLK_APBAMASK_TC1;
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break;
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case 2:
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MCLK->APBBMASK.reg |= MCLK_APBBMASK_TC2;
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break;
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case 3:
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MCLK->APBBMASK.reg |= MCLK_APBBMASK_TC3;
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break;
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case 4:
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MCLK->APBCMASK.reg |= MCLK_APBCMASK_TC4;
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break;
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case 5:
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MCLK->APBCMASK.reg |= MCLK_APBCMASK_TC5;
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break;
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case 6:
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MCLK->APBDMASK.reg |= MCLK_APBDMASK_TC6;
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break;
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case 7:
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MCLK->APBDMASK.reg |= MCLK_APBDMASK_TC7;
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break;
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default:
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break;
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}
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} else {
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switch (index) {
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case 0:
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MCLK->APBBMASK.reg |= MCLK_APBBMASK_TCC0;
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break;
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case 1:
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MCLK->APBBMASK.reg |= MCLK_APBBMASK_TCC1;
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break;
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case 2:
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MCLK->APBCMASK.reg |= MCLK_APBCMASK_TCC2;
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break;
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case 3:
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MCLK->APBCMASK.reg |= MCLK_APBCMASK_TCC3;
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break;
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case 4:
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MCLK->APBDMASK.reg |= MCLK_APBDMASK_TCC4;
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break;
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default:
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break;
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}
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}
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// FIXME(tannewt): TC4-TC7 can only have 100mhz inputs.
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hri_gclk_write_PCHCTRL_reg(GCLK, gclk_id,
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gclk_index | (1 << GCLK_PCHCTRL_CHEN_Pos));
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#endif
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#ifdef SAMD21
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// Determine the clock slot on the APBC bus. TCC0 is the first and 8 slots in.
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uint8_t clock_slot = 8 + index;
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// We index TCs starting at zero but in memory they begin at three so we have to add three.
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if (is_tc) {
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clock_slot += 3;
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}
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PM->APBCMASK.reg |= 1 << clock_slot;
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_gclk_enable_channel(gclk_id, gclk_index);
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#endif
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}
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void tc_set_enable(Tc* tc, bool enable) {
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tc->COUNT16.CTRLA.bit.ENABLE = enable;
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#ifdef SAMD21
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while (tc->COUNT16.STATUS.bit.SYNCBUSY != 0) {
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/* Wait for sync */
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}
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#endif
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#ifdef SAMD51
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while (tc->COUNT16.SYNCBUSY.bit.ENABLE != 0) {
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/* Wait for sync */
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}
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#endif
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}
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void tc_enable_interrupts(uint8_t tc_index) {
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NVIC_DisableIRQ(tc_irq[tc_index]);
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NVIC_ClearPendingIRQ(tc_irq[tc_index]);
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NVIC_EnableIRQ(tc_irq[tc_index]);
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}
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void tc_disable_interrupts(uint8_t tc_index) {
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NVIC_DisableIRQ(tc_irq[tc_index]);
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NVIC_ClearPendingIRQ(tc_irq[tc_index]);
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}
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void tcc_set_enable(Tcc* tcc, bool enable) {
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tcc->CTRLA.bit.ENABLE = enable;
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while (tcc->SYNCBUSY.bit.ENABLE != 0) {
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/* Wait for sync */
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}
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}
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void tc_wait_for_sync(Tc* tc) {
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#ifdef SAMD21
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while (tc->COUNT16.STATUS.bit.SYNCBUSY != 0) {}
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#endif
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#ifdef SAMD51
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while (tc->COUNT16.SYNCBUSY.reg != 0) {}
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#endif
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}
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void tc_reset(Tc* tc) {
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tc->COUNT16.CTRLA.bit.SWRST = 1;
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while (tc->COUNT16.CTRLA.bit.SWRST == 1) {
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}
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}
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void shared_timer_handler(bool is_tc, uint8_t index) {
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// Add calls to interrupt handlers for specific functionality here.
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if (is_tc) {
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pulseout_interrupt_handler(index);
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}
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}
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#ifdef SAMD51
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#define TC_OFFSET 0
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#endif
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#ifdef SAMD21
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#define TC_OFFSET 3
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#endif
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void TCC0_Handler(void) {
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shared_timer_handler(false, 0);
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}
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void TCC1_Handler(void) {
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shared_timer_handler(false, 1);
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}
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void TCC2_Handler(void) {
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shared_timer_handler(false, 2);
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}
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// TC0 - TC2 only exist on the SAMD51
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#ifdef TC0
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void TC0_Handler(void) {
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shared_timer_handler(true, 0);
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}
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#endif
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#ifdef TC1
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void TC1_Handler(void) {
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shared_timer_handler(true, 1);
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}
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#endif
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#ifdef TC2
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void TC2_Handler(void) {
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shared_timer_handler(true, 2);
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}
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#endif
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void TC3_Handler(void) {
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shared_timer_handler(true, 3 - TC_OFFSET);
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}
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void TC4_Handler(void) {
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shared_timer_handler(true, 4 - TC_OFFSET);
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}
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void TC5_Handler(void) {
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shared_timer_handler(true, 5 - TC_OFFSET);
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}
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#ifdef TC6
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void TC6_Handler(void) {
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shared_timer_handler(true, 6 - TC_OFFSET);
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}
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#endif
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#ifdef TC7
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void TC7_Handler(void) {
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shared_timer_handler(true, 7 - TC_OFFSET);
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}
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#endif
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