4e25a4f6b3
Doing a squash merge to avoid having the `slc_cli_linux` .zip files in the history. They were added in one commit and removed and replaced with a submodule in another. * Initial commit for xg24 * Fix SLC issue * Fix SLC extract fail * Change board's name * Correct spelling of code Build immediately after slc generate * Remove VID and PID * Change creator and creation id * Apply new creator_id and creation_id * Update makefile, error message, mcu_processor function * Update mpconfigboard.mk * Update Board extensions, PORT_DEPS * Update makefile * Add exclude_patterns * Show java, jinja2 version * Show path for debugging CI * Add requirements-dev for slc * Add PATH slc_cli * Update background function * Add jinja2 PATH * Show PATH * Update jinja2 path * Update jinja2 path * Update jinja2 path * Update jinja2 path * Change slc folder * Change markupsafe folder * Add symbolic link for slc * Update makefile * Update makefile * Update MX25R3235F.toml from submodule nvm.toml * alphabetize the list * Remove slc_cli_linux folder * Update slc_cli submodule --------- Co-authored-by: Chat Nguyen <cvnguyen@silabs.com> Co-authored-by: silabs-ChatNguyen <chat.nguyen@silabs.com> Co-authored-by: silabs-ChatNguyen <126220343+silabs-ChatNguyen@users.noreply.github.com>
29 lines
631 B
ArmAsm
29 lines
631 B
ArmAsm
.syntax unified
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.cpu cortex-m33
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.thumb
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.text
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.align 2
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@ uint cpu_get_regs_and_sp(r0=uint regs[10])
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.global cpu_get_regs_and_sp
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.thumb
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.thumb_func
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.type cpu_get_regs_and_sp, %function
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cpu_get_regs_and_sp:
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@ store registers into given array
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str r4, [r0], #4
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str r5, [r0], #4
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str r6, [r0], #4
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str r7, [r0], #4
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str r8, [r0], #4
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str r9, [r0], #4
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str r10, [r0], #4
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str r11, [r0], #4
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str r12, [r0], #4
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str r13, [r0], #4
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@ return the sp
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@Move stack pointer to return register
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mov r0, sp
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@Branch to link register (return address) and change instruction set if needed
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bx lr
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