651 lines
20 KiB
C
651 lines
20 KiB
C
/**
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* \file
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*
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* \brief Direct Memory Access Controller Driver for SAMB
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*
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* Copyright (C) 2015-2016 Atmel Corporation. All rights reserved.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. The name of Atmel may not be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* 4. This software may only be redistributed and used in connection with an
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* Atmel microcontroller product.
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*
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* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* \asf_license_stop
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*
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*/
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/*
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* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
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*/
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#ifndef DMA_H_INCLUDED
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#define DMA_H_INCLUDED
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* \defgroup asfdoc_samb_dma_group SAM Direct Memory Access Controller Driver (DMAC)
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*
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* This driver for Atmel® | SMART SAM devices provides an interface for the configuration
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* and management of the Direct Memory Access Controller(DMAC) module within
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* the device. The DMAC can transfer data between memories and peripherals, and
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* thus off-load these tasks from the CPU. The module supports peripheral to
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* peripheral, peripheral to memory, memory to peripheral, and memory to memory
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* transfers.
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*
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* The following peripherals are used by the DMAC Driver:
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* - DMAC (Direct Memory Access Controller)
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*
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* The following devices can use this module:
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* - Atmel | SMART SAM B11
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*
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* The outline of this documentation is as follows:
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* - \ref asfdoc_samb_dma_prerequisites
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* - \ref asfdoc_samb_dma_module_overview
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* - \ref asfdoc_samb_dma_special_considerations
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* - \ref asfdoc_samb_dma_extra_info
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* - \ref asfdoc_samb_dma_examples
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* - \ref asfdoc_samb_dma_api_overview
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*
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*
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* \section asfdoc_samb_dma_prerequisites Prerequisites
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*
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* There are no prerequisites for this module.
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*
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*
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* \section asfdoc_samb_dma_module_overview Module Overview
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*
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* SAM devices with DMAC enables high data transfer rates with minimum
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* CPU intervention and frees up CPU time. With access to all peripherals,
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* the DMAC can handle automatic transfer of data to/from modules.
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* It supports static and incremental addressing for both source and
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* destination.
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*
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* The DMAC when used with peripheral triggers, provides a
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* considerable advantage by reducing the power consumption and performing
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* data transfer in the background.
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* The CPU can remain in sleep during this time to reduce power consumption.
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*
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* <table>
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* <tr>
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* <th>Device</th>
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* <th>Dma channel number</th>
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* </tr>
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* <tr>
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* <td>SAMB11</td>
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* <td>4</td>
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* </tr>
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* </table>
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* The DMA channel operation can be suspended at any time by software,
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* or after selectable descriptor execution. The DMAC driver for SAM
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* supports four types of transfers such as peripheral to peripheral,
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* peripheral to memory, memory to peripheral, and memory to memory.
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*
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* The basic transfer unit is a beat which is defined as a single bus access.
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* There can be multiple beats in a single block transfer and multiple block
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* transfers in a DMA transaction.
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* DMA transfer is based on descriptors, which holds transfer properties
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* such as the source and destination addresses, transfer counter, and other
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* additional transfer control information.
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* The descriptors can be static or linked. When static, a single block transfer
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* is performed. When linked, a number of transfer descriptors can be used to
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* enable multiple block transfers within a single DMA transaction.
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*
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* The implementation of the DMA driver is based on the idea that DMA channel
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* is a finite resource of entities with the same abilities. A DMA channel resource
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* is able to move a defined set of data from a source address to destination
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* address triggered by a transfer trigger. On the SAM devices there are 12
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* DMA resources available for allocation. Each of these DMA resources can trigger
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* interrupt callback routines.
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* The other main features are:
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*
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* - Selectable transfer trigger source
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* - Software
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* - Peripheral
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* - Tree level channel priority
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* - Normal level
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* - High level
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* - Top level
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* - Optional interrupt generation on transfer complete, channel error
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* - Supports multi-buffer or circular buffer mode by linking multiple descriptors
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* - Beat size configurable as 8-bit, 16-bit, or 32-bit
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*
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* A simplified block diagram of the DMA Resource can be seen in
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* \ref asfdoc_samb_dma_module_block_diagram "the figure below".
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*
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* \anchor asfdoc_samb_dma_module_block_diagram
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* \dot
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* digraph overview {
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* splines = false;
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* rankdir=LR;
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*
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* mux1 [label="Transfer Trigger", shape=box];
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*
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* dma [label="DMA Channel", shape=polygon, sides=6, orientation=60, style=filled, fillcolor=darkolivegreen1, height=1, width=1];
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* descriptor [label="Transfer Descriptor", shape=box, style=filled, fillcolor=lightblue];
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*
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* mux1 -> dma;
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* descriptor -> dma;
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*
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* interrupt [label="Interrupt", shape=box];
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* events [label="Events", shape=box];
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*
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* dma:e -> interrupt:w;
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* dma:e -> events:w;
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*
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* {rank=same; descriptor dma}
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*
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* }
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* \enddot
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*
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* \subsection asfdoc_samb_dma_module_overview_dma_channels DMA Channels
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* The DMAC in each device consists of several DMA channels, which
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* along with the transfer descriptors defines the data transfer properties.
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* - The transfer control descriptor defines the source and destination
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* addresses, source and destination address increment settings, the
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* block transfer count
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* - Dedicated channel registers control the peripheral trigger source,
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* trigger mode settings, and channel priority level settings
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*
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* With a successful DMA resource allocation, a dedicated
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* DMA channel will be assigned. The channel will be occupied until the
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* DMA resource is freed. A DMA resource handle is used to identify the specific
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* DMA resource.
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* When there are multiple channels with active requests, the arbiter prioritizes
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* the channels requesting access to the bus.
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*
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* \subsection asfdoc_samb_dma_module_overview_dma_trigger DMA Triggers
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* DMA transfer can be started only when a DMA transfer request is acknowledged/granted by the arbiter. A
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* transfer request can be triggered from software, peripheral. There
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* are dedicated source trigger selections for each DMA channel usage.
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*
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* \subsection asfdoc_samb_dma_module_overview_dma_transfer_descriptor DMA Transfer Descriptor
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* The transfer descriptor resides in the SRAM and
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* defines these channel properties.
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*
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* <table>
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* <tr>
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* <th>Field name</th>
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* <th>Field width</th>
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* </tr>
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* <tr>
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* <td>Source Address</td>
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* <td>32 bits</td>
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* </tr>
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* <tr>
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* <td>Destination Address</td>
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* <td>32 bits</td>
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* </tr>
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* <tr>
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* <td>Block Transfer Counter</td>
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* <td>32 bits</td>
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* </tr>
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* <tr>
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* <td>Descriptor Next Address</td>
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* <td>30 bits</td>
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* </tr>
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* <tr>
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* <td>Block Transfer Interrupt</td>
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* <td>1 bit</td>
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* </tr>
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* <tr>
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* <td>Block Transfer Stop Control</td>
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* <td>1 bit</td>
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* </tr>
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* </table>
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*
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* Before starting a transfer, at least one descriptor should be configured.
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* After a successful allocation of a DMA channel, the transfer descriptor can
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* be added with a call to \ref dma_add_descriptor(). If there is a transfer
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* descriptor already allocated to the DMA resource, the descriptor will
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* be linked to the next descriptor address.
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*
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* \subsection asfdoc_samb_dma_module_overview_dma_output DMA Interrupts
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* Both an interrupt callback and an peripheral can be triggered by the
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* DMA transfer. Three types of callbacks are supported by the DMA driver:
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* transfer complete, channel suspend, and transfer error. Each of these callback
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* types can be registered and enabled for each channel independently through
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* the DMA driver API.
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*
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*
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* \section asfdoc_samb_dma_special_considerations Special Considerations
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*
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* There are no special considerations for this module.
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*
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*
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* \section asfdoc_samb_dma_extra_info Extra Information
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*
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* For extra information, see \ref asfdoc_samb_dma_extra. This includes:
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* - \ref asfdoc_samb_dma_extra_acronyms
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* - \ref asfdoc_samb_dma_extra_dependencies
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* - \ref asfdoc_samb_dma_extra_errata
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* - \ref asfdoc_samb_dma_extra_history
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*
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*
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* \section asfdoc_samb_dma_examples Examples
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*
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* For a list of examples related to this driver, see
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* \ref asfdoc_samb_dma_exqsg.
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*
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*
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* \section asfdoc_samb_dma_api_overview API Overview
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* @{
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*/
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#include <compiler.h>
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#include <system_sam_b.h>
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#include "conf_dma.h"
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/** DMA IRQn number. */
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#define PROV_DMA_CTRL0_IRQn 15
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/** DMA invalid channel number. */
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#define DMA_INVALID_CHANNEL 0xff
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/** DMA peripheral index */
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enum dma_peripheral_index {
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MEMORY_DMA_PERIPHERAL = 0,
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UART0RX_DMA_PERIPHERAL,
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UART0TX_DMA_PERIPHERAL,
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UART1RX_DMA_PERIPHERAL,
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UART1TX_DMA_PERIPHERAL,
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SPI0RX_DMA_PERIPHERAL,
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SPI0TX_DMA_PERIPHERAL,
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SPI1RX_DMA_PERIPHERAL,
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SPI1TX_DMA_PERIPHERAL,
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I2C0RX_DMA_PERIPHERAL,
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I2C0TX_DMA_PERIPHERAL,
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I2C1RX_DMA_PERIPHERAL,
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I2C1TX_DMA_PERIPHERAL,
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DUALTIMER0_DMA_PERIPHERAL = 15,
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TIMER0_DMA_PERIPHERAL,
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};
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/** DMA channel index */
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enum dma_ch_index {
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/** DMA channel 0 */
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DMA_CHANNEL_0 = 0,
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/** DMA channel 1 */
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DMA_CHANNEL_1,
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/** DMA channel 2 */
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DMA_CHANNEL_2,
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/** DMA channel 3 */
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DMA_CHANNEL_3,
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};
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enum dma_endian_swap {
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/** DMA endian no swap */
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DMA_ENDIAN_NO_SWAP,
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/** DMA endian 16-bit */
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DMA_ENDIAN_SIZE_16,
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/** DMA endian 32-bit */
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DMA_ENDIAN_SIZE_32,
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/** DMA endian 64-bit */
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DMA_ENDIAN_SIZE_64,
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};
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/**
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* Callback types for DMA callback driver.
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*/
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enum dma_callback_type {
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/** Callback for transfer complete */
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DMA_CALLBACK_TRANSFER_DONE,
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/** AHB read slave error */
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DMA_CALLBACK_READ_ERR,
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/** AHB write slave error */
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DMA_CALLBACK_WRITE_ERR,
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/** FIFO has been overflown */
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DMA_CALLBACK_FIFO_OVERFLOW,
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/** FIFO has been underflows */
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DMA_CALLBACK_FIFO_UNDERFLOW,
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/** Read timeout on AHB bus (timeout value fixed at 1024 cycles) */
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DMA_CALLBACK_READ_TIMEOUT,
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/** Write timeout on AHB bus (timeout value fixed at 1024 cycles) */
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DMA_CALLBACK_WRITE_TIMEOUT,
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/** Channel active but did not start a burst for 2048 cycles */
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DMA_CALLBACK_WDT_TRIGGER,
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/** Number of available callbacks */
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DMA_CALLBACK_N,
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};
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/**
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* DMA transfer descriptor configuration. When the source or destination address
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* increment is enabled, the addresses stored into the configuration structure
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* must correspond to the end of the transfer.
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*/
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struct dma_descriptor {
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/** Start address of read buffer */
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uint32_t read_start_addr;
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/** Start address of write buffer */
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uint32_t write_start_addr;
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/** Size (in bytes) of buffer to transfer */
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uint32_t buffer_size;
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union {
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struct {
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/** Active high interrupt enable once buffer has been transferred */
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uint32_t set_interrupt:1;
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/** If set, channel stops when buffer done, otherwise load from cmd_next_addr */
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uint32_t last:1;
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/** Address of next command if cmd_last is not set */
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uint32_t next_addr:30;
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} cmd;
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uint32_t next;
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};
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};
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/** Structure for DMA source/description */
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struct dma_config {
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/** Maximum number of bytes of an AHB read/write burst */
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uint8_t max_burst;
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/** Number of AHB read/write commands to issue before channel is released */
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uint8_t tokens;
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/** If true, the controller will increment the next burst address */
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bool enable_inc_addr;
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/** Index of peripheral to read/write from (0 if memory or no peripheral flow control) */
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enum dma_peripheral_index periph;
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/**
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* Number of cycles to wait for read/write request signal to update
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* after issuing the read/write clear signal
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*/
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uint8_t periph_delay;
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/** Top priority enable */
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bool enable_proi_top;
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/** Top priority channel index */
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uint8_t proi_top_index;
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/** High priority enable */
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bool enable_proi_high;
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/** High priority channel index */
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uint8_t proi_high_index;
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};
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/** Structure for DMA transfer resource */
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struct dma_resource_config {
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struct dma_config src;
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struct dma_config des;
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/** If true, channel will work in joint mode */
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bool enable_joint_mode;
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/** Endian Byte Swapping */
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enum dma_endian_swap swap;
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};
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/** Forward definition of the DMA resource */
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struct dma_resource;
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/** Type definition for a DMA resource callback function */
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typedef void (*dma_callback_t)(struct dma_resource *const resource);
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/** Structure for DMA transfer resource */
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struct dma_resource {
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/** Allocated DMA channel ID */
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uint8_t channel_id;
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/** Array of callback functions for DMA transfer job */
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dma_callback_t callback[DMA_CALLBACK_N];
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/** Bit mask for enabled callbacks */
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uint8_t callback_enable;
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/** Status of the last job */
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volatile enum status_code job_status;
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/** Transferred data size */
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uint32_t transfered_size;
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/** DMA transfer descriptor */
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struct dma_descriptor* descriptor;
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};
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/**
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* \brief Get DMA resource status.
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*
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* \param[in] resource Pointer to the DMA resource
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*
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* \return Status of the DMA resource.
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*/
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static inline enum status_code dma_get_job_status(struct dma_resource *resource)
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{
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return resource->job_status;
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}
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/**
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* \brief Enable a callback function for a dedicated DMA resource.
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*
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* \param[in] resource Pointer to the DMA resource
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* \param[in] type Callback function type
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*
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*/
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static inline void dma_enable_callback(struct dma_resource *resource,
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enum dma_callback_type type)
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{
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resource->callback_enable |= 1 << type;
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}
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/**
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* \brief Disable a callback function for a dedicated DMA resource.
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*
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* \param[in] resource Pointer to the DMA resource
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* \param[in] type Callback function type
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*
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*/
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static inline void dma_disable_callback(struct dma_resource *resource,
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enum dma_callback_type type)
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{
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resource->callback_enable &= ~(1 << type);
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}
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/**
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* \brief Register a callback function for a dedicated DMA resource.
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*
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* There are three types of callback functions, which can be registered:
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* - Callback for transfer complete
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* - Callback for transfer error
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* - Callback for channel suspend
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*
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* \param[in] resource Pointer to the DMA resource
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* \param[in] callback Pointer to the callback function
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* \param[in] type Callback function type
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*
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*/
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static inline void dma_register_callback(struct dma_resource *resource,
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dma_callback_t callback, enum dma_callback_type type)
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{
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resource->callback[type] = callback;
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}
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/**
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* \brief Unregister a callback function for a dedicated DMA resource.
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*
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* There are three types of callback functions:
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* - Callback for transfer complete
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* - Callback for transfer error
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* - Callback for channel suspend
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*
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* The application can unregister any of the callback functions which
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* are already registered and are no longer needed.
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*
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* \param[in] resource Pointer to the DMA resource
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* \param[in] type Callback function type
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*
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*/
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static inline void dma_unregister_callback(struct dma_resource *resource,
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enum dma_callback_type type)
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{
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resource->callback[type] = NULL;
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}
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/**
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* \brief Initializes DMA transfer configuration with predefined default values.
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*
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* This function will initialize a given DMA descriptor configuration structure to
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* a set of known default values. This function should be called on
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* any new instance of the configuration structure before being
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* modified by the user application.
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*
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* The default configuration is as follows:
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* \li Set the read start address as 0
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* \li Set the write start address as 0
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* \li Set buffer size as 1
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* \li Set beat size as byte
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* \li Enable the interrupt
|
|
* \li Enable the channel stops when buffer done
|
|
* \li Set next command address to 0
|
|
* \param[out] config Pointer to the configuration
|
|
*
|
|
*/
|
|
static inline void dma_descriptor_get_config_defaults(struct dma_descriptor *config)
|
|
{
|
|
/* Default read buffer size is set to 0 */
|
|
config->read_start_addr = 0;
|
|
/* Default write buffer size is set to 0 */
|
|
config->write_start_addr = 0;
|
|
/* Set beat size to one byte */
|
|
config->buffer_size = 1;
|
|
/* Enable transferred interrupt */
|
|
config->cmd.set_interrupt = 1;
|
|
/* Channel stops when buffer done */
|
|
config->cmd.last = 1;
|
|
/* Set next command to 0 */
|
|
config->cmd.next_addr = 0;
|
|
}
|
|
|
|
/**
|
|
* \brief Update DMA descriptor.
|
|
*
|
|
* This function can update the descriptor of an allocated DMA resource.
|
|
*
|
|
*/
|
|
static inline void dma_update_descriptor(struct dma_resource *resource,
|
|
struct dma_descriptor* descriptor)
|
|
{
|
|
resource->descriptor = descriptor;
|
|
}
|
|
|
|
/**
|
|
* \brief Reset DMA descriptor.
|
|
*
|
|
* This function will clear the DESCADDR register of an allocated DMA resource.
|
|
*
|
|
*/
|
|
static inline void dma_reset_descriptor(struct dma_resource *resource)
|
|
{
|
|
resource->descriptor = NULL;
|
|
}
|
|
|
|
void dma_get_config_defaults(struct dma_resource_config *config);
|
|
enum status_code dma_allocate(struct dma_resource *resource,
|
|
struct dma_resource_config *config);
|
|
enum status_code dma_add_descriptor(struct dma_resource *resource,
|
|
struct dma_descriptor* descriptor);
|
|
enum status_code dma_start_transfer_job(struct dma_resource *resource);
|
|
enum status_code dma_free(struct dma_resource *resource);
|
|
uint8_t dma_get_status(uint8_t channel);
|
|
uint8_t dma_get_interrupt_status(uint8_t channel);
|
|
void dma_clear_interrupt_status(uint8_t channel, uint8_t flag);
|
|
/** @} */
|
|
|
|
/**
|
|
* \page asfdoc_samb_dma_extra Extra Information for DMAC Driver
|
|
*
|
|
* \section asfdoc_samb_dma_extra_acronyms Acronyms
|
|
* Below is a table listing the acronyms used in this module, along with their
|
|
* intended meanings.
|
|
*
|
|
* <table>
|
|
* <tr>
|
|
* <th>Acronym</th>
|
|
* <th>Description</th>
|
|
* </tr>
|
|
* <tr>
|
|
* <td>DMA</td>
|
|
* <td>Direct Memory Access</td>
|
|
* </tr>
|
|
* <tr>
|
|
* <td>DMAC</td>
|
|
* <td>Direct Memory Access Controller </td>
|
|
* </tr>
|
|
* <tr>
|
|
* <td>CPU</td>
|
|
* <td>Central Processing Unit</td>
|
|
* </tr>
|
|
* </table>
|
|
*
|
|
*
|
|
* \section asfdoc_samb_dma_extra_dependencies Dependencies
|
|
* There are no dependencies related to this driver.
|
|
*
|
|
*
|
|
* \section asfdoc_samb_dma_extra_errata Errata
|
|
* There are no errata related to this driver.
|
|
*
|
|
*
|
|
* \section asfdoc_samb_dma_extra_history Module History
|
|
* An overview of the module history is presented in the table below, with
|
|
* details on the enhancements and fixes made to the module since its first
|
|
* release. The current version of this corresponds to the newest version in
|
|
* the table.
|
|
*
|
|
* <table>
|
|
* <tr>
|
|
* <th>Changelog</th>
|
|
* </tr>
|
|
* <tr>
|
|
* <td>Initial Release</td>
|
|
* </tr>
|
|
* </table>
|
|
*/
|
|
|
|
/**
|
|
* \page asfdoc_samb_dma_exqsg Examples for DMAC Driver
|
|
*
|
|
* This is a list of the available Quick Start Guides (QSGs) and example
|
|
* applications for \ref asfdoc_samb_dma_group. QSGs are simple examples with
|
|
* step-by-step instructions to configure and use this driver in a selection of
|
|
* use cases. Note that QSGs can be compiled as a standalone application or be
|
|
* added to the user application.
|
|
*
|
|
* - \subpage asfdoc_samb_dma_basic_use_case
|
|
*
|
|
* \note More DMA usage examples are available in peripheral QSGs.
|
|
*
|
|
* \page asfdoc_samb_dma_document_revision_history Document Revision History
|
|
*
|
|
* <table>
|
|
* <tr>
|
|
* <th>Doc. Rev.</td>
|
|
* <th>Date</td>
|
|
* <th>Comments</td>
|
|
* </tr>
|
|
* <tr>
|
|
* <td>A</td>
|
|
* <td>09/2015</td>
|
|
* <td>Initial release</td>
|
|
* </tr>
|
|
* </table>
|
|
*/
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif /* DMA_H_INCLUDED */
|