106 lines
3.7 KiB
C
106 lines
3.7 KiB
C
/*
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* This file is part of the MicroPython project, http://micropython.org/
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2019 Damien P. George
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#ifndef MICROPY_INCLUDED_STM32_MPU_H
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#define MICROPY_INCLUDED_STM32_MPU_H
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#if defined(STM32F7) || defined(STM32H7) || defined(MICROPY_HW_ETH_MDC)
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#define MPU_REGION_ETH (MPU_REGION_NUMBER0)
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#define MPU_REGION_QSPI1 (MPU_REGION_NUMBER1)
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#define MPU_REGION_QSPI2 (MPU_REGION_NUMBER2)
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#define MPU_REGION_QSPI3 (MPU_REGION_NUMBER3)
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#define MPU_REGION_SDRAM1 (MPU_REGION_NUMBER4)
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#define MPU_REGION_SDRAM2 (MPU_REGION_NUMBER5)
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#define MPU_CONFIG_DISABLE(srd, size) ( \
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MPU_INSTRUCTION_ACCESS_DISABLE << MPU_RASR_XN_Pos \
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| MPU_REGION_NO_ACCESS << MPU_RASR_AP_Pos \
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| MPU_TEX_LEVEL0 << MPU_RASR_TEX_Pos \
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| MPU_ACCESS_NOT_SHAREABLE << MPU_RASR_S_Pos \
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| MPU_ACCESS_NOT_CACHEABLE << MPU_RASR_C_Pos \
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| MPU_ACCESS_NOT_BUFFERABLE << MPU_RASR_B_Pos \
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| (srd) << MPU_RASR_SRD_Pos \
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| (size) << MPU_RASR_SIZE_Pos \
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| MPU_REGION_ENABLE << MPU_RASR_ENABLE_Pos \
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)
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#define MPU_CONFIG_ETH(size) ( \
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MPU_INSTRUCTION_ACCESS_DISABLE << MPU_RASR_XN_Pos \
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| MPU_REGION_FULL_ACCESS << MPU_RASR_AP_Pos \
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| MPU_TEX_LEVEL1 << MPU_RASR_TEX_Pos \
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| MPU_ACCESS_SHAREABLE << MPU_RASR_S_Pos \
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| MPU_ACCESS_NOT_CACHEABLE << MPU_RASR_C_Pos \
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| MPU_ACCESS_NOT_BUFFERABLE << MPU_RASR_B_Pos \
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| 0x00 << MPU_RASR_SRD_Pos \
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| (size) << MPU_RASR_SIZE_Pos \
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| MPU_REGION_ENABLE << MPU_RASR_ENABLE_Pos \
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)
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#define MPU_CONFIG_SDRAM(size) ( \
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MPU_INSTRUCTION_ACCESS_ENABLE << MPU_RASR_XN_Pos \
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| MPU_REGION_FULL_ACCESS << MPU_RASR_AP_Pos \
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| MPU_TEX_LEVEL1 << MPU_RASR_TEX_Pos \
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| MPU_ACCESS_NOT_SHAREABLE << MPU_RASR_S_Pos \
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| MPU_ACCESS_CACHEABLE << MPU_RASR_C_Pos \
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| MPU_ACCESS_BUFFERABLE << MPU_RASR_B_Pos \
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| 0x00 << MPU_RASR_SRD_Pos \
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| (size) << MPU_RASR_SIZE_Pos \
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| MPU_REGION_ENABLE << MPU_RASR_ENABLE_Pos \
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)
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static inline void mpu_init(void) {
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MPU->CTRL = MPU_PRIVILEGED_DEFAULT | MPU_CTRL_ENABLE_Msk;
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SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
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__DSB();
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__ISB();
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}
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static inline uint32_t mpu_config_start(void) {
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return disable_irq();
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}
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static inline void mpu_config_region(uint32_t region, uint32_t base_addr, uint32_t attr_size) {
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MPU->RNR = region;
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MPU->RBAR = base_addr;
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MPU->RASR = attr_size;
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}
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static inline void mpu_config_end(uint32_t irq_state) {
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__ISB();
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__DSB();
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__DMB();
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enable_irq(irq_state);
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}
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#else
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static inline void mpu_init(void) {
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}
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#endif
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#endif // MICROPY_INCLUDED_STM32_MPU_H
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