circuitpython/ports/litex
Scott Shawcroft 931c7c1c51
Add Bangle.js 2, JDI memory displays and ACeP epd
This 2-in-1 PR started with the goal of support the Bangle.js 2
smartwatch with *no USB*.
* Adds "secure" DFU build support with a committed private key.
* Adds 3-bit color support with one dummy bit for the JDI memory display
* Allows nrf boards to have a board_background_task() run in RUN_BACKGROUND_TASK.
  This is needed because the Bangle.js 2 uses the watchdog to reset.
* Renamed port_background_task() to port_background_tick() to indicate it
  runs on tick, not RUN_BACKGROUND_TASK.
* Marks serial connected when the display terminal is inited. This means
  that safe mode messages show up on the display.

ACep, 7-color epaper displays also pack 3 bits in 4. So, I added that
support as well.
* Adds 3-bit ACeP color support for 7-color e-paper displays. (Not
  watch related but similar due to color depth.)
* Allows a refresh sequence instead of a single int command. The 7" ACeP
  display requires a data byte for refresh.
* Adds optional delay after resetting the display. The ACeP displays
  need this. (Probably to load LUTs from flash.)
* Adds a cleaning phase for ACeP displays before the real refresh.

For both:
* Add dither support to Palette.
* Palette no longer converts colors when set. Instead, it caches
  converted colors at each index.
* ColorConverter now caches the last converted color. It should make
  conversions faster for repeated colors (not dithering.)
2023-02-15 15:03:40 -08:00
..
boards/fomu Use MP_WEAK for default board.c routines 2022-09-08 07:36:50 -04:00
common-hal cyw43 basic gpio support, hwaddr in boot_out 2022-09-28 10:06:33 -05:00
hw run code formatting script 2021-03-15 19:27:36 +05:30
supervisor litex: Enable -Werror=missing-prototypes 2021-11-12 19:13:51 -06:00
background.c Add Bangle.js 2, JDI memory displays and ACeP epd 2023-02-15 15:03:40 -08:00
background.h supervisor: factor supervisor_background_tasks from sundry ports 2020-07-15 11:49:44 -05:00
crt0-vexriscv.S ports: litex: add port and fomu board 2020-03-31 09:40:38 +08:00
irq.h run code formatting script 2021-03-15 19:27:36 +05:30
Makefile Merge pull request #7247 from tannewt/picow_web_workflow 2022-11-28 14:19:42 -08:00
mpconfigport.h run code formatting script 2021-03-15 19:27:36 +05:30
mpconfigport.mk Change I2C terminology from "peripheral" to "target" 2022-08-09 13:13:19 -04:00
mphalport.c Start of USB host API 2022-03-07 18:07:25 -08:00
mphalport.h Merge tag 'v1.17' into merge-1.17 2021-10-15 08:20:54 -05:00
qstrdefsport.h Merge MicroPython 1.13 into CircuitPython 2021-05-04 18:06:33 -07:00
README.rst Update the supported ports 2020-03-31 18:27:55 -07:00

LiteX (FPGA)
============

`LiteX <https://github.com/enjoy-digital/litex>`_ is a Python-based System on a Chip (SoC) designer
for open source supported Field Programmable Gate Array (FPGA) chips. This means that the CPU
core(s) and peripherals are not defined by the physical chip. Instead, they are loaded as separate
"gateware". Once this gateware is loaded, CircuitPython can be loaded on top of it to work as
expected.

Installation
-------------

You'll need ``dfu-util`` to install CircuitPython on the Fomu.

Make sure the foboot bootloader is updated. Instructions are here: https://github.com/im-tomu/fomu-workshop/blob/master/docs/bootloader.rst

Once you've updated the bootloader, you should know how to use ``dfu-util``. It's pretty easy!

To install CircuitPython do:

.. code-block:: shell

  dfu-util -D adafruit-circuitpython-fomu-en_US-<version>.dfu

It will install and then restart. CIRCUITPY should appear as it usually does and work the same.