circuitpython/ports/esp8266/modules
Yonatan Goldschmidt bc4f8b438b extmod/moduwebsocket: Refactor `websocket` to `uwebsocket`.
As mentioned in #4450, `websocket` was experimental with a single intended
user, `webrepl`. Therefore, we'll make this change without a weak
link `websocket` -> `uwebsocket`.
2019-02-14 00:35:45 +11:00
..
_boot.py ports: Make new ports/ sub-directory and move all ports there. 2017-09-06 13:40:51 +10:00
apa102.py ports: Make new ports/ sub-directory and move all ports there. 2017-09-06 13:40:51 +10:00
dht.py esp8266/modules: Move dht.py driver to drivers/dht directory. 2018-01-31 18:11:06 +11:00
ds18x20.py all: Update Makefiles and others to build with new ports/ dir layout. 2017-09-06 14:09:13 +10:00
flashbdev.py ports: Make new ports/ sub-directory and move all ports there. 2017-09-06 13:40:51 +10:00
inisetup.py esp8266/main: Activate UART(0) on dupterm for REPL before boot.py runs. 2019-01-16 17:24:23 +11:00
neopixel.py ports: Make new ports/ sub-directory and move all ports there. 2017-09-06 13:40:51 +10:00
ntptime.py esp8266/modules/ntptime.py: Remove print of newly-set time. 2018-06-05 14:30:35 +10:00
onewire.py all: Update Makefiles and others to build with new ports/ dir layout. 2017-09-06 14:09:13 +10:00
port_diag.py ports: Make new ports/ sub-directory and move all ports there. 2017-09-06 13:40:51 +10:00
upip.py all: Update Makefiles and others to build with new ports/ dir layout. 2017-09-06 14:09:13 +10:00
upip_utarfile.py all: Update Makefiles and others to build with new ports/ dir layout. 2017-09-06 14:09:13 +10:00
webrepl.py extmod/moduwebsocket: Refactor `websocket` to `uwebsocket`. 2019-02-14 00:35:45 +11:00
webrepl_setup.py esp8266/modules/webrepl_setup: Fix first-time enable of WebREPL. 2017-11-30 10:54:33 +11:00
websocket_helper.py ports: Make new ports/ sub-directory and move all ports there. 2017-09-06 13:40:51 +10:00