57 lines
2.1 KiB
C
57 lines
2.1 KiB
C
/*
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* Copyright 2018 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include "evkmimxrt1050_flexspi_nor_config.h"
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/* Component ID definition, used by tools. */
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#ifndef FSL_COMPONENT_ID
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#define FSL_COMPONENT_ID "platform.drivers.xip_board"
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#endif
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/*******************************************************************************
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* Code
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******************************************************************************/
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#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
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#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
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__attribute__((section(".boot_hdr.conf")))
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#elif defined(__ICCARM__)
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#pragma location = ".boot_hdr.conf"
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#endif
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const flexspi_nor_config_t qspiflash_config = {
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.memConfig =
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{
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.tag = FLEXSPI_CFG_BLK_TAG,
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.version = FLEXSPI_CFG_BLK_VERSION,
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.readSampleClkSrc = kFlexSPIReadSampleClk_ExternalInputFromDqsPad,
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.csHoldTime = 3u,
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.csSetupTime = 3u,
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.columnAddressWidth = 3u,
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// Enable DDR mode, Wordaddassable, Safe configuration, Differential clock
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.controllerMiscOption =
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(1u << kFlexSpiMiscOffset_DdrModeEnable) | (1u << kFlexSpiMiscOffset_WordAddressableEnable) |
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(1u << kFlexSpiMiscOffset_SafeConfigFreqEnable) | (1u << kFlexSpiMiscOffset_DiffClkEnable),
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.sflashPadType = kSerialFlash_8Pads,
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.serialClkFreq = kFlexSpiSerialClk_133MHz,
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.sflashA1Size = 64u * 1024u * 1024u,
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.dataValidTime = {16u, 16u},
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.lookupTable =
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{
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// Read LUTs
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FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0xA0, RADDR_DDR, FLEXSPI_8PAD, 0x18),
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FLEXSPI_LUT_SEQ(CADDR_DDR, FLEXSPI_8PAD, 0x10, DUMMY_DDR, FLEXSPI_8PAD, 0x06),
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FLEXSPI_LUT_SEQ(READ_DDR, FLEXSPI_8PAD, 0x04, STOP, FLEXSPI_1PAD, 0x0),
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},
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},
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.pageSize = 512u,
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.sectorSize = 256u * 1024u,
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.blockSize = 256u * 1024u,
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.isUniformBlockSize = true,
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};
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#endif /* XIP_BOOT_HEADER_ENABLE */
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